United States Patent [19]
`Wuu et al.
`
`111111111111111111111111111111111111111111111111111111111111111111111111111
`US005547892A
`[11] Patent Number:
`[45] Date of Patent:
`
`5,547,892
`Aug. 20, 1996
`
`[54] PROCESS FOR FORMING STACKED
`CONTACTS AND METAL CONTACTS ON
`STATIC RANDOM ACCESS MEMORY
`HAVING THIN FILM TRANSISTORS
`
`[75]
`
`Inventors: Shou-Gwo Wuu; Mong-Song Liang;
`Chung-Hui Su; Chen-Jong Wang, all
`of Hsin-Chu, Taiwan
`
`[73] Assignee: Taiwan Semiconductor
`Manufacturing Company, Hsin-Chu,
`Taiwan
`
`[21] Appl. No.: 429,725
`
`[22] Filed:
`
`Apr. 27, 1995
`
`Int. Cl.6
`..•...••••.••.•••••.•.•..•.•. H01L 21n0; HOIL 27/00
`[51]
`[52] U.S. Cl •................................. 437/52; 437/47; 437/60;
`437/40
`[58] Field of Search .................................. 437/47-48, 52,
`437/40 TFT, 40-41, 60, 915, 195, 101,
`192; 257/903-904, 393, 67, 385
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`4,980,732 12/1990 Okazawa ................................. 257/369
`7/1991 Yamanaka et al ...................... 257/380
`5,034,797
`5,196,233
`311993 Chan et al ................................ 437/52
`211994 Manning ................................... 437/41
`5,286,663
`Primary Examiner-H. ley Tsai
`Attorney, Agent, or Firm-George 0. Saile
`[57]
`ABSTRACT
`
`A method for fabricating a novel plug structure for low
`resistance ohmic stacked contacts and at the same time
`forming metal contacts to devices on a SRAM cell was
`achieved. The method involved forming electrically conduc(cid:173)
`tive plugs in the stacked contact openings to form ohmic
`connections between a P+ doped polysilicon layer and aN+
`doped polysilicon layer and thereby increasing the on cur(cid:173)
`rent (I0 n) of the SRAM cell. The electrical conductive plugs
`are also simultaneously formed in metal contact openings to
`devices areas elsewhere on the substrate.
`
`12 Claims, 3 Drawing Sheets
`
`l8'
`
`18
`
`22
`18
`16~~~~~~~~~~~~~~:=~LL1===~---16
`12
`
`10
`
`P-
`
`14(G1)
`
`14(G2)
`
`Petitioner Nanya Technology Corp. - Ex. 1006, p. 1
`
`

`
`U.S. Patent
`
`Aug. 20, 1996
`
`Sheet 1 of 3
`
`5,547,892
`
`BL1
`
`8L2
`
`FIG. 1
`
`Prior Art
`
`Vss
`
`14(G1)
`
`14(G2)
`
`16
`12
`
`10
`
`FIG. 2 -Prior-Art
`
`1 4 ( G1 )
`
`16
`12
`
`10
`
`FIG. 3 - Prior Art
`
`Petitioner Nanya Technology Corp. - Ex. 1006, p. 2
`
`

`
`U.S. Patent
`
`Aug. 20, 1996
`
`Sheet 2 of 3
`
`5,547,892
`
`16
`12
`
`10
`
`14(G1)
`14(G2)
`FIG. 4 -Prior Art
`
`22
`18
`16
`12
`
`10
`
`14(G1)
`1.4(G2)
`FIG. 5 -Prior Art
`
`P1
`\ 15
`18'
`
`16
`12
`
`10
`
`14(G1)
`FIG. 6
`
`P-
`
`14(G2)
`
`Petitioner Nanya Technology Corp. - Ex. 1006, p. 3
`
`

`
`U.S. Patent
`
`Aug. 20, 1996
`
`Sheet 3 of 3
`
`5,547,892
`
`18'
`
`4
`
`18
`
`16
`12
`
`10
`
`FIG.
`
`14(G1)
`7
`
`18'
`
`18
`
`22
`18
`16
`12
`
`1 0
`
`14(G2)
`
`18 22 7
`{
`
`22
`
`16
`
`22
`
`16
`
`FIG.
`
`14(G1)
`8
`
`14(G2)
`
`22
`18
`1 6 "'-J:::~~ _,....,.._ ~~ ~~- ~L....-1
`~~~~~~~~~~~~C===j--16
`12
`
`~---1-24
`22
`
`10
`
`14(G1)
`FIG. 9
`
`14(G2)
`
`Petitioner Nanya Technology Corp. - Ex. 1006, p. 4
`
`

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`5,547,892
`
`1
`PROCESS FOR FORMING STACKED
`CONTACTS AND METAL CONTACTS ON
`STATIC RANDOM ACCESS MEMORY
`HAVING THIN FILM TRANSISTORS
`
`BACKGROUND OF THE INVENTION
`
`5
`
`2
`After completing portions of the word line and bit line
`structure on substrate 10, the latch circuits of the SRAM
`memory cells are formed having the P-channel TFTs on
`portions of the substrate within the array of word and bit
`lines. Referring now to FIG. 2, the TFf gate electrodes G1
`and G2 are patterned from an N+ doped third polysilicon
`layer 14. A thin gate oxide 16 is then deposited over the gate
`electrodes, also shown in FIG. 2. A contact opening 2 is then
`formed in the gate oxide to the second gate G2 (see FIG. 3)
`10 by photoresist masking and etching. A fourth polysilicon
`layer 18 is then deposited and patterned to form the TFT
`channel layer 18 over the G1 gate electrode and makes
`contact to the G2 gate electrode in opening 2, as shown in
`FIG. 4. The layer 18 is then implanted with a P-type dopant
`through a patterned photoresist mask to form the source and
`drain areas of the P-channel TFT and at the same time
`forming an electrical connection from the drain 20 of the
`TFT, which is also the node point Q1 (FIG. 1) to the gate G2.
`Now as shown in FIG. 5, a second insulating layer 22 is
`20 deposited on the SRAM structure. A second opening is made
`in layer 22 for the first metal contact plugs. The metal plug
`is usually formed from a barrier metal such as tungsten. A
`first metal layer 26 is then deposited and patterned to form
`the first level of interconnections on the SRAM integrated
`25 circuit. Although the metal contact is shown adjacent to the
`gate G2 contact for clearer visualization, it should be under(cid:173)
`stood that the metal contact plug is formed to any area on the
`substrate where an electrical contact is required.
`There are a number of concerns with the prior art structure
`30 and process which degrade the performance and reliability
`of the SRAM. For example, during the etching of the contact
`opening 2, photoresist is in direct contact with the gate oxide
`and can introduce contaminants such as sodium into the
`oxide resulting in unstable device properties. And still
`35 another serious problem is the p+fN+ junction formed by the
`stacked contact between the doped polysilicon layers 14 and
`18 in the contact opening 2. Although the dopant concen(cid:173)
`trations are high, the junctions still have diode characteristic
`which reduce the on current Cion) when the SRAM cell is
`40 switches to the opposite state. Ideally, one would prefer a
`low resistance ohmic stacked contact.
`Therefore, there is a strong need in the semiconductor
`industry for improved structures and processes for making
`thin film transistors for SRAMs and other integrate circuits
`that do not have the above problems, and is cost effective.
`
`SUMMARY OF THE INVENTION
`
`It is a principle object of this invention to provide a
`process for simultaneously forming low resistance ohmic
`N+tp+ stacked contacts and metal contacts on SRAMs
`having thin film transistors (TFT), and thereby improving
`the SRAM performance by increasing the on current and the
`Oaiio.ff) ratio.
`It is another object of this invention to provide a process
`that avoids contamination of the TFT FET gate oxide and
`thereby improve the stability of the thin film transistor.
`It is still another object of this invention to provide this
`improved low resistance ohmic stacked contacts and metal
`contacts using a reduced mask set, and thereby provide a
`cost effective manufacturing process.
`In accordance with the objects of this invention a method
`for fabricating a novel plug structure on a SRAM cell is
`65 described. The method forms the stacked contact and the
`metal contact simultaneously by merging the process steps.
`The method starts by providing a P-type (boron) doped
`
`60
`
`15
`
`45
`
`(1) Field of the Invention
`The present invention relates to integrated circuits on
`semiconductor substrates, and more particularly to the fab(cid:173)
`rication of ohmic contacts relating to Thin Film Transistors
`(TFT) on Static Random Access Memory (SRAM).
`(2) Description of the Prior Art
`Random Access Memory (RAM) is used extensively in
`the electronics industry for storing data for digital systems,
`such as computers. The major types of RAMs, are the
`Dynamic Random Access Memory (DRAM) and the Static
`Random Access Memory (SRAM). The individual DRAM
`cells, composed of a single transistor and capacitor store
`information on the capacitors as charge. In general the
`DRAM is slower than the SRAM and needs to be refreshed
`periodically to maintain the charge on the capacitor, but is
`considerably cheaper to produce per bit of information
`stored than the SRAM. The SRAM cell, on the other hand,
`is usually composed of six transistors and functions as a
`static latch or flip flop circuit, does not have to be refreshed
`and is much faster than the DRAM. Because of its speed the
`SRAM is ideal for use as a cache or buffer memory to speed
`up the system performance.
`A circuit schematic for a typical six-transistor CMOS
`SRAM cell is shown in FIG. 1. Only one of the array of
`many cells is shown in FIG. 1. The trend in recent years is
`to fabricate the CMOS SRAMs using a P channel Thin Film
`Transistor (TFT) for the P1 and P2 transistors to reduce the
`size of the cell and the cost of the chip. For example, T.
`Okazawa, U.S. Pat. No. 4,980,732 teaches a method for
`making TFTs with lower off currents. In that patent the FET
`drain side of charmel is off set from the gate electrode to
`reduce the current. Briefly, the SRAM cell functions as
`follows. Referring to FIG. 1, an applied gate voltage on the
`word line WL switch on the pass transistors WN1 and WN2.
`The voltage at the nodes Q1 and Q2 between the two pairs
`of CMOS transistor P1, N1 and P2, N2, are sensed on the bit
`lines BL1 and BL2 during the read cycle to determine the
`state of the SRAM latch. During the write cycle an
`impressed voltage on the bit lines can switch the voltage
`levels on the latch and thereby change the stored binary data
`representing one's and zero's.
`However, during fabrication of the SRAM cell the nodes 50
`Q1 and Q2 between each pair of CMOS P-channel and
`N-channel FETs must, respectively, make good electrical
`contact to the gate electrodes G2 and G1, as shown in the
`circuit schematic of FIG. 1. Unfortunately, when the P-chan(cid:173)
`nel TFf are built on the semiconductor substrate by methods 55
`of the prior art, a number of additional processing problems
`occur that limit the performance and reliability of the
`SRAM.
`These problems are best understood by referring to the
`conventional prior art process for forming the P-type TFT, as
`shown in schematic cross-sectional views in FIGS. 2
`through 5. In order to simplify the discussion only portions
`of the substrate for the SRAM cell is shown on which the
`P-channel TFT is built. The other circuit elements, such as
`the WN1, WN2 FETs and the word line formed from a first
`polysilicon layer and the bit lines formed from a second
`polysilicon layer are not shown in FIGS. 2 through 5.
`
`Petitioner Nanya Technology Corp. - Ex. 1006, p. 5
`
`

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`5,547,892
`
`3
`single crystal semiconductor substrate having device areas
`on the substrate surface, and surrounded by electrically
`isolating field oxide (FOX) areas. N-channel field effect
`transistors (pass transistor) having gate electrodes and inter(cid:173)
`connecting word lines are formed from a first polysilicon 5
`layer in the device areas. Source/drain areas are then formed
`and a second polysilicon layer N-doped is patterned to
`contact one of the source/drain area on each pass transistor.
`Two P-channel thin film transistor (TFT) are then formed on
`a first insulating layer in each cell area of the SRAM. The 10
`TFT are formed by depositing a third polysilicon layer
`doped N+ with an N type dopant, such as arsenic or
`phosphorus, and patterned to form the gate electrodes of the
`two P-channel thin film transistors. A second insulating layer
`is deposited to form the gate oxide over the gate electrodes. 15
`A lightly N- doped amorphous polysilicon layer is deposited
`over the gate oxide layer and then selectively implanted with
`a P type impurity, such as boron, to form the TFT source/
`drain areas adjacent to the gate electrodes. The amorphous
`silicon layer is mask from P doped implantation over the 20
`areas where the two TFT are to be formed. Elsewhere over
`the gate electrodes the amorphous silicon layer is p+ doped.
`The amorphous silicon layer is patterned by masking and
`etching to form the lightly N- doped FET silicon channel
`over portion of each of the gate electrode having p+ source/ 25
`drains. The patterned P+ conducting silicon layer of each
`TFT also extends over a portion of the other TFT gate
`electrode, and provide a means of forming a stacked contact
`to connect the drain of one TFT to the gate electrode of the
`other TFT. The stacked contacts and the metal contact are 30
`no~ formed simultaneously by first etching openings in the
`patterned P+ amorphous silicon layer that extends over the
`gate electrode areas of each TFT. A third insulating layer is
`deposited and contact opening are anisotropically etched in
`the insulator over and aligned to the openings in the amor- 35
`pho~s silicon layer. The openings are etched to the P+ doped
`portion of the surface of the amorphous silicon layer and
`further, the second insulating layer (gate oxide) is etched in
`the amorphous silicon layer openings to the surface of the
`~+.third polysilicon layer. The above masking and etching 40
`IS simultaneously used to form the metal contact openings to
`the other device areas for electrical interconnections
`thereby reducing the masking levels by one masking ste~
`over the prior art. Conducting plugs are formed in the
`openings, for example, by depositing a refractory metal, 45
`such as tungsten, and etching back to the surface of the third
`insulating layer. The SRAM is then completed to the first
`metal wiring level by depositing a metal, such as aluminium
`~d patterning to form the interconnections. The metal plug
`m th~ stacked contact opening shorts the p+fN+ junction 50
`forrrung a good low resistance ohmic contact.
`
`4
`ohmic stacked contacts and a metal contacts formed simul(cid:173)
`taneously.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`The present invention relates to the formation of an
`improved stacked contact on a SRAM cell having P-channel
`thin film transistors (TFT) and the simultaneous formation
`of metal contacts by merging two of the masking steps.
`However, it should be well understood by those killed in the
`art that the method can be equally applied to other semi(cid:173)
`conductor integrated circuits using P-channel TFT where
`low resistance ohmic stacked contacts are required between
`doped silicon layers having different conductivity type
`dopants.
`To better understand the present invention for making the
`novel plug structure, a brief description is given of the
`fabrication of a SRAM cell. The complete SRAM cell is not
`shown in the cross section views of the FIGS. 6-9, but the
`device elements are depicted in the electrical schematic of
`FIG. 1. The SRAM is formed on a semiconductor substrate
`such as on a p- doped single crystal silicon substrate. Devic~
`areas are formed for an array of N-channel pass transistors.
`Two of the transistors WN1 and WN2 are depicted in the
`SRAM cell of FIG. 1. Typically, the electrically isolated
`device areas are formed by selectively oxidizing the regions
`around the device areas, for example, by using a conven(cid:173)
`tional LOCal Oxidation of Silicon (LOCOS) process. The
`pass transistors are formed by growing a gate oxide on the
`device areas and then using a patterned first polysilicon layer
`to form the field effect transistor gate electrodes and the
`word lines ( one word line WL is depicted in FIG. 1) .
`Source/drain are1!-s are implanted adjacent to the gate elec(cid:173)
`trodes and the gate electrodes are electrical insulated from a
`second polysilicon layer which is then patterned to form the
`bit lines (two bit lines BLl and BL2 are depicted also in FIG.
`1) th~t contact one of the two source/drain areas of the pass
`transistors WN1 and WN2. The other source/drain areas of
`each transistor is later connect to the nodes Q1 and Q2 of the
`SRAM latch portion of the circuit. The latch circuit is
`formed from CMOS FET devices consisting of two P-chan(cid:173)
`nel thin film transistors P1 and P2 and two N-channel
`transistors N1 and N2 having gate electrodes G1 and G2, as
`depicted in FIG. 1. The gate electrodes of the N1 and N2
`transistors, also referred to as driver. transistors, are also
`formed from the same first polysilicon layer as the pass
`transistor gate electrodes. The second polysilicon layer is
`used to form the driver transistor N1 and N2 source ground
`plate to provide the V ss ground contact, as indicated in FIG.
`1.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The objects and other advantages of the invention will
`become more apparent in the preferred embodiment when
`read in conjunction with the following drawings.
`FIGS. 1 shows an electrical schematic of a prior art six
`transistor SRAM cell.
`FIGS. 2 through 5 show schematic cross sectional views
`of the prior art for a portion of a SRAM cell having a reverse
`P-channel thin film transistor (TFT) and a conventional
`p+fN+ stacked contact with p+fN+ junctions.
`FIGS. 6 through 9 show schematic cross sectional views
`for a portion of a SRAM cell having a P-channel thin film
`transistor (TFT) of this invention having low resistance
`
`Referring now to FIGS. 6 through 9, the embodiment of
`this invention is described in detail for the formation of the
`55 P-channel thin film transistors and more specifically the
`method for making the novel plug structure and the metal
`contacts on the latch portion of the SRAM circuit.
`Referring first to FIGS. 6, shown in schematic cross
`sectional view is a portion of the p- silicon substrate 10 in
`the SRAM cell region. Shown is one of the P-channel thin
`film transistor (TFT) P1 and a portion of the gate electrode
`G2 of the second TFT P2 . Also shown is a portion on the
`right side of the substrate 10 where a metal contact will be
`made to one of the substrate to contact a previously fo~ed
`65 device in the device area. The device in the substrate is not
`shown to simplify the drawing. A first insulating 12 formed
`on substrate 10 by an earlier process step provides electrical
`
`60
`
`Petitioner Nanya Technology Corp. - Ex. 1006, p. 6
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`

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`5,547,892
`
`5
`
`10
`
`15
`
`5
`isolation for the TFf from the substrate 10. The method of
`making the P-channel TFfs having the novel plug process is
`now described starting with FIG. 6.
`Still referring to FIG. 6, a third polysilicon layer 14 is
`deposited on the substrate and patterned using conventional
`photolithographic methods and plasma etching .to form the
`gate electrodes G1 and G2 for the two thin film transistors
`(TFf). The gate electrodes formed from the third polysilicon
`layer contact the gate electrodes of the driver transistors
`formed from the first polysilicon layer by means of a stacked
`contact. The layer 14 is preferable deposited by low pressure
`chemical vapor deposition (LPCVD) using, for example, a
`reactant gas containing silane (SiH4 ), and the preferred
`thickness of polysilicon layer 14 is between about 300 to
`1500 Angstroms. The polysilicon layer 14 is then doped with
`anN type dopant such as arsenic (As 75
`) or phosphorus (P31
`)
`by ion implantation or alternatively, the layer 14 can be in
`situ doped by adding a dopant, such as phosphine (PH3)
`during the CVD deposition. The preferred dopant concen(cid:173)
`tration in layer 14 is between about 1.0 E 18 to 1.0 E 20
`atomslcm3
`.
`The polysilicon layer 14 is then patterned using conven(cid:173)
`tional photolithographic techniques and anisotropic plasma
`etching to define the gate electrode regions G1 and G2, as
`shown in FIG. 6. The preferred anisotropic etching, for
`example, can be performed in a reactive ion etcher (RIE) 25
`using a gas mixture, for example, containing a chlorine
`containing gas species and using a carrier gas such as argon.
`A second insulating layer 16, also shown in FIG. 6, is
`deposited next over the gate electrodes G1 and G2 formed
`from the patterned layer 14. This layer 16 serves as the gate 30
`oxide for the thin film transistors. The preferred deposition
`is carried out in a high temperature (about 800° C.) LPCVD
`system using a gas mixture of, for example, composed of
`dichloromethane (SiH2Cl2 ) and nitrous oxide (N20). The
`gate oxide is relatively thin. For example, the preferred 35
`thickness of the second insulating layer 16 is between about
`50 to 500 Angstroms.
`A relatively thin amorphous silicon layer 18, also shown
`in FIG. 6, is then deposited over the gate oxide layer 16 to
`provide a channel layer for the thin film transistors. The
`amorphous silicon layer is usually achieved by a low tem(cid:173)
`perature CVD deposition For example, the amorphous layer
`18 is typically deposited by LPCVD using a reactant gas
`containing silane (SiH4 ) or a higher hydride of silicon, such
`as disilane (Si2H6 ), and having a preferred deposition tem(cid:173)
`perature is in a range of between about 450° to 560° C. The
`preferred thickness of layer 18 is between about 50 to 800
`Angstroms. Typically, the amorphous silicon layer is lightly
`doped with an N-type dopant, such as arsenic (As) or
`phosphorus (P) to prevent inversion when the P-channel
`TFf is in a nonconducting state (off) and to provide for the
`P+IN- junctions between the TFr FET channel and the
`source/drain areas. The N type dopant is typically achieved
`by ion implantation of arsenic (As75
`) of phosphorus (P31
`)
`and the preferred concentration in layer 18 is typically
`between about 1.0 E 16 to 1.0 E 18 atoms/cm3
`.
`One important advantage of this invention over the prior
`art, is that contact openings are not formed in the TFf gate
`oxide, as shown in FIG. 3 for the prior art. This eliminates
`the exposure of the gate oxide to a photoresist masking
`which is known in the semiconductor industry to contami(cid:173)
`nated the gate oxide. This contamination, such as sodium
`(Na), can create device electrical instabilities when the
`·
`circuit is powered on.
`Still referring to FIG. 6, A patterned photoresist implant
`mask 15 is now formed on layer 18 to mask portions of layer
`
`6
`18 over the gate electrodes where the channels for the TFrs
`are required. The mask portion for one of the TFf having the
`gate electrode G1 is shown in FIG. 1 labeled 18'. The
`amorphous silicon layer 18 is now subjected to an ion
`implantation using a P type dopant, for example, using a
`
`boronll (B 11 ). This ion implant forms the source/drain
`doped regions of the P-channel TFfs, and also provide a
`conducting layer elsewhere on the substrate. The implant
`mask 15 is shown for only the TFr having the gate electrode
`labeled G1 in FIG. 6. The cross section through the second
`gate electrode G2 is through an area not having a channel
`region and therefore has a p+ doped portion of layer 18
`extending over the gate electrode G2. A typical boron (Bll)
`dopant concentration in layer 18, after ion implantation, is
`between about 1.0 E 18 to 1.0 E 20 atoms/cm3
`.
`Referring now to FIG. 7, the next sequence of process
`steps are shown. Using a photoresist mask (not shown) and
`plasma etching, the amorphous silicon layer 18 is patterned
`to define the P+ doped conducting stripes, also labeled 18 in
`FIG. 7. The patterning step also defining the channel width
`20 over the TFr gate electrodes. The channel layer 18' over the
`gate electrode G1 is shown in FIG. 7. The patterned P+
`doped conducting stripe also extends over the a portion of
`the G2 gate electrode of the other TFf, as shown in FIG. 7.
`An important feature of the invention, is the simultaneously
`formation of the opening 4 in layer 18 to the gate oxide layer
`16 over a portion of gate electrode G2. The etching is
`preferable done in a reactive ion etcher or other high plasma
`density etcher using a selective and anisotropic etch. For
`example, a gas Inixture containing chlorine (Cl2) or dichlo-
`rodiftuoromethane (CC12F2 ) with a carrier gas, such as argon
`(Ar), can be used.
`A third insulating layer 22 is deposited over the patterned
`layer 18, as also shown in FIG. 7. Preferably the insulating
`layer is composed of a low flow glass to provide a leveling
`effect for planarizing the surface. For example, layer 22 can
`be deposited at between about 8000 to 13000 Angstroms by
`low pressure chelnical vapor deposition (LPCVD) reactor by
`decomposing a tetraethosiloxane (TEOS) while introducing
`dopants such as phosphine (PH3) and diborane(6) (B2H6 ) to
`form the BPTEOS glass. The glass of silicon oxide is then
`40 annealed for about between 15 to 60 minutes at a tempera(cid:173)
`ture of between about 800° to 900° C. to level the glass layer
`22. The layer also serves as a barrier layer to sodium (Na)
`contarnination.
`Referring now to FIG. 8, a second opening 6 is form in the
`third insulating layer 22, by conventional photolithog!aphic
`techniques an anisotropic etching. The second opening is
`aligned over and is larger in size (width) than the opening 4
`in the amorphous silicon layer 18. The preferred etching is
`50 accomplished in a reactive ion etcher using an etch gas
`mixture that has a high etch rate selectivity of silicon oxide
`to silicon. For example, the etching can be accomplished in
`a carbon tetrafluoride (CF4) containing a hydrogen gas (H2)
`or alternatively in a gas Inixture containing triftuoromethane
`(CHF3). The preferred etch rate selectivity of silicon oxide
`to silicon being greater than about 30 to 1.
`As shown in FIG. 8, the opening 6 in layer 22 (BPTEOS)
`is etched to the surface of the amorphous silicon layer 18 and
`then further etched/utilizing the high selective etch masking
`60 advantage of layer 18 to etch the gate oxide 16 in opening
`4 to the surface of the gate electrode layer 14 (G2), which
`itself provides an excellent etch stop, being composed of the
`third polysilicon layer 14. This then forms the stacked
`contact opening to the p+ and N+ layers 18 and 14 respec-
`tively.
`Simultaneously, and using the same masking level a
`second set of openings 7 are etched in the insulating layer 22
`
`45
`
`55
`
`65
`
`Petitioner Nanya Technology Corp. - Ex. 1006, p. 7
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`

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`5,547,892
`
`7
`to from the metal contact openings to the other device on the
`substrate in the device areas. This as mention earlier elimi(cid:173)
`nates one of the masking levels from the prior art.
`Referring now to FIG. 9, The novel plug structure is
`completed by depositing a metal layer 24 to conformally fill 5
`the openings 6 and 7 and thereby making an electriclil
`contact between the P+ and N+ layers 14 and 18 in opening
`6 and simultaneously making electrical contact to the ter(cid:173)
`minals of the other devices on the substrate in openings 7.
`The metal layer 24 is then etched back with plasma CF4 gas 10
`to form the electrically isolated conductive plugs 24 in each
`contact opening, as shown in FIG. 9. The conductive plugs
`24 are preferably composed of a refractory metal, such as
`tungsten (W), which also functions as a barrier layer to metal
`penetration from the first metal layer into the silicon contacts 15
`on the substrate. The tungsten can be deposited by several
`methods, such as CVD, physical evaporation, sputtering and
`the likes, but is preferably accomplished by using CVD and
`the thermal decomposition of tungsten hexafluoride (WF6).
`FIG. 9 shows the SRAM completed up to the first level metal 20
`26. For example, an aluminium layer 26 can be deposited
`and then patterned by photoresist masking an plasma etching
`to form the first metal interconnect level.
`To simplify the description of the invention FIGS. 6
`through 9 show the formation of only one electrical con- 25
`nection between the drain (node Q1 FIG. 1) of the first TFT
`having gate electrode G1 to the gate G2 of the second TFT.
`However, it should be noted that during the processing a
`second connection is made from the drain (node Q2 FIG. 1)
`of the second TFT to the gate electrode G1 of the first TFT. 30
`Both connections are made through stacked contacts
`between the p+ and N+ layers 18 and 14 using metal plugs
`that electrically short the p+fN+ junction and provide a very
`low resistance ohmic contact, which is a significant
`improvement over the stacked contacts of the prior art of 35
`FIGS. 2 through 5.
`While the invention has been particularly shown and
`described with reference to the preferred embodiments
`thereof, it will be understood by those skilled in the art that
`various changes in form and details may be made without 40
`departing from the spirit and scope of the invention. For
`example, although
`the embodiment describes making
`improved stacked contacts for SRAM circuits, it should also
`be understood that these improved ohmic contacts can also
`be made on other semiconductor integrated circuits that 45
`requiring low resistance ohmic contacts between p+ to N+
`silicon layers and requiring also metal contacts to other
`devices on the same substrate.
`What is claimed is:
`1. A method for fabricating a plug structure for stacked 50
`contacts and metal contacts on a Static Random Access
`Memory (SRAM) cell having thin film transistors, compris(cid:173)
`ing the steps of:
`providing a semiconductor substrate having device areas
`and field oxide areas and further having field effect
`transistors (FETs) and word lines formed from a first
`polysilicon layer, and Vss ground plates and bit lines
`formed from a second polysilicon layer, and further
`comprising of;
`depositing a first insulating layer on said substrate;
`depositing a third polysilicon layer on said first insulating
`layer, said third polysilicon layer doped with anN-type
`dopant;
`patterning said third polysilicon layer and thereby form- 65
`ing first and second gate electrodes for first and second
`thin film transistors of said SRAM cell;
`
`8
`depositing a second insulating layer and thereby forming
`a gate oxide on said first and second gate electrodes;
`depositing an N type amorphous silicon layer on said
`second ipsulating layer;
`masking portions of said amorphous silicon layer over
`said first and second gate electrodes and ion implanting
`a P-type conductive dopant elsewhere in said amor(cid:173)
`phous silicon layer;
`patterning said amorphous silicon layer leaving undoped
`portions over said first and second gate electrodes, and
`thereby forming P-channel regions for said first and
`second thin film transistors, each said undoped portions
`contiguous with P-doped portions of said amorphous
`silicon layer, and said P-doped portions extending over
`areas of the other said first and second gate electrodes,
`and on said second insula):ing layer;
`photoresist masking and etching openings in and through
`said P-doped portions of said amorphous silicon layer
`to said second insulating layer;
`depositing a third insulating layer over said patterned
`amorphous silicon layer and said openings in said
`P-doped portions of said amorphous silicon layer;
`forming a patterned photoresist mask on said third insu(cid:173)
`lating layer having openings aligned over said openings
`in said P doped portions of said amorphous silicon
`layer, said photoresist mask openings being larger in
`size, and further said photoresist mask having openings
`for first metal contacts over said device areas;
`anisotropically and selectively etching said third insulat-
`ing layer in said photoresist mask opening to said
`openings in said P-doped portions of said amorphous
`silicon layer, and etching further to form openings in
`said second insulating layer to one of said first and
`second gate electrodes forming stacked contact open(cid:173)
`ings, and simultaneously forming metal contact open(cid:173)
`ings to said device areas elsewhere on the ·said sub(cid:173)
`strate;
`forming conducting plugs in said stacked contact and
`metal contact openings;
`depositing a first metal layer and patterning said first
`metal layer to form a interconnecting metal layer, and
`thereby completing said plug structure on said SRAM
`cell.
`2. The method of claim 1, wherein a concentration of said
`third polysilicon layer N+ dopant is between about 1.0 E 18
`to 1.0 E 20 atoms/cm3 and the thickness is between about
`300 to 1500 Angstroms.
`3. The method of claim 1, wherein a thickness of said gate
`oxide formed from said second insulating is a silicon oxide
`formed by low pressure chemical vapor deposition having a
`thickness of between about 50 to 500 Angstroms.
`4. The method of claim 1, wherein a thickness of said N
`doped amorphous silicon layer is between about 50 to 800
`55 Angstroms.
`5. The method of claim 4, wherein said N doped amor(cid:173)
`phous silicon layer is doped with phosphorus (P) having a
`concentration between about 1.0 E 16 to 1.0 E 18 atoms/
`cm3
`·•
`6. The method of claim 1, wherein said ion implanted
`P-type conductive dopant in said amorphous silicon layer
`forms source/drain areas of said thin film transistors.
`7. The method of claim 6, wherein said P-type dopant is
`boron having a concentratioil between about 1.0 E 18 to 1.0
`E 20 atoms/cm3
`.
`8. The method of claim 1, wherein said third insulating
`layer is a silicon oxide and is formed by low pressure
`
`60
`
`Petitioner Nanya Technology Corp. - Ex. 1006, p. 8
`
`

`
`5,547,892
`
`9
`chemical vapor deposition (LPCVD) and is between about
`8000 to 13000 Ang