United States Patent [t9J
`Langley
`
`[11] Patent Number:
`[45] Date of Patent:
`
`4,939,105
`Jul. 3, 1990
`
`[54] PLANARIZING CONTACT ETCH
`
`[75]
`
`Inventor: Rod C. Langley, Boise, Id.
`
`[73] Assignee: Micron Technology, Inc., Boise, Id.
`
`[21] Appl. No.: 388,841
`
`[22] Filed:
`
`Aug. 3, 1989
`
`Int. Cl.5 ..................... ROlL 21/00; ROlL 21/02;
`[51]
`HOlL 21/283; ROlL 21/302
`[52] u.s. Cl •.................................... 437/228; 437/225;
`437/235; 437/981; 148/DIG. 51; 148/DIG.
`131; 156/643; 156/644; 156/646
`[58] Field of Search ............... 437/189, 195, 225, 228,
`437/235, 981; 148/DIG. 51, DIG. 131;
`204/192.32, 192.24, 192.37; 156/643, 646, 653,
`657, 659.1
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`4,520,041 5/1985 Aoyama et al ...................... 437/195
`
`FOREIGN PATENT DOCUMENTS
`0160126 8/1985 Japan ........................ 148/DIG. 161
`
`OTHER PUBLICATIONS
`Sze, S., VLSI Technology, pp. 317-321, McGraw-Hill,
`1983.
`Primary Examiner-Brian E. Hearn
`Assistant Examiner-B. Everhart
`Attorney, Agent, or Firm-Jon Paul Busack; Stan
`Protigal; Angus C. Fox
`
`ABSTRACT
`[57]
`The present invention is a contact etch method which
`simultaneously smoothes a reflowed oxide profile so
`that separate phanarization photoresist coat and etch
`steps are unnecessary. This method is characterized in
`that it is fast, uses only one photoresist mask layer,
`etches contacts to poly and to substrate simultaneously,
`is done entirely with plasma etch technology in a single
`reactor, and builds up less polymer in the plasma reac(cid:173)
`tor. The novel method eliminates a coat and an etch
`step, improving yield and reducing fabrication time.
`Lower polymer buildup means higher yields due to a
`cleaner process, and less downtime for reactor chamber
`cleaning.
`
`15 Claims, 2 Drawing Sheets
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`15'
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`(( 14
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`14
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`Petitioner Nanya Technology Corp. - Ex. 1005, p. 1
`
`

`
`U.S. Patent
`
`Jul. 3, 1990
`
`Sheet 1 of2
`
`4,939,105'
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`~POLY
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`I
`I
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`:RESIST
`I
`:OXIDE
`I
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`I SUBSTRATE
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`l _________________ J
`Fl&.l
`!PRIOR ART)
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`~POLY
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`..J
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`:OXIDE
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`I
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`:SUBSTRATE
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`F1&.2
`!PRIOR ART)
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`: SUBSTRATE ·
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`F1&.3
`(PRIOR ART)
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`Petitioner Nanya Technology Corp. - Ex. 1005, p. 2
`
`

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`F1&.7
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`10
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`Petitioner Nanya Technology Corp. - Ex. 1005, p. 3
`
`

`
`1
`
`PLANARIZING CONTAcr ETCH
`
`4,939,105
`
`2
`duce near-vertical slope near the bottom of the contact.
`The resist is then stripped and the wafer stands ready as
`shown in FIG. 3 for metal deposition. Although both of
`these etches can be done dry, the isotropic etch step is
`5 often done wet.
`It is desirable to perform planarization and contact
`etch using one resist mask layer instead of two. It is
`further desirable to perform this entirely by dry etching.
`
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`The present invention relates to etching methods
`used in the fabrication of integrated electronic circuits
`in a semiconductor substrate such as silicon, particu(cid:173)
`larly a combined contact etch and planarization in a
`single mask process.
`SUMMARY OF THE INVENTION
`The present invention is a contact etch method which
`An electronic circuit is chemically and physically
`simultaneously smoothes a reflowed oxide profile so
`integrated into a substrate such as a silicon wafer by
`that separate planarization photoresist coat and etch
`patterning regions 'in the substrate, and by patterning
`steps are unnecessary. This method is characterized in
`layers on the substrate. These regions and layers can be
`conductive, for conductor and resistor fabrication, or 15 that it is fast, uses only one photoresist mask layer,
`insulative, for insulator and capacitor fabrication. They
`~tches con~cts to. poly and to substrate simul~aneo_usly,
`can also by of differing conductivity types, which is
`essential for transistor and diode fabrication. Degrees of
`IS done entrrely .with plasma etch tec?nology m a smgle
`reactor: and b~tlds up less P?lymer m the pl~~a reac-
`resistance, capacitance, or conductivity are controlla-
`ble, as are the physical dimensions and locations of the 20 tor. Usmg a smgle photoresist mask layer ehmmates a
`patterned regions and layers, making circuit integration
`coat and an etch step, improving yield and reducing
`possible. Fabrication can be quite complex and time
`.fabricating time. Lower polymer buildup means higher
`consuming, and therefore expensive. It is thus a continu-
`yields due to a cleaner process, and less downtime for
`ing quest of those in the semiconductor fabrication
`reactor chamber cleaning.
`business to reduce fabrication times and costs of such 25
`In the inventive method, a reflowed layer of oxide
`devices in order to increase profits. Any simplified pro-
`over polycrystalline silicon ("poly") structures
`is
`cessing step or combination of processes at a single step
`masked with patterened resist. A frrst etch step is per-
`becomes a _co~petitive advantage.
`formed, which slopes the resist and begins etching ex-
`2. r;>esc~ptton of the Relate~ AX:
`.
`.
`.
`posed oxide. As the resist erodes, more oxide is exposed
`. (\ SI~uatto~ w~er~ a P,rocess s~p!ificatiOn IS desrrable 30 to the etching atmosphere and therefore the top of the
`IS m dtelec~nc ( oXIde ) plananzatlon an.d contact etch
`contact is widened, or "sloped". The amount of resist
`steps, parttc~arl~ f~r contacts 1.2 microns ~r less
`erosion is critical, as it serves to ultimately define the
`across. Plananzatton ts necessary because the dtstance
`.
`.
`aks ·
`th
`"d
`.
`destred contact profile or slope. In a second step, restst
`th all
`bet
`1
`d
`e oXI e 1s so arge
`.
`.
`ween
`e v eys an pe m
`that a subsequent layer such as photoresist ("resist") or 35 an~ oxtd~ are e~ched at app~oXImately a 1:1 ~tch rate
`metal is difficult to pattern due to differences in focus-
`rat1o ?ntil poly 1s, o_r nearly 1s, exposed. A third, non-
`selective, et~h step IS then ~e~ormed. A.lthough some
`ing and exposure requirements between the peaks and
`valleys, due to different elevations and due to the ten-
`of the poly IS etched where 1t IS exposed m the shallow
`dency for the subsequenct layer to 'thin out at the peaks
`contacts, full poly thickness is not needed in this struc-
`and pool in the valleys. "Contact etch" refers to the 40 ture. Furthermore, this step has the advantages of being
`faster and producing less polymer than with a more
`etching of holes, or contacts, through an intermediate
`layer such as oxide, so that a conductive layer such as
`selective etch. When a predermined maximum allow-
`metal on top of the insulative oxide can contact a layer
`able amount of poly has been lost, a fourth and fmal etch
`underneath the oxide.
`step is performed, reactive to oxide more than poly, to
`"Reflow", where a layer of oxide is heated suffi- 45 clear remaining oxide from deep contacts without re-
`moving much more poly.
`ciently to cause it to smooth out, provides a degree of
`planarization. This technique along is not always satis(cid:173)
`factory because the high temperature required for ade(cid:173)
`quate reflow may also affect the semiconductor struc(cid:173)
`tures under fabrication.
`Plasma or "dry" etching is an ideal technology for
`performing both planarization and contact etch. Plasma
`offers easy control of the resist-to-oxide etch rate ratio,
`ideally 1:1 for planarization. Plasma also offers aniso(cid:173)
`tropic etchability, appropriate for making contact walls 55
`vertical, which is desirable. A camber or slope in the
`upper contact wall may also be desirable, to allow easy
`flow of a subequent layer into the contact during depo(cid:173)
`sition. This slope can be done using plasma techniques
`or by well known chemical or "wet" etch methods.
`Conventionally, an oxide layer is first planarized and
`then contacts are etched in the oxide before a subse(cid:173)
`quent metal deposition. In planarization, resist is layered
`on oxide, as illustrated in FIG. 1, and then etched back
`at a 1:1 etch rate ratio (resist to oxide), as shown in FIG. 65
`2. Contact etch is done by patterning a mask of resist on
`the oxide, isotropically etching to slope the contacts,
`and then finishing with a more anisotropic etch to pro-
`
`10
`
`BRIEF DESCRIPTION OF THE ORA WINGS
`The inventive method will be more apparent from the
`50 description of the preferred embodiment set forth be(cid:173)
`low, with reference to the accompanying sectional
`drawings, in which:
`FIG. 1 shows oxide coated with resist just prior to a
`conventional planarization etch;
`FIG. 2 shows the oxide layer after a conventional
`planarization etch;
`FIG. 3 shows the result after a conventional contact
`etch;
`FIG. 4 depicts a patterned contact mask on top of a
`reflowed oxide layer;
`FIG. 5 shows the result of the first step of the inven(cid:173)
`tive method, which widens the contacts;
`FIG. 6 shows the result of the second step of the
`inventive method, an etch down to poly; and
`FIG. 7 shows the result of the third and fourth steps
`of the inventive method, an etch clearing all oxide from
`the contacts.
`
`60
`
`Petitioner Nanya Technology Corp. - Ex. 1005, p. 4
`
`

`
`4,939,105
`
`3
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENT
`As illustrated in FIG. 4, a preferred embodiment of
`the inventive method is well suited to etch planarized 5
`contacts in 15 kA ofborophosphosilicate oxide (BPSG)
`13, over a 1.5 kA barrier layer of tetraethylorthosilicate
`derived oxide (TEOS) 12, over 5.5 kA yoly structures
`11, the BPSG layer 13 having a 10.5 kA mask layer of
`resist 14 which is patterned for contacts 15 and 15'. 10
`After the inventive process is performed, contacts 15
`open to poly 11, and contacts 15' open to silicon sub(cid:173)
`strate 10.
`In this structure, BPSG layer 13 has preferably previ(cid:173)
`ously undergone reflow to achieve partial improvement 15
`in planarization. Reflow is well understood in the art
`and therefore not detailed herein. TEOS barrier layer
`12 acts to block boron and phosphorus from diffusing
`into poly 11 from BPSG 13 during said reflow. Resist 14
`openings for contacts 15 and 15' of about 0.8 microns 20
`across will result in fmal measurements of about 1.2-1.4
`microns across the bottom of contacts 15 and 15'.
`Contacts 15 and 15' will have a preferred slope of about
`60• from horizontal near their tops, although slopes of
`about 45•-75• can be achieved by variations in step one 25
`of the inventive process.
`The preferred method includes four timed etch steps
`in a single Lam 790 parallel plate plasma etch reactor,
`having an inert cathode such as anodized aluminum,
`and an anode on which substrate 10 is mounted. All four 30
`steps utilize a 0.36-0.5 em gap between reactor elec(cid:173)
`trodes, a 2.0-2.8 torr chamber pressure, and about
`1.54-3.39 W /cm2 plasma power density, although ap(cid:173)
`proximately 0.46 em, 2.3 torr, and 2.78 W /cm2 are pre(cid:173)
`ferred.
`In the first step, a chamber atmosphere of Oz, He,
`CHF3, and CF4 is provided, widening, or forming
`slopes in, contacts 15 and 15' by eroding resist 14. This
`etch step is timed at about 45 seconds for a preferred
`slope, after which the structure appears as shown in 40
`FIG. 5. The atmosphere includes 5-20 seem Oz, 0-200
`seem He, 0-30 seem CHF3, and 75-200 seem CF4, al(cid:173)
`though 10 seem, 140 seem, 15 seem, and 125 seem,
`respectively, are preferred. In this disclosure, "seem"
`denotes a flow of standard cubic centimeters per min- 45
`ute, injected into the plasma through holes in the cath(cid:173)
`ode.
`After the proper contact slope is obtained, a second
`etch is performed, the chamber atmosphere including
`about 140 seem He, 15 seem CHF3, and 125 seem CF4, 50
`in order to etch oxides 13 and 12 and remaining resist 14
`at a 1:1 etch rate ratio. This etch is carefully timed at
`about 30 seconds, although up to 45 seconds has suc(cid:173)
`cessfully been done, stopping at or just before poly 11 is
`exposed. Preferably, resist 14 clears at about the same 55
`time that poly 11 is exposed, at which point the struc(cid:173)
`ture appears as shown in FIG. 6. Notice that contacts 15
`are essentially complete at this point. Although the
`preferred gas flows are given, they can range within
`approximately 0-200 seem for He, 0-30 seem for CHF3, 60
`and 75-200 seem for CF4.
`The third etch step in the inventive process includes
`at atmosphere of about 120 seem He, 20 seem CHF3,
`and 50 seem CF4, to quickly and cleanly etch most of
`the remaining oxide out of contacts 15'. This etch is 65
`timed at about 45-60 seconds, preferably 60, and is
`nonselective to reduce etch time and polymer forma(cid:173)
`tion, thus producing a faster, cleaner process. It is true
`
`4
`that this third step will etch more of poly 11 than a
`similar, more selective etch, but the structure etched by
`the preferred method does not require full poly 11
`thickness, and the etch step is stopped before too much
`poly is etched away. In this step, the gas flows can
`range within about 0-200 seem for He, 10-30 seem for
`CHF3, and 25-75 seem for CF4. as long as more CF4 is
`provided than CHF 3·
`The fourth and final step in the preferred method is
`selective, simply etching remaining oxide out of
`contacts 15' down to substrate, without etching much
`poly 11 out of contacts 15. This etch step is similar to
`the third etch step, except the amount of CHF3 relative
`of CF4 is increased to provide selectivity. The chamber
`atmosphere includes about 0-200 seem He, 30-60 seem
`CHF3, and 25-75 seem CF4. there being more CF4
`provided than CHF3. About 120 seem He, 45 seem
`CHF3, and 50 seem CF4 are preferred. This etch is
`timed at about 90-150 seconds, prefereably 90 for the
`given structure.
`FIG. 7 illustrates the final result of the inventive etch.
`Notice that contacts 15 and 15' are well sloped at their
`tops, and deeper contacts 15' have vertical or near-ver-
`tical walls.
`Clearly, because the inventive method reduces oxide
`and poly thicknesses, original layer thicknesses of a
`given structure must be predetermined based on antici(cid:173)
`pated removal to obtain desired final thicknesses. Al(cid:173)
`though timed etches are preferred, it is recognized
`among those skilled in plasma etch that exact times will
`vary for given plasma etch reactors, semiconductor
`structures, and ftlm compositions (for example, BSG or
`PSG vs. BPSG, or poly doping variations). It is known
`that endpoints can often be used as an alternative to
`35 timed etches. This etch may also be interrupted at some
`intermediate layer between oxide and substrate, instead
`of stopping at substrate. The fact that poly may or may
`not rest on gate oxide is trivial to this process. These
`variations and others are intended to be circumscribed
`by these claims.
`I claim:
`1. A planarizing contact etch method, for a semicon(cid:173)
`ductor structure including a first layer of oxide over a
`pattered second layer of poly over a substrate, compris(cid:173)
`ing the steps of:
`(a) masking the semiconductor structure with resist
`patterned for first and second groups of contacts, a
`contact of said first group located over poly, and a
`contact of said second group located over sub(cid:173)
`strate;
`(b) providing a parallel plate plasma etch reactor,
`having a first electrode whereon the substrate is
`mounted, and having an inert second eletrode;
`(c) performing a first plasma etch on the semicondic(cid:173)
`tor structure while it is in a first atmosphere includ(cid:173)
`ing approximately 5 to 20 seem Oz, 0 to 200 seem
`He, 0 to 30 seem CHF3, and 75 to 200 seem CF4,
`until contacts of said first and second groups are
`sufficiently sloped;
`(d) performing a second plasma etch on the semicon(cid:173)
`ductor structure while it is in a second atmosphere
`including approximately 0 to 200 seem He, 0 to 30
`seem CHF3, and 75 to 200 seem CF4, until a
`contact of said first group is etched to, or nearly to,
`poly;
`(e) performing a third plasma etch on the semicon(cid:173)
`ductor structure while it is in a third atmosphere
`including approximately 0 to 200 seem He, 10 to 30
`
`Petitioner Nanya Technology Corp. - Ex. 1005, p. 5
`
`

`
`4,939,105
`
`5
`seem CHF3, and 25 to 75 seem CF4, there being
`more CF4 provided than CHF3, to quickly etch
`oxide out of a contact of said second group, until a
`predetermined limit of poly has been etched out of
`a contact of said first group; and
`(f) performing a fourth plasma etch on the semicon(cid:173)
`ductor structure while it is in a fourth atmosphere
`including approximately 0 to 200 seem He, 30 to 60
`seem CHF3, and 25 to 75 seem CF4, there being
`more CF4 provided than CHF3, until a contact of 10
`said second group is etched to substrate.
`2. The method of claim 1, wherein a gap within ap(cid:173)
`proximately 0.36 to 0.5 em exists between said first and
`second electrodes during at least one of said plasma
`etches.
`3. The method of claim 1, wherein a gap of approxi(cid:173)
`mately 0.46 em exists between said frrst and second
`electrodes during at least one of said plasma etches.
`4. The method of claim 1, wherein at least one of said
`atmospheres has a pressure within approximately 2.0 to 20
`2.8 torr.
`5. The method of claim 1, wherein at least one of said
`atmospheres has a pressure of approximately 2.3 torr.
`6. The method of claim 1, wherein at least one of said
`plasma etches utilizes a plasma power density within 25
`approximately 1.54 to 3.39 W /cm2.
`7. The method of claim 1, wherein at least one of said
`plasma etches utilizes a plasma power density of ap(cid:173)
`proximately 2.78 W /cm2.
`8. The method of claim 1, wherein said frrst atmo- 30
`sphere includes approximately lO seem 02, 140 seem
`He, 15 seem CHF3, and 125 seem CF4.
`9. The method of claim 1, wherein said second atmo(cid:173)
`sphere includes approximately 140 seem He, 15 seem
`CHF3, and 125 seem CF4.
`10. The method of claim 1, wherein said third atmo(cid:173)
`sphere includes approximately 120 seem He, 20 seem
`CHF3, and 50 seem CF4.
`11. The method of claim 1, wherein said fourth atmo(cid:173)
`sphere includes approximately 120 seem He, 45 seem 40
`CHF3, and 50 seem CF4.
`12. A planarizing contact etch method, for a semicon(cid:173)
`ductor structure including a first layer of oxide over a
`
`35
`
`6
`patterned second layer of poly over a silicon substrate,
`comprising the steps of:
`(a) masking the semiconductor structure with resist
`patterned for first and second groups of contacts, a
`contact of said first group located over poly, and a
`contact of said second group located over sub(cid:173)
`strate;
`(b) providing a parallel plate plasma etch reactor,
`having a first electrode whereon the substrate is
`mounted, and having an inert second electrode;
`(c) peroforming a first plasma etch on the semicon(cid:173)
`ductor structure while it is in a frrst atmosphere
`including approximately lO seem 02, 140 seem He,
`15 seem CHF3, and 125 seem CF4, to etch said
`resist and the frrst layer until contacts of said first
`and second groups are sufficiently sloped;
`(d) performing a second plasma etch on the semicon(cid:173)
`ductor structure while it is in a second atmosphere
`including approximately 140 seem He, 15 seem
`CHF3, and 125 CF4, until a contact of said frrst
`group etches to, or nearly to, poly;
`(e) performing a third plasma etch on the semicon(cid:173)
`ductor structure while it is in a third atmosphere
`including approximately 120 seem He, 20 seem
`CHF3, and 50 seem CF4, to quickly etch oxide out
`of a contact of said second group, until a predeter(cid:173)
`mined limit of poly has been etched out of a contact
`of said frrst group; and
`(f) performing a fourth plasma etch on the semicon(cid:173)
`ductor structure while it is in a fourth atmosphere
`including approximately 120 seem He, 45 seem
`CHF3, and 50 CF4, until a contact of said second
`group is etched to substrate.
`13. The method of claim 12, wherein said resist has a
`thickness such that it clears at approximately the same
`time that said second plasma etch is complete.
`14. The method of claim 12, wherein the oxide layer
`includes at least one of the group of oxide, BPSG, PSG,
`BSG, and TEOS.
`15. The method of claim 12, wherein the oxide layer
`is previously reflowed.
`* * * * *
`
`5
`
`15
`
`45
`
`50
`
`55
`
`60
`
`65
`
`Petitioner Nanya Technology Corp. - Ex. 1005, p. 6
`
`

`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`CERTIFICATE OF CORRECTION
`
`PATENT NO.
`DATED
`INVENTOR(S) :
`
`4,939,105
`July 3, 1990
`Rod C. Langley
`
`It is certified that error appears in the above-indentified patent and that said Letters Patent is hereby
`corrected as shown below:
`
`'
`
`Column 1, line 15, delete "by" and insert -- be --;
`
`Column 4, line 44, delete "pattered" and insert
`patterned --;
`
`Column 4, line 53, delete "eletrode" and insert
`electrode --;
`
`Column 6, line 11, delete "peroforming" and insert
`performing
`
`Signed and Sealed this
`
`Sixteenth Day of November, 1993
`
`Attest:
`
`Attesting Officer
`
`Commissioner of Patents and Trademarks
`
`BRUCE LEHMAN
`
`Petitioner Nanya Technology Corp. - Ex. 1005, p. 7