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`U.S. UTILITY Patent Application
`PATENT DATE
`O,.I,P.,E,
`.-
`,M
`APR 16
`i.
`
`NA
`
`BEST COPY
`
`PATENT NUMBER
`8372838
`
`632638 ill
`
`6372638
`
`il-
`a c.:..ndu-t.ive= pll.l t bet.weEnt', conlducti ve
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`CLASS
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`ISSUING CLASSIFICATION
`CROSS REFERENCE(S)
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`STERMINAL
`DISCLAIMER
`
`DRAWINGS
`
`CLAIM
`
`LOWED
`
`Sheets Drwg.
`
`Figs. Drw*
`
`Print Fig.
`
`Total Claimr'
`
`Print Claim for O.G.
`
`Continued on Issue Silip Inside File Jacket
`
`,
`
`(dat )/
`(date)
`
`I The term of this patent
`subsequent to
`has been disclaimed.
`O The term of this patent shall
`not extend beyond the expiration date
`of U.S Patent. No.
`
`OTICE OF ALLOWANCE MAILED "
`
`(Asli
`
`ml
`
`b- O
`(Date)
`
`!
`Cb es Bowers
`
`,_,
`
`A
`
`chnology Center 2800
`imary Examiner)
`
`(Date)
`
`( O -
`
`O(
`
`I
`ISSUE FEE
`
`O The terminal
`months of
`this patent have been disclaimed.
`
`pal Instruments Examiner)
`
`(Date)
`
`ISSUE BATCH NUMBER
`
`WARNING:
`The i;lormation disclosed herein may be restricted. Unauthorized disclosure may be prohibited by the United Stales Code Title 36, Sections 122, 181 and 388.
`Possession outside the U.S. Patent & Trademark Office is restricted to authorized employees and contractors only.
`
`Form PTO-496A
`(Aev. 8!98)
`
`FILED WITH: L DISK (CRF)
`Issue Fee
`
`r CD-ROM
`1 FICHE
`(Attached in pocket on right Inlde fap)
`
`(FACE)
`
`r,'A
`
`Petitioner Nanya Technology Corp. - Ex. 1002, p. 1
`
`

`
`6,372,638
`
`Method for forming a conductive plug between conductive layers of an
`integrated circuit
`
`Transaction History
`
`
`Transaction Description
`Date
`06-22-2000 Workflow - Drawings Finished
`06-22-2000 Workflow - Drawings Matched with File at Contractor
`06-22-2000 Preliminary Amendment
`06-22-2000 Information Disclosure Statement (IDS) Filed
`06-22-2000 Information Disclosure Statement (IDS) Filed
`06-22-2000 Initial Exam Team nn
`07-14-2000 IFW Scan & PACR Auto Security Review
`08-14-2000 Correspondence Address Change
`08-21-2000 Application Dispatched from OIPE
`10-26-2000 Case Docketed to Examiner in GAU
`02-02-2001 Miscellaneous Incoming Letter
`02-15-2001 Case Docketed to Examiner in GAU
`04-20-2001 Non-Final Rejection
`04-23-2001 Mail Non-Final Rejection
`07-18-2001 Response after Non-Final Action
`07-25-2001 Date Forwarded to Examiner
`09-10-2001 Mail Notice of Allowance
`09-10-2001 Notice of Allowance Data Verification Completed
`09-12-2001 Receipt into Pubs
`09-12-2001 Receipt into Pubs
`09-13-2001 Workflow - File Sent to Contractor
`11-02-2001 Issue Fee Payment Verified
`01-16-2002 Issue Fee Payment Received
`03-19-2002 Application Is Considered Ready for Issue
`03-21-2002 Receipt into Pubs
`03-28-2002 Issue Notification Mailed
`04-16-2002 Recordation of Patent Grant Mailed
`04-16-2002 Patent Issue Date Used in PTA Calculation
`09-05-2006 Correspondence Address Change
`
`
`Petitioner Nanya Technology Corp. - Ex. 1002, p. 2
`
`

`
`APPLICATION
`
`PATENT
`09599378
`
`PTO
`
`M1U.8.
`
`Imo.
`0 9918iItIiiIJ~"~I"U~I
`
`3
`
`CONTENTS
`Date Recelved
`(Incl. C. of M.)
`or
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`
`43.
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`__
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`81. _
`~82.
`(LEFT' OUTSIDE)
`
`Petitioner Nanya Technology Corp. - Ex. 1002, p. 3
`
`

`
`ISSUE SLIP STAPLE AREA (for additional cross references)
`
`POSITION
`
`INITIALS
`
`ID NO.
`
`DATE
`
`FEE DETERMINATION
`O.I.P.E. CLASSIFIER
`FORMALITY REVIEW
`RESPONSE FORMALITY REVIEW
`
`^
`
`' ,
`
`INDEX OF CLAIMS
`Rejected
`.................................
`Non-elected
`N ..............................
`I ................................. Interference
`................................. Allowed
`(Through numeral)... Canceled
`A .............................. Appeal
`................................ Restricted
`.............................. Objected
`0
`
`Claim
`
`Date
`
`Claim
`
`Date
`
`-
`
`j
`
`+, .•
`
`101
`1
`
`1 1
`
`04
`105
`106
`107I
`108
`09
`110
`111
`112
`113
`11
`115
`116
`117
`118
`119
`
`120
`121""
`22
`123
`124
`125
`26
`127
`128
`29
`130
`131
`3
`13
`13
`13
`
`3 3 3
`
`8
`
`3 4
`
`0
`14
`14
`14
`143
`45
`
`4
`14
`14
`15
`
`51
`
`53
`
`59
`60
`61
`62
`63
`64
`65
`66
`67
`68
`69
`70
`71
`72
`73
`74
`75
`76
`77
`78
`79
`80
`81
`82
`83
`84
`85
`86
`87
`88
`89
`90
`91
`92
`93
`94
`95
`96
`97
`98
`
`If more than 150 claims or 10 actions
`staple additional sheet here
`
`(LEFT INSIDE)
`
`Petitioner Nanya Technology Corp. - Ex. 1002, p. 4
`
`

`
`.
`
`(
`
`i i
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`f I
`
`
`
`.- _.. --
`
`-
`
`-
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`...
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`__._ _ _
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`F't
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`1.5 W operation of superlumiescent diode with highly
`strained GalnAslGaAs quantum well emitting at 1.2 IspD mulm
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`Koyama, F.; Schlenker, D.; Miyamoto, T.; Chen, Z.; Yamatoya, T.;
`Kondo, T.; Iga, K.
`Semiconductor Laser Conference, 2000. Conference Digest.
`2000 IEEE 17th International , 2000, Page(s): 71 -72
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`using a vertical silicon probe
`Nishiguchi, K.; Oda, S.
`Device Research Conference, 2000. Conference Digest. 58th
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`Tunable 1.3-spl mulm fiber ring laser employina a tapered
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`Williamson, R.C.; Belts, G.E.; Donnelly, J.P.; Groves, S.H.;
`Walpole, J.N.; O'Donnell, F.J.; Bailey, R.J.
`Lasers and Electro-Optics Society Annual Meeting, 1998.
`LEOS '98. IEEE
`Volume: 1 , 1998 , Page(s): 153 -154 vol.1
`Towards microcavity vertical cavity lasers: aperture and cavity
`design for high efficiency and low threshold
`Hegblom, E.R.; Thibeault, B.J.; Coldren, L.A.
`Vertical-Cavity Lasers, Technologies for a Global Information
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`Materials, Processing, and Devices, 1997 Digest of the
`IEEE/LEOS Summer Topical Meetin, 1997 , Page(s): 9 -10
`Assessment of Grashoff cooling potential in micro heat pipes:
`an experimental study
`Oshima, K.; Kaudinya, J. V.
`Semiconductor Thermal Measurement and Management
`Symposium, 1991. SEMI-THERM VII. Proceedings., Seventh
`Annual IEEE, 1991, Page(s): 73
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`620 mW near-diffraction-limited, 1.8 mu m tapered laser
`Mehuys, D.G.; Major, J.S., Jr.; Piano, W.B.; Welch, D.F.
`Electronics Letters
`Volume: 30 14 , 7 July 1994 ,Page(s): 1131 -1133
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`Petitioner Nanya Technology Corp. - Ex. 1002, p. 7
`
`

`
`CLIPPEDIMAGE= JP409183603A
`PAT-NO: JP409183603A
`DOCUMENT-IDENTIFIER: JP 09183603 A
`TITLE: FORMATION OF TAPERED DIELECTRIC LAYER OF SEMICONDUCTOR
`DEVICE BY
`ETCHING
`
`PUBN-DATE: July 15, 1997
`
`INVENTOR-INFORMATION:
`NAME
`YUUJIYA, SUU
`YUU, KEI WAN
`KAMU, ESU ROU
`HARUHIRO, EICHI GOTOU
`
`ASSIGNEE-INFORMATION:
`NAME
`.APPLIED KOMATSU TECHNOL KK
`
`APPL-NO: JP08268551
`APPL-DATE: October 9, 1996
`
`COUNTRY
`N/A
`
`INT-CL (IPC): C01B017/45; C23F001/12 ; C23F004/00 ; H01L021/3065
`; H01L029/786
`
`ABSTRACT:
`PROBLEM TO BE SOLVED: To provide a high-performance semiconductor
`device by
`forming inclined side walls within openings by using an etching
`gas system
`consisting of SF<SB>6</SB> and Cl<SB>2</SB> at the time of
`forming the openings
`by etching the dielectric layer of a semiconductor device.
`
`SOLUTION: The layer of a dielectric material (e.g.; silicon
`oxide) is deposited
`atop a substrate consisting of an insulating material (e.g.;
`glass). Next, a
`photoresist layer is deposited atop this dielectric material
`layer and is
`patterned. The dielectric material layer is then at least partly
`removed by
`the etching gas system consisting of the SF<SB>6</SB> and
`C1<SB>2</SB> to form
`at least one opening extending up to the front surface of the
`substrate. The
`openings are internally provided with the inclined side walls
`
`04/18/2001, EAST Version: 1.02.0008
`
`Petitioner Nanya Technology Corp. - Ex. 1002, p. 8
`
`

`
`between the front
`surface of the dielectric material layer and the front surface of
`the
`substrate. The inclined side walls formed in such a manner are
`preferably so
`formed as to have about 20 to 85&deg; taper angle measured from
`the front
`surface of the substrate. A conductive material (e.g.;
`indium-tin oxide) is
`then deposited in these openings, by which the seiriconductor
`device is obtd.
`
`COPYRIGHT: (C)1997,JPO
`
`04/18/2001, EAST Version: 1.02.0008
`
`Petitioner Nanya Technology Corp. - Ex. 1002, p. 9
`
`

`
`
`
`
`
`I 1111
`
`
`
`S11111111111 11111111 11111 II I HII 11 1111 11 11
`
`US006372638B1
`US 6,372,638 BI
`Apr. 16, 2002
`
`(12) United States Patent
`Rodriguez et al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`(54) METHOD FOR FORMING A CONDUCTIVE
`PLUG BETWEEN CONDUCTIVE LAYERS OF
`AN INTEGRATEID CIRCUIT
`
`2/1993 Clonin et al
`5,189,5Y, A
`5,854,140 A * 12/1998 Jas- ....
`.....
`6,143,648 A * 11/200I Rodnguez et al.
`
`....
`257/752
`... 438/740
`438/640
`....
`
`(75)
`
`Inventors. Robert Arthur Rodriguez, Heather
`Marie Klesat, both of Austin, TX (US)
`
`(73) Assignce Motorola, Inc., Schaumburg, IL (US)
`
`Notice
`
`Subject to any disclaimer, the term of Tbis
`patent is extended or adjusted under 35
`U.S C 154(b) by 0 days
`
`Appi No. 09/599,378
`
`Filed
`
`Jun. 22, 2010
`
`Related U.S. Application Data
`
`(63) Continualion of application No. 08/802,299, fled on Feb
`18, 1997, now Pat No 6,143,648
`
`Int. Cl
`(51)
`(52) U.S. CL
`
`H01L 21/4763
`...............
`438/640; 438/633; 438/637;
`..
`......
`438/673; 438/713; 257/752; 257/774
`(58) Field of Search
`...
`....
`.. 438/637, 638,
`438/640, 672, 675, 633, 620, 622, 713,
`673; 257/752, 750, 774
`
`(56)
`
`References Cited
`
`U S PATENT DOCUMENTS
`
`4,908,333 A
`4,970,573 A
`4997.518 A
`5,049,975 A
`5,082,801 A
`
`3/1990 Shimokawa et al.....
`438/624
`... 357/71
`11/1990 Roberts et al
`...
`3/1991 Madokoro
`.................. 156/643
`9/1991 Ajika et al
`.....
`... 357/71
`1/1992 Nagata
`... ........
`438/640
`
`OTIIER PUBLICATIONS
`
`Kaanta et al, "Dual Damascene. A ULSI Wiring Technol
`ogy," VMIC Conference, 9 pgs. (1991)
`Kaufman et al., "Chemical-Mechanical Polishing for Fab-
`ricating Patterned W Metal Features as Chip Interconnects,"
`J. Electrochem Soc vol 138, No
`11, pp. 3460-3464
`(1991)
`
`* cited by examiner
`
`Primary lxammer-('harlcs Bowers
`Assistant Lxamner-Hsiln-Mng Lce
`(74) Atorney, Agent, or Firm-Robert A Rodrguez, Keath
`E Witek
`
`(57)
`
`ARSTRACT
`
`A method for forming void free tungsten plug contacts
`(56a-56c) begins by etching a contact opening (55a-55c)
`chemistry. The etch chemistry is
`using a C2 F, and C11II
`then changed to an O, and CIIsF chemistry an order to mnsitu
`remove the contact photoresist while tapering an upper
`portion of the contact opening. A tungsten deposition pro-
`cess is then periormed wherchby the tapered portion of the
`contact reduces the offects of noncinformal and step
`coverage-inconsistent tungstcn deposition wherein voids in
`the contact are either substantially reduced or totally avoided
`within the contact slruclure. The reduction of or total elimi-
`nation of voids (22) within the tungsten contact will increase
`yield, increase reliability, and reduce electromigraton fail-
`ures within integrated circuit devices
`
`11 Claims, 5 Drawing Sheets
`
`Petitioner Nanya Technology Corp. - Ex. 1002, p. 10
`
`

`
`U.S. Patent
`
`Apr. lfi, 2002
`
`Shcct 1 of 5
`
`US 6,372,638 B1
`
`18
`
`"A-
`
`- I0
`
`j 10
`
`FIG. 1
`
`-PRIOR ART-
`
`FIG.2
`-PRIOR ART-
`
`FIG. 3
`-PRIOR ART-
`
`Petitioner Nanya Technology Corp. - Ex. 1002, p. 11
`
`

`
`U.S. Patent
`
`Apr. 16, 2002
`
`Sheet 2 of 5
`
`US 6,372,638 B1
`
`FIG. 4
`
`<55a
`
`<-55b
`
`<55c
`
`FIG. 5
`
`Petitioner Nanya Technology Corp. - Ex. 1002, p. 12
`
`

`
`U.S. Patent
`
`Apr. 16, 2002
`
`Sheet 3 of 5
`
`US 6,372,638 B1
`
`FIG. 6
`
`52
`
`,52
`
`FIG. 7
`
`Petitioner Nanya Technology Corp. - Ex. 1002, p. 13
`
`

`
`U.S. Patent
`
`Apr. 16, 2002
`
`Sheet 4 of 5
`
`US 6,372,638 B1
`
`55a
`
`54
`
`52
`
`55b
`
`Y
`
`55c
`
`54
`
`52
`
`30
`
`FIG. 8
`
`55a
`
`FIG. 9
`
`Petitioner Nanya Technology Corp. - Ex. 1002, p. 14
`
`

`
`U.S. Patent
`
`Apr. 16, 2002
`
`Sheet 5 of 5
`
`US 6,372,638 B1
`
`30
`
`48
`
`48
`
`52
`
`50
`
`34
`
`44
`
`42
`
`46
`
`44
`
`FIG. 10
`
`52
`
`50
`
`32
`
`52
`
`52
`
`50
`
`56b
`5
`
`56c
`5
`
`50
`
`34
`
`44
`
`42
`
`46
`
`44
`
`32
`
`FIG.11
`
`Petitioner Nanya Technology Corp. - Ex. 1002, p. 15
`
`

`
`US 6,372,638 B1
`
`METHOD FOR FORMING A CONDUCTIVE
`PLUG BETWEEN CONDUCTIVE IAYERS OF
`AN INTEGRATED CIRCUIT
`
`This is a continuation of U.S patent application Ser. No
`08/802299, filed on Feb. 18, 1997 now U.S. Pat. No.
`6,143,643, which is hereby incorporated by reference, and
`prnioity thereto [or common subject matter
`is hereby
`claimed
`
`FIELD OF THE INVENTION
`[The present invention relates generally to integrated cir-
`cuit manufacturing, and more particularly to, a method lfor
`formmg tungsten contact plugs in a void-free manner.
`
`-
`
`10
`
`15
`
`HACKGROUND OF THE INVENTION
`
`ence of the voids 22 in high aspect ratio contacts are
`disadvantageous and a sigmnificant problem for integrated
`circuit (IC) processing.
`FIG. 3 illustrates that a chemical mechanical polishing
`(CMP) operation is used to form the tungsten plug 20c
`illustrated in FIG 3 Note that the void 22 is still present
`within the contact structure after polishing and therefore is
`still problematic in the final integrated circuit (IC) device.
`Therefore, a need exists for a IC contact formation
`process which continues to utilize nonconformal tungsten
`deposition processes while resulting in reduced or totally
`elimmated void formation.
`
`BRIEF DESCRIPTION OF TEIE DRAWINGS
`
`FIGS 1 through 3 illustrate, in cross sectional diagrams,
`a method for forminmg a prior art contact structure containmg
`unwanted voids.
`FIGS 4 through 7 illustrate, in cross-sectional diagrams,
`a method for forming void free tungsten plug contacts in
`accordance with the present invention
`FIGS 8 through II illustrate, in cross-sectional diagrams,
`an alternative method for forming void free tungsten plug
`contacts m accordance with the present invention.
`
`DETAIIEI) I)ESCRIPI1ON OF THE DRAWINGS
`
`In the integrated circuit (IC) mduslry, contacts between
`polysthcon layers and/or metal layers are sometimes formed
`using tungsten plugs. As advances are made m lithographic
`processing and etch technology, the radial opemng of an 20
`integrated circuit contact continues to shrink while the
`vertical depth of integrated circuit contacts have been
`increasing This increase in contact aspect ratio (depth/
`radius) creates rehabihty and manufacuring problems when
`using tungsten deposition and chemical mechamcal polish- 25
`ing (C(MP) technology to form tungsten plugs
`The problems arise when tungsten (W) continues in the
`Generally, the present invention is a method for lirming
`industry to be used to plug large aspect ratio contacts is
`a void free tungsten plug contact. 'lhe process herem can
`illustrated in prior art FIGS. 1-3. As is known in the art, o
`utilize the same conventional tungsten deposition processes
`tungstlen deposition suffers from highly nonconformal depo
`which are highly nonconformal and have step coverage
`sition characteristics, also referred to as inconsistent step
`problems without resulting in the void formation illustrated
`coverage The adverse effects ol this non-confrmal nature
`In the FIGS 1 through 3. Generally, the nonconformal or
`of tungsten deposition is illustrated in FIGS 1-3
`step coverage problem of conventional tungsten (W) depo-
`sition is compensated for by altering the contact profile to a
`In FIG 1, a contact structure 10 is formed by initially 35
`tapered contact unlike the constant radius X contact illus-
`providmg a base layer 12. A lirst conductive layer 14 is
`trated in FIG. 1. By using unique etch chemistries to taper
`formed on top of the base layer 12 Layer 14 is lithographi-
`the sidewall profile of contacts to form a "golf tee" contact
`cally patterned and etched A dielectric layer 16 is formed
`overlying the patterned layer 14 1he dielectric layer 16 is
`prolile or a "wine glass" contact profile, conventional non
`conformal and step coverage hmited tungsten processing
`then patterned then etched to form a contact opening 18 40
`can be used to form tungsten plug contacts with high aspect
`which has a substantially uniform radius X at all elevations
`ratios that have improved yield, greater functional die per
`through the contact 18 of FIG
`I FIG. 1 illustrates the
`wafer, and improved clectronmgration resistance. In general,
`beginning of the tungsten deposillon process which forms an
`void-free or void-reduced contacts formed as taught herein
`initial tungsten layer 20a.
`result in integrated circuits (ICs) being formed with higher
`In FIG. 1, tungsten is deposited in a highly nonconformal 4s
`aspect ratio contacts at a higher yield. In addition, most
`manner In other words, top surfaces of the diectnrc layer
`alterations of contact profiles result in adversely affecting
`16 will accumulate tungsten material at a much faster rate
`design rule spacing of contact structures However, the
`than the bottom comers of the contact opening 18.
`contact profile processes taught herem can be utilihed with-
`Therefore, the shape of the initial stages of tungsten depo
`out adversely ellecting contact spacing design rules since a
`sition is accurately illustrated in FIG. I whereby top portions so
`chemical mechanical pohsh (CMP) process is used to
`of the dielectric layer 16 have accumulated a greater thick-
`remove the widened "golf tee" or "wine glass" contact
`ness of tungsten than lower portions of the contact opening
`profile alterations in a final step so that contact spacing is not
`18.
`adversely effected
`In FIG. 2, tungsten deposition continues to transform the
`The invention can be further understood with reference to
`thinner tungsten layer 20a in FIG
`to a thicker tungsten 55
`FIGS 4 through 11
`layer20b in FIG 2 The tungsten, which continues to deposit
`FIGS 4 through 7 illustrate a first method for forming a
`in FIG 2, is also nonconformal and deposits more along the
`void free tungsten (W) plug contact structure. FIG. 4 illus-
`top exposed surfaces of layer 20a and less along the side-
`trates a substrate 32 Substrate 32 is typically a silicon wafer
`walls and bottom portion of the contact 18. Due to this
`but can also be a gallium arsenide wafer, a germanium doped
`nonconformal deposition, many contacts formed using a 5o
`layer, epitaxial silicon, a silicon-on-insulator (SOI)
`tungsten deposition process will form keyholes or voids 22
`substrate, or any like integrated circuit substrate. A gate
`as illustrated in FIG. 2 These voids form from the noncon-
`oxide layer 34 is formed overlying the substrate 32 Gate
`formal deposition nature of tungsten "pinching off' the top
`opening in the contact hole The voids 22 resulting from this
`oxide layer 34 is typically a thermally grown oxide within
`the range of 35 A to 120 A In alternate embodiments, the
`nonconformal step coverage of tungsten create depressed c,5
`gate oxide 34 can be a composite dielectric comprising
`yields, nonfunctional IC die from electrical open cacuits,
`and electromigration failures over time. Therefore, the pres
`deposited and/or thermally grown dielectric materials
`In
`
`Petitioner Nanya Technology Corp. - Ex. 1002, p. 16
`
`

`
`US 6,372,638 B1
`
`addihton, the gate oxide 34 may be exposed to a nitrogen or
`fluorine ambient to incorporate one of either nitrogen or
`fluorine within the gate oxide 34 to improve overall gate
`oxide rehability
`A polysllcon or amorphous silicon layer 36
`is then
`deposited over the gate oxide 34 The layer 36 may be
`formed min a single deposition process or in an A-poly/B-poly
`process which is known m the art. The layer of polysilicon
`or amorphous silicon 36 can be optionally sihcided via
`exposure to an environment containing a refractory metal. In
`addition, the layer of polystlicon or amorphous silicon 36 is
`covered with a capping layer 38 illustrated in FIG 4. In a
`preferred form, the capping layer 38 is silicon nitride, but the
`capping layer can be any dielectric or conductive layer
`which performs either an etch stop function and/or ntll-
`reflective coating (ARC) function. The layer of polysilicon
`or amorphous silicon 36 as well as any slicide and/or
`capping layer 38 formed over the layer 36 are then photo-
`lilhographrcally patterned and etched as a stack to form gate
`electrode portions 36 on the integrated circuit (IC). In
`addition to forming gate electrodes, portions of layer 36 may
`be hthographically formed for contact regions, buried
`contacts, or like polysilicon structures
`After formallon of the gate electrode 36 in FIG. 4,
`sidewall spacers 40 are made in order to enable lightly doped
`drain (LDD) current electrode formation Thle exact current
`electrodes (source and dram) are not specifically illustrated
`in FIG. 4. A first tetraethylorthosthcate (TEOS) layer 42 is
`then formed overlyig the spacers 40 m FIG 4 Other oxides
`in the art may replace the
`and dielectrcs as are known
`specific dielectrics and/or oxides taught herein to create
`other embodiments. A second layer of polysihcon and/or
`amorphous silcon 44 is deposited and patterned in FIG 4
`Overlying the layer 44, another TEOS layer 46 is deposited.
`After deposlion of the TEOS layer 46, a thud polysilicon or
`amorphous slh cn layer is deposited and patterned to form
`polysthcon regions 47 as illustrated in FIG. 4. Overlying
`region 47 is another TEOS layer 48, followed by a boro-
`phosphosihcate glass (BPSG) layer 50 Layer 50 is followed
`by yet another TEOS layer 52 It should be noted herein that
`the dielectric layers and conductive layers taught herein can
`be replaced equivalent dielectric and conductive materials as
`is known in the art (e.g, silicided polysilicon may replace
`unsulicided amorphous silicon in some embodiments).
`Once the TEOS layer 52 is formed, a photoresist layer 54
`is formed on the wafer The photoresist 54 as then selectively
`exposed using cventional photoresist processing The
`photoresist is then developed to form openings 55a through
`55c within the photoresist layer 54 as illustrated in FIG 4
`After defining the opening in the photoresist layer 54, the
`layers 52, 50, 48, 46, and 42 are then etched in FIG 4 using
`a CcF and CIIF3 etch environment to extend the opemng
`deeper into the semiconductor device
`In the case of contact 55a, the CzF and CHF3 etch
`chemistry is selective to the nitride layer 38 so that the
`contact 55a will continue to etch/deepen until the capping
`layer 38 is exposed (at which time etching will significantly
`reduce in rate). In the case of the contact 556 of FIG 4, the
`CF,o and CHF 3 etch chemistry is selective to the semicon-
`ductor substrate 32 Furthermore, the CF 6 and CIITP used
`to etch the contact 55c is selective to the polysilicon and/or
`amorphous silicon 44. 'Therefore, the three contact openings
`55a through 55c are formed as illustrated in FIG 4 using a
`reactive ion etch (RIl) or like plasma etch environment In
`addition, it is important to note that there are other oxide etch
`chemistries and processes other than (CF6 and/or CHF 3
`which may be used herein to etch the contacts 55a through
`55c
`
`FIG 5 illustrales that the photoresisl 54 of FIG 4 is
`removed. 'lus removal can be performed in one of two
`manners. In a preferred form, the photoresist 54 is removed
`from the wafer by using an in situ CIIF and Oz etch
`5 environment in another form, a purely exsitu 02 chemistry
`may be used to remove the photoresist in a different pro
`cessing chamber other than the etch chamber than the
`chamber used to perform the elchmg illustrated In FIG 4
`After the photoresist 54 is removed from the wafer in FIG
`to 5, the wafer is exposed to a CH 3F and O0 environment to
`perform tapering of an upper portion of the contact openings
`55a through $5Sc. In a preferred form, the CHF etch
`chamber and etch plasma used to perform the contact taper
`process in the same or similar process used to perform the
`15 preferred m situ photoresist removal. In addition, the same
`(CH3F etch chamber and etch plasma used to perform the
`contact taper process can simultaneously be used to remove
`the silicon mtride used to form the capping layer 38 from the
`bottom of the contact opemng 55a as shown m FIG 5
`As illustrated m FIG. 5, the contact tapering operation
`results in an upper portion of the contacts 55a through 55c
`being enlarged to a radius Y wherein the radius Y of FIG 5
`is greater than the radius X formed via the etching of FIG
`4 The radius X of FIG 5 is identical to the radius X of FIG
`25 1, and is typically a mmimum lithographic dimension
`allowed by the specific lithographic equipment utilized in
`the manufacture of the contact structure. The exposure of the
`wafer to the CH 3F and 02 plasma etch environment results
`in a rounding of the upper corners of the contact openings
`30 55a through 55c to form a "golf tee" proille In Table 1
`below, the etch process discussed above with respect to FIG
`4 through FIG 5 is summanzed in a Table 1
`
`2'
`
`35
`
`TABLE 1
`
`Source Power
`(wats)
`40 Bias Power
`(Wata)
`P'ressure (mbri
`TN)
`time (see)
`S'.5s (sem)
`cml,
`(sccm)
`Ciat,
`(sCem)
`t e (sgcm)
`0, (sccm)
`
`Main contaci Reqit Strip
`Etch
`and Taper Etch
`
`Polymer
`Removal Step
`
`2800 . 20%
`
`tsco a 20% 20
`
`600
`
`20%
`
`1400 e 20%
`
`250
`
`20%
`
`300 z 20%
`
`1) ± 0%
`
`20 ± 20%
`
`25 ± 20%
`
`210 ±20%
`40 ± 20%
`IS ± 210%
`
`7520%
`
`60 ± 50%
`
`60 ± 20%
`
`40 ± 20%
`
`so ± 20%
`
`95 ± 20%
`
`so
`
`Etch Process for Forming the Contacts 55a-55c of
`FIGS 4-5 Using an Applied 5300 Ccntura HDP
`Oxide Etcher
`
`As Table I illustrates, the contacts illustrated in PIGS 4
`55 through 5 are formed by a three step etch process. A first
`step, which is referred to as the main contact etch, i used to
`form the opemnings 55a 55c as they are illustrated in FIG 4
`The main contact etch of Table I shows values for preferred
`power, pressure, etch time, and gas flow wherein these
`5n preferred values can be altered around the middle optimal
`operating point by roughly 20%.
`Table 1 also illustrates the resist strip and taper etch which
`is used in FIG. 5 to remove the photoresist 54 in an in situ
`manner, to taper the top portions of the openings 55a
`through 55c, and to remove the portion of the layer 38 within
`the opemng 55a. The time needed to perform the resist strip
`and taper etch can vary around a preferred time of sixty
`
`c5
`
`Petitioner Nanya Technology Corp. - Ex. 1002, p. 17
`
`

`
`US 6,372,638 B1
`
`seconds by up to 50% due to the fact that the taper profile
`can be controlled significantly by controlling etch time.
`Some tungsten deposition processes and equipment may
`require more or less Y-radius taper than other tungsten
`processes, or etch time may be used to control the shape of
`the taper. The amount of taper required is also a function of
`the aspect ratio of the contac openings which are mitially
`formed in FIG. 4
`In addition to the main contact etch followed by the resist
`strinp and taper etch, a final polymer etch removal etch step
`as illustrated in Table 1. The third etch step of Table 1,
`referred to as the polymer removal step, removes polymer
`byproducts of the etch plasma from the contact openings
`and/or oxide surfaces Typically, polymers are intended to be
`formed on various integrated circuits surlaces during etching
`in order to effect selectivity of the etch process. While these
`polymer layers are beneficial to selectivity, they should be
`subsequently removed to avoid sigmficant contact resistance
`deviations, adhesion problems, open circuits, etc. This final
`etch step therefore ensures that any of these polymer
`byproducts are properly removed so that the final contact
`structure is not adversely efecited
`After formation of the etch contact as illustrated in FIG.
`5, a tungsten (W) deposition process is performed to form a
`layer of tungstcn 56 as shown in FIG. 6 Due to the
`tapered/rounded "golf
`tee" corners of the contacts 55a
`through 55c an FIG 5, the inherent nonconform