(12)
`
`United States Patent
`Rodriguez et al.
`
`(10) Patent N0.:
`(45) Date of Patent:
`
`US 6,372,638 B1
`Apr. 16, 2002
`
`US006372638B1
`
`(54) METHOD FOR FORMING A CONDUCTIVE
`PLUG BETWEEN CONDUCTIVE LAYERS ()1?
`AN INTEGRATED CIRCUIT
`
`2/1993 Cronin et al. ............. .. 257/752
`5,189,506 A
`5,854,140 A * 12/1998 Jaso ......................... .. 438/740
`6,143,648 A * 11/2000 Rodriguez et al. ........ .. 438/640
`
`(75) Inventors: Robert Arthur Rodriguez; Heather
`Marie Klesat, both of Austin, TX (US)
`
`(73) Assigneer Motorola, 1116-, schallmbllfg, IL (Us)
`
`(*) Noticer
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21) Appl- No-3 09/599,378
`-
`22 F1 01:
`.22 2000
`1 6
`(
`)
`Jun
`’
`Related US. Application Data
`
`(63) Continuation of application No. 08/802,299, ?led on Feb.
`18: 1997: now Pat NO- 671437648
`(51) Int. c1.7 .......................................... .. H01L 21/4763
`(52) US. Cl. ..................... .. 438/640; 438/633; 438/637;
`438/673; 438/713; 257/752; 257/774
`(58) Field of Search
`438/637 638
`438
`620 622’ 713’
`67’3_ 25’7/752’ 750’ 774;
`’
`’
`’
`References Cited
`
`’
`
`’
`
`(56)
`
`US. PATENT DOCUMENTS
`
`4,908,333 A
`
`3/1990 Shimokawa et al. ...... .. 438/624
`
`4,970,573 A 11/1990 Roberts et al. . . . . . .
`
`. . . .. 357/71
`
`156/643
`3/1991 Madokoro ...... ..
`4,997,518 A
`357/71
`9/1991 Ajika et al.
`5,049,975 A
`5,082,801 A * 1/1992 Nagata ..................... .. 438/640
`
`OTHER PUBLICATIONS
`
`Kaanta et al., “Dual Damascene: A ULSI Wiring Technol
`ogy,” VMIC Conference, 9 pgs. (1991).
`Kaufman et al., “Chemical—Mechanical Polishing for Fab
`ricating Patterned W Metal Features as Chip Interconnects,”
`J. Electrochem. Soc. VOl. 138, NO. 11, pp. 3460—3464
`(1991)_
`
`ABSTRACT
`
`* cited by examiner
`Primary Examiner—Charles BoWers
`Assistant Examiner—Hsien-Min Lee
`g
`(74) Attorney, Agent, or Firm—Robert A. Rodriguez; Keith
`E- Wltek
`57
`(
`)
`A method for forming void free tungsten plug contacts
`(566F566) begins by etching 499mm Opening (55_a—55c_)
`‘15mg a C2136 and CHF3 chemlstry- The eFCh Che/“115F715
`then changed to an O2 and CH3F chemistry in order to msitu
`remove the contact photoresist While tapering an upper
`portion of the contact opening. A tungsten deposition pro
`cess is then performed Whereby the tapered portion of the
`contact reduces the effects of nonconformal and step
`coverage-inconsistent tungsten deposition Wherein voids in
`the contact are either substantially reduced or totally avoided
`Within the contact structure. The reduction of or total elimi
`nation of voids (22) Within the tungsten contact Will increase
`yield, increase reliability, and reduce electromigration fail
`‘Hes Wlthln mtegrated 61mm devlces
`
`_
`
`_
`
`_
`
`_
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`_
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`_
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`11 Claims, 5 Drawing Sheets
`
`L s
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`jo
`
`Petitioner Nanya Technology Corp. - Ex. 1001, p. 1
`
`

`
`U.S. Patent
`
`Apr. 16, 2002
`
`Sheet 1 of 5
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`US 6,372,638 B1
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`/13
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`10
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`-PRIOR ART-
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`FIG.2
`
`FIG’. 3
`-PRIOR ART-
`
`Petit10ne1'Nanya Technology Corp. - Ex. 1001, p. 2
`
`Petitioner Nanya Technology Corp. - Ex. 1001, p. 2
`
`

`
`U.S. Patent
`
`Apr. 16, 2002
`
`Sheet 2 6f 5
`
`US 6,372,638 B1
`
`6
`
`5_2
`
`30
`1
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`z a
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`40 36
`34
`
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`44
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`42
`
`46
`
`44
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`FIG. 5
`
`Petitioner Nanya Technology Corp. - Ex. 1001, p. 3
`
`

`
`U.S. Patent
`
`Apr. 16, 2002
`
`Sheet 3 6f 5
`
`US 6,372,638 B1
`
`48
`
`/ //|
`
`FIG. 6'
`
`FIG. 7
`
`Petitioner Nanya Technology Corp. - Ex. 1001, p. 4
`
`

`
`U.S. Patent
`
`Apr. 16, 2002
`
`Sheet 4 of 5
`
`US 6,372,638 B1
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`fl/
`“ |Wfl
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`3
`
`44
`
`FIG. .9
`
`Petitioner Nanya Technology Corp. - Ex. 1001, p. 5
`
`Petitioner Nanya Technology Corp. - Ex. 1001, p. 5
`
`

`
`U.S. Patent
`
`Apr. 16, 2002
`
`Sheet 5 6f 5
`
`US 6,372,638 B1
`
`Petitioner Nanya Technology Corp. - Ex. 1001, p. 6
`
`

`
`US 6,372,638 B1
`
`1
`METHOD FOR FORMING A CONDUCTIVE
`PLUG BETWEEN CONDUCTIVE LAYERS OF
`AN INTEGRATED CIRCUIT
`
`This is a continuation of US. patent application Ser. No.
`08/802,299, ?led on Feb. 18, 1997 now US. Pat. No.
`6,143,643, Which is hereby incorporated by reference, and
`priority thereto for common subject matter is hereby
`claimed.
`
`FIELD OF THE INVENTION
`
`The present invention relates generally to integrated cir
`cuit manufacturing, and more particularly to, a method for
`forming tungsten contact plugs in a void-free manner.
`
`BACKGROUND OF THE INVENTION
`In the integrated circuit (IC) industry, contacts betWeen
`polysilicon layers and/or metal layers are sometimes formed
`using tungsten plugs. As advances are made in lithographic
`processing and etch technology, the radial opening of an
`integrated circuit contact continues to shrink While the
`vertical depth of integrated circuit contacts have been
`increasing. This increase in contact aspect ratio (depth/
`radius) creates reliability and manufacturing problems When
`using tungsten deposition and chemical mechanical polish
`ing (CMP) technology to form tungsten plugs.
`The problems arise When tungsten
`continues in the
`industry to be used to plug large aspect ratio contacts is
`illustrated in prior art FIGS. 1—3. As is knoWn in the art,
`tungsten deposition suffers from highly nonconformal depo
`sition characteristics, also referred to as inconsistent step
`coverage. The adverse effects of this non-conformal nature
`of tungsten deposition is illustrated in FIGS. 1—3.
`In FIG. 1, a contact structure 10 is formed by initially
`providing a base layer 12. A ?rst conductive layer 14 is
`formed on top of the base layer 12. Layer 14 is lithographi
`cally patterned and etched. A dielectric layer 16 is formed
`overlying the patterned layer 14. The dielectric layer 16 is
`then patterned then etched to form a contact opening 18
`Which has a substantially uniform radius X at all elevations
`through the contact 18 of FIG. 1. FIG. 1 illustrates the
`beginning of the tungsten deposition process Which forms an
`initial tungsten layer 20a.
`In FIG. 1, tungsten is deposited in a highly nonconformal
`manner. In other Words, top surfaces of the dielectric layer
`16 Will accumulate tungsten material at a much faster rate
`than the bottom comers of the contact opening 18.
`Therefore, the shape of the initial stages of tungsten depo
`sition is accurately illustrated in FIG. 1 Whereby top portions
`of the dielectric layer 16 have accumulated a greater thick
`ness of tungsten than loWer portions of the contact opening
`18.
`In FIG. 2, tungsten deposition continues to transform the
`thinner tungsten layer 20a in FIG. 1 to a thicker tungsten
`layer 20b in FIG. 2. The tungsten, Which continues to deposit
`in FIG. 2, is also nonconformal and deposits more along the
`top eXposed surfaces of layer 20a and less along the side
`Walls and bottom portion of the contact 18. Due to this
`nonconformal deposition, many contacts formed using a
`tungsten deposition process Will form keyholes or voids 22
`as illustrated in FIG. 2. These voids form from the noncon
`formal deposition nature of tungsten “pinching off” the top
`opening in the contact hole. The voids 22 resulting from this
`nonconformal step coverage of tungsten create depressed
`yields, nonfunctional IC die from electrical open circuits,
`and electromigration failures over time. Therefore, the pres
`
`10
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`15
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`20
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`25
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`30
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`35
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`45
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`2
`ence of the voids 22 in high aspect ratio contacts are
`disadvantageous and a signi?cant problem for integrated
`circuit (IC) processing.
`FIG. 3 illustrates that a chemical mechanical polishing
`(CMP) operation is used to form the tungsten plug 20c
`illustrated in FIG. 3. Note that the void 22 is still present
`Within the contact structure after polishing and therefore is
`still problematic in the ?nal integrated circuit (IC) device.
`Therefore, a need eXists for a IC contact formation
`process Which continues to utiliZe nonconformal tungsten
`deposition processes While resulting in reduced or totally
`eliminated void formation.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIGS. 1 through 3 illustrate, in cross-sectional diagrams,
`a method for forming a prior art contact structure containing
`unWanted voids.
`FIGS. 4 through 7 illustrate, in cross-sectional diagrams,
`a method for forming void free tungsten plug contacts in
`accordance With the present invention.
`FIGS. 8 through 11 illustrate, in cross-sectional diagrams,
`an alternative method for forming void free tungsten plug
`contacts in accordance With the present invention.
`
`DETAILED DESCRIPTION OF THE DRAWINGS
`
`Generally, the present invention is a method for forming
`a void free tungsten plug contact. The process herein can
`utiliZe the same conventional tungsten deposition processes
`Which are highly nonconformal and have step coverage
`problems Without resulting in the void formation illustrated
`in the FIGS. 1 through 3. Generally, the nonconformal or
`step coverage problem of conventional tungsten
`depo
`sition is compensated for by altering the contact pro?le to a
`tapered contact unlike the constant radius X contact illus
`trated in FIG. 1. By using unique etch chemistries to taper
`the sideWall pro?le of contacts to form a “golf tee” contact
`pro?le or a “Wine glass” contact pro?le, conventional non
`conformal and step coverage limited tungsten processing
`can be used to form tungsten plug contacts With high aspect
`ratios that have improved yield, greater functional die per
`Wafer, and improved electromigration resistance. In general,
`void-free or void-reduced contacts formed as taught herein
`result in integrated circuits (ICs) being formed With higher
`aspect ratio contacts at a higher yield. In addition, most
`alterations of contact pro?les result in adversely affecting
`design rule spacing of contact structures. HoWever, the
`contact pro?le processes taught herein can be utiliZed With
`out adversely effecting contact spacing design rules since a
`chemical mechanical polish (CMP) process is used to
`remove the Widened “golf tee” or “Wine glass” contact
`pro?le alterations in a ?nal step so that contact spacing is not
`adversely effected.
`The invention can be further understood With reference to
`FIGS. 4 through 11.
`FIGS. 4 through 7 illustrate a ?rst method for forming a
`void free tungsten
`plug contact structure. FIG. 4 illus
`trates a substrate 32. Substrate 32 is typically a silicon Wafer
`but can also be a gallium arsenide Wafer, a germanium doped
`layer, epitaxial silicon, a silicon-on-insulator (SOI)
`substrate, or any like integrated circuit substrate. A gate
`oXide layer 34 is formed overlying the substrate 32. Gate
`oXide layer 34 is typically a thermally groWn oXide Within
`the range of 35 A to 120
`In alternate embodiments, the
`gate oXide 34 can be a composite dielectric comprising
`deposited and/or thermally groWn dielectric materials. In
`
`Petitioner Nanya Technology Corp. - Ex. 1001, p. 7
`
`

`
`US 6,372,638 B1
`
`3
`addition, the gate oxide 34 may be exposed to a nitrogen or
`?uorine ambient to incorporate one of either nitrogen or
`?uorine Within the gate oxide 34 to improve overall gate
`oXide reliability.
`A polysilicon or amorphous silicon layer 36 is then
`deposited over the gate oXide 34. The layer 36 may be
`formed in a single deposition process or in an A-poly/B-poly
`process Which is knoWn in the art. The layer of polysilicon
`or amorphous silicon 36 can be optionally silicided via
`eXposure to an environment containing a refractory metal. In
`addition, the layer of polysilicon or amorphous silicon 36 is
`covered With a capping layer 38 illustrated in FIG. 4. In a
`preferred form, the capping layer 38 is silicon nitride, but the
`capping layer can be any dielectric or conductive layer
`Which performs either an etch stop function and/or anti
`re?ective coating (ARC) function. The layer of polysilicon
`or amorphous silicon 36 as Well as any silicide and/or
`capping layer 38 formed over the layer 36 are then photo
`lithographically patterned and etched as a stack to form gate
`electrode portions 36 on the integrated circuit (IC). In
`addition to forming gate electrodes, portions of layer 36 may
`be lithographically formed for contact regions, buried
`contacts, or like polysilicon structures.
`After formation of the gate electrode 36 in FIG. 4,
`sideWall spacers 40 are made in order to enable lightly doped
`drain (LDD) current electrode formation. The eXact current
`electrodes (source and drain) are not speci?cally illustrated
`in FIG. 4. A ?rst tetraethylorthosilicate (TEOS) layer 42 is
`then formed overlying the spacers 40 in FIG. 4. Other oXides
`and dielectrics as are knoWn in the art may replace the
`speci?c dielectrics and/or oXides taught herein to create
`other embodiments. A second layer of polysilicon and/or
`amorphous silicon 44 is deposited and patterned in FIG. 4.
`Overlying the layer 44, another TEOS layer 46 is deposited.
`After deposition of the TEOS layer 46, a third polysilicon or
`amorphous silicon layer is deposited and patterned to form
`polysilicon regions 47 as illustrated in FIG. 4. Overlying
`region 47 is another TEOS layer 48, folloWed by a boro
`phosphosilicate glass (BPSG) layer 50. Layer 50 is folloWed
`by yet another TEOS layer 52. It should be noted herein that
`the dielectric layers and conductive layers taught herein can
`be replaced equivalent dielectric and conductive materials as
`is knoWn in the art (e.g., silicided polysilicon may replace
`unsilicided amorphous silicon in some embodiments).
`Once the TEOS layer 52 is formed, a photoresist layer 54
`is formed on the Wafer. The photoresist 54 is then selectively
`eXposed using conventional photoresist processing. The
`photoresist is then developed to form openings 55a through
`55c Within the photoresist layer 54 as illustrated in FIG. 4.
`After de?ning the opening in the photoresist layer 54, the
`layers 52, 50, 48, 46, and 42 are then etched in FIG. 4 using
`a C2F6 and CHF3 etch environment to eXtend the opening
`deeper into the semiconductor device.
`In the case of contact 55a, the C2F6 and CHF3 etch
`chemistry is selective to the nitride layer 38 so that the
`contact 55a Will continue to etch/deepen until the capping
`layer 38 is eXposed (at Which time etching Will signi?cantly
`reduce in rate). In the case of the contact 55b of FIG. 4, the
`C2F6 and CHF3 etch chemistry is selective to the semicon
`ductor substrate 32. Furthermore, the C2F6 and CHF3 used
`to etch the contact 55c is selective to the polysilicon and/or
`amorphous silicon 44. Therefore, the three contact openings
`55a through 55c are formed as illustrated in FIG. 4 using a
`reactive ion etch (RIE) or like plasma etch environment. In
`addition, it is important to note that there are other oXide etch
`chemistries and processes other than C2F6 and/or CHF3
`Which may be used herein to etch the contacts 55a through
`55c.
`
`10
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`30
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`60
`
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`
`4
`FIG. 5 illustrates that the photoresist 54 of FIG. 4 is
`removed. This removal can be performed in one of tWo
`manners. In a preferred form, the photoresist 54 is removed
`from the Wafer by using an in situ CH3F and O2 etch
`environment. In another form, a purely eXsitu O2 chemistry
`may be used to remove the photoresist in a different pro
`cessing chamber other than the etch chamber than the
`chamber used to perform the etching illustrated in FIG. 4.
`After the photoresist 54 is removed from the Wafer in FIG.
`5, the Wafer is eXposed to a CH3F and O2 environment to
`perform tapering of an upper portion of the contact openings
`55a through 55c. In a preferred form, the CH3F etch
`chamber and etch plasma used to perform the contact taper
`process in the same or similar process used to perform the
`preferred in situ photoresist removal. In addition, the same
`CH3F etch chamber and etch plasma used to perform the
`contact taper process can simultaneously be used to remove
`the silicon nitride used to form the capping layer 38 from the
`bottom of the contact opening 55a as shoWn in FIG. 5.
`As illustrated in FIG. 5, the contact tapering operation
`results in an upper portion of the contacts 55a through 55c
`being enlarged to a radius Y Wherein the radius Y of FIG. 5
`is greater than the radius X formed via the etching of FIG.
`4. The radius X of FIG. 5 is identical to the radius X of FIG.
`1, and is typically a minimum lithographic dimension
`alloWed by the speci?c lithographic equipment utiliZed in
`the manufacture of the contact structure. The eXposure of the
`Wafer to the CH3F and O2 plasma etch environment results
`in a rounding of the upper corners of the contact openings
`55a through 55c to form a “golf tee” pro?le. In Table 1
`beloW, the etch process discussed above With respect to FIG.
`4 through FIG. 5 is summariZed in a Table 1:
`
`TABLE 1
`
`Main Contact Resist Strip
`Etch
`and Taper Etch
`
`Polymer
`Removal Step
`
`2800 r 20%
`
`1800 r 20%
`
`2600 r 20%
`
`1400 r 20%
`
`250 r 20%
`
`300 r 20%
`
`10 r 20%
`
`20 r 20%
`
`25 r 20%
`
`210 r 20%
`40 r 20%
`15 r 20%
`
`75 r 20%
`
`60 r 50%
`
`60 r 20%
`
`40 r 20%
`
`80 r 20%
`
`95 r 20%
`
`Source Power
`(Watts)
`Bias Power
`(Watts)
`Pressure (mTorr/
`Tv)
`Time (sec)
`C2F6 (sccm)
`CHF3 (sccm)
`CH3F (sccm)
`He (sccm)
`O2 (sccm)
`
`Etch Process for Forming the Contacts 55a—55c of
`FIGS. 4—5 Using an Applied 5300 Centura HDP
`Oxide Etcher
`
`As Table 1 illustrates, the contacts illustrated in FIGS. 4
`through 5 are formed by a three step etch process. A ?rst
`step, Which is referred to as the main contact etch, is used to
`form the openings 55a—55c as they are illustrated in FIG. 4.
`The main contact etch of Table 1 shoWs values for preferred
`poWer, pressure, etch time, and gas ?oW Wherein these
`preferred values can be altered around the middle optimal
`operating point by roughly 20%.
`Table 1 also illustrates the resist strip and taper etch Which
`is used in FIG. 5 to remove the photoresist 54 in an in situ
`manner, to taper the top portions of the openings 55a
`through 55c, and to remove the portion of the layer 38 Within
`the opening 55a. The time needed to perform the resist strip
`and taper etch can vary around a preferred time of siXty
`
`Petitioner Nanya Technology Corp. - Ex. 1001, p. 8
`
`

`
`US 6,372,638 B1
`
`10
`
`15
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`20
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`25
`
`5
`seconds by up to 50% due to the fact that the taper pro?le
`can be controlled signi?cantly by controlling etch time.
`Some tungsten deposition processes and equipment may
`require more or less Y-radius taper than other tungsten
`processes, or etch time may be used to control the shape of
`the taper. The amount of taper required is also a function of
`the aspect ratio of the contact openings Which are initially
`formed in FIG. 4.
`In addition to the main contact etch folloWed by the resist
`strip and taper etch, a ?nal polymer etch removal etch step
`is illustrated in Table 1. The third etch step of Table 1,
`referred to as the polymer removal step, removes polymer
`byproducts of the etch plasma from the contact openings
`and/or oXide surfaces. Typically, polymers are intended to be
`formed on various integrated circuits surfaces during etching
`in order to effect selectivity of the etch process. While these
`polymer layers are bene?cial to selectivity, they should be
`subsequently removed to avoid signi?cant contact resistance
`deviations, adhesion problems, open circuits, etc. This ?nal
`etch step therefore ensures that any of these polymer
`byproducts are properly removed so that the ?nal contact
`structure is not adversely effected.
`After formation of the etch contact as illustrated in FIG.
`5, a tungsten
`deposition process is performed to form a
`layer of tungsten 56 as shoWn in FIG. 6. Due to the
`tapered/rounded “golf tee” corners of the contacts 55a
`through 55c in FIG. 5, the inherent nonconformal step
`coverage characteristics of tungsten deposition processing
`are compensated for so that keyhole or voids are reduced or
`totally eliminated Within the contact openings 55a—55c.
`While voids have noW been avoided, the issue of leaving
`Wider Y radius contacts intact on a substrate is problematic.
`The larger the opening of any portion of a contact, the
`greater the spacing betWeen contacts must be to avoid
`electrical cross-coupling or to avoid photographic misalign
`ment defects. Therefore, subsequent processing in FIG. 7 is
`used to remove the Wider contact portion Y to leave behind
`only the smaller void-free contact portion X so that design
`rules are not compromised by the void-free etch process
`discussed above.
`In essence, as is illustrated in FIG. 6, an upper portion of
`the contacts 55a through 55c Will contain a Wider portion Y
`of conductive material than loWer portions of the contact
`having a radius X. If the upper portion having a radius Y
`45
`Were alloWed to remain on the ?nal semiconductor device,
`physical design rule spacing betWeen contacts Would be
`increased and the siZe of memory cells and like spacing
`critical structures Would be adversely affected. To remedy
`this problem, a CMP process is used not only to form the
`actual tungsten
`plugs themselves, but to remove the
`taper Y from the ?nal contact structure so that dose contact
`pitch design rules can be preserved in the design rules to
`maXimal circuit densities.
`To this end, FIG. 7 illustrates a chemical mechanical
`polishing (CMP) process Which is used to planeriZe surfaces
`to form plug regions 56a through 56c in FIG. 7 and to
`remove the Widened, tapered, upper contact pro?le Y of all
`of the contacts 55a through 55c. The resulting contacts of
`FIG. 7 are void free tungsten plugs Which are improved over
`the prior art illustrated in FIG. 3. It is important to note that
`a polish stop layer (e.g. silicon nitride, not speci?cally
`illustrated in FIGS. 4—7) can be optionally formed betWeen
`the layers 50 and 52 of FIG. 4 to improve the polish process
`at the eXpense of complicating the contact etch process. In
`another, more preferred embodiment, a timed polish process
`can be utiliZed With no need for a polish stop layer. Any
`
`30
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`60
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`
`6
`top
`polish process Which removes both the tungsten
`portions and the TEOS/BPSG oXides may be utiliZed in FIG.
`7.
`It is important to note that the layer 50 of FIG. 7 is
`preferably a BPSG layer. These doped oXide layers are
`typically not alloWed to be in contact With conductive layers.
`For this reasons, at least a thin portion of TEOS layer 52 is
`left overlying the surface of the BPSG layer 50 after CMP
`operations to ensure that the BPSG layer is properly insu
`lated from overlying conductive layers (subsequently
`formed and not illustrated in FIG. 7). The thickness of layer
`52 can be adjusted to ensure proper BPSG isolation as is
`needed in the ?nal contact structure.
`It is important to note that the device of FIGS. 4 through
`7 is preferably a static random access memory (SRAM) cell.
`In this preferred SRAM embodiment, the layer 36 is a gate
`electrode for a MOS transistor Within an SRAM cell. The
`layer 44 is used to form SRAM output node contacts to the
`storage nodes of the SRAM cell. The layer 47 is a thin layer
`of polysilicon less than 1000 A in thickness Which is used to
`form a polysilicon resistor for the SRAM cell, In the
`alternative, the layer 47 may be used to form a thicker thin
`?lm transistor (TFT) structure Within the SRAM cell in
`place of polysilicon SRAM load resistors. Therefore, FIG. 7
`illustrates that the contacts 55a through 55c may be used to
`contact three different conductive levels Within an integrated
`circuit (IC) and preferably Within an SRAM cell. It is
`important to note that this contact process may also be used
`in microprocessors, other memory devices (i.e., EEPROM,
`EPROM, DRAM, ferroelectric devices, ?ash memory, etc.)
`or any semiconductor device fabrication process using plug
`contacts.
`FIGS. 8 through 11 illustrate an alternate embodiment of
`the present invention Whereby void free tungsten
`plug
`contacts can be formed. The layers or material 32 through 54
`of FIG. 8 are identical or very similar to the material
`discussed in FIGS. 4 through 7. Identical layers betWeen
`FIGS. 4—7 and FIGS. 8—11 are labeled With identical refer
`ence numerals and not further explained beloW.
`FIG. 8 illustrates the photoresist layer 54. The photoresist
`layer is patterned With the three openings 55a through 55c
`similar to that illustrated in FIG. 4. The dielectric layer 52
`of FIG. 8 is then eXposed to an isotropic etch chemistry. A
`typical isotropic etch process comprises pressuriZing a
`chamber to 1400 millitorr. This chamber is provided With an
`RF poWer of 700 Watts, an NF3 How of 480 ccm, a helium
`(He) carrier gas How of 540 ccm, for a time duration of
`roughly thirty seconds. The exposure to this NF3 etch
`chemistry results in a boWl-shaped, tapered pro?le, referred
`to as a “Wine glass” pro?le, as illustrated in FIG. 8.
`Once the isotropic etch of FIG. 8 is performed, a reactive
`ion etch (RIE) or a like plasma etch is utiliZed, as discussed
`previously for FIG. 4, to form the remaining portion of the
`contact opening illustrated in FIG. 9. In addition, a silicon
`nitride etch step is then used to remove the nitride capping
`layer 38 off of the polysilicon gate electrode 36 of FIG. 9 in
`either an eXsitu or in situ manner. Therefore, the contact
`structures 55a through 55c of FIG. 9 have a tapered structure
`Wherein an upper radius of the contact has a radius Y and a
`loWer portion of the contact has a radius X similar to that
`illustrated in FIG. 5. Unlike the anisotropic plasma etch
`taper process illustrated in FIG. 5, the isotropic taper process
`of FIG. 9 results in a differently-sloped contact pro?le. The
`pro?le of FIG. 4 is referred to as a “golf tee pro?le”.
`Whereas, the pro?le of FIG. 9 is a “Wine glass” pro?le.
`In FIG. 10, the photoresist layer 54 of FIG. 9 is removed
`either via an in situ etch or an eXsitu process comprising one
`
`Petitioner Nanya Technology Corp. - Ex. 1001, p. 9
`
`

`
`US 6,372,638 B1
`
`7
`or more of O2 and CH3F. Once the photoresist layer 54 has
`been removed, a tungsten
`deposition process is per
`formed in order to form a tungsten layer 56 as illustrated in
`FIG. 10. The presence of the upper tapered contact portion,
`having a radius of roughly equal to Y, results in the reduction
`or total elimination of the void formation associated With the
`nonconformal step coverage typically associated With tung
`sten deposition.
`As also illustrated in FIG. 7, FIG. 11 illustrates a chemical
`mechanical polish (CMP) step Which is used to polish the
`top isotropically etched portion Y of the contact pro?les as
`Well as top portions of the tungsten 56 to form a conductive
`contact plug. This CMP process not only forms the tungsten
`plugs 56a through 56c in FIG. 11 but also ensures the same
`minimal spacing separation distances for design rules
`formed used for conventional voided contacts of FIGS. 1—3.
`Therefore, it is apparent that there has been provided, in
`accordance With the present invention, a method for forming
`a tungsten
`contact structure in a void free manner.
`Although the invention has been described and illustrated
`With reference to speci?c embodiments, it is not intended
`that the invention be limited to these illustrative embodi
`ments. The method taught herein can be used for forming
`dual Damascene or dual inlaid contact structures as Well as
`plug contact structures. The process taught herein can be
`
`utiliZed With other metallic material other than tungsten For eXample, aluminum, copper, or like conductive materi
`als can be formed using the contact pro?le techniques taught
`herein. Therefore, those skilled in the art Will recogniZe that
`modi?cations and variations may be made herein Without
`departing from the spirit and scope of the invention.
`Therefore, it is intended that this invention encompass all
`variations and modi?cations as fall Within the scope of the
`appended claims.
`What is claimed is:
`1. A method for forming a contact structure, the method
`comprising the steps of:
`forming a ?rst conductive material overlying a semicon
`ductor substrate;
`forming a dielectric layer overlying the ?rst conductive
`layer;
`forming a resist layer over the dielectric layer;
`patterning the resist layer to form an opening that exposes
`portions of the dielectric layer;
`placing the semiconductor substrate into a reactive ion
`etching chamber and in-situ processing the semicon
`ductor substrate as folloWs:
`etching portions of the dielectric layer using a gas
`miXture that includes a ?uorocarbon source gas to
`form an opening in the dielectric layer, the opening
`having a bottom portion and a sideWall portion;
`etching a portion of the resist layer using a gas mixture
`that includes a ?uorocarbon source gas and an oXy
`gen source gas to remove the portion of the resist
`layer and eXpose a top surface portion of the dielec
`tric layer adjacent the sideWall portion;
`etching the top surface portion of the dielectric layer
`adjacent the sideWall portion to form a taper that
`eXtends betWeen a top surface of the dielectric layer
`and the sideWall portion, Wherein the taper toWards
`the top surface portion has a radius Y and the taper
`toWards the sideWall portion has a radius X Wherein
`X<Y; and
`removing remaining portions of the resist layer;
`depositing a second conductive material Within the open
`ing; and
`polishing aWay a top portion of the conductive material
`and a top portion of the dielectric layer to remove the
`taper.
`
`15
`
`25
`
`35
`
`55
`
`8
`2. The method of claim 1, Wherein the second conductive
`material comprises tungsten.
`3. The method of claim 1, Wherein removing remaining
`portions of the resist layer is performed as part of in
`situ-processing in the reactive ion etching chamber.
`4. The method of claim 1 further comprising using the top
`portion of the opening having the radius Y to reduce void
`formation in the contact structure due to the step of depos
`iting.
`5. The method of claim 1, Wherein the step of forming the
`?rst conductive layer comprises forming the ?rst conductive
`layer as a gate electrode Which gates a transistor in an
`SRAM cell.
`6. The method of claim 1, Wherein forming the ?rst
`conductive layer is further characteriZed as forming a poly
`silicon layer Which is coupled to a storage node of an SRAM
`cell.
`7. The method of claim 1, Wherein the step of forming the
`?rst conductive layer comprises forming the ?rst conductive
`layer as a doped current electrode for a transistor Within a
`substrate, the transistor being coupled in an SRAM cell.
`8. Amethod for forming an integrated circuit, the method
`comprising:
`patterning a resist layer over a dielectric layer;
`anisotropically etching portions of the dielectric layer
`eXposed by the resist layer to de?ne an opening in the
`dielectric layer, Wherein:
`the opening includes a top portion that is adjacent an
`upper surface of the dielectric layer, a bottom portion
`that is opposite the top portion, and a sideWall
`portion that is disposed betWeen the top portion and
`the bottom portion;
`removing the resist layer;
`tapering the top portion of the opening using an aniso
`tropic etching process after removing of the resist layer;
`depositing a material over portions of the upper surface of
`the dielectric layer and Within the opening; and
`polishing to remove (1) the material over portions of the
`upper surface of the dielectric layer and (2) the top
`portion of the opening including the taper and portions
`of the material contained Within the top portion.
`9. The method of claim 8, Wherein the material includes
`a conductive material.
`10. The method of claim 9 Wherein the conductive mate
`rial is further characteriZed as a tungsten material.
`11. Amethod for forming an integrated circuit, the method
`comprising: pattering a resist layer over a dielectric layer;
`anisotropically etching portions of the dielectric layer
`eXposed by the resist layer to substantially de?ne a top
`portion of the opening that is adjacent an upper surface
`of the dielectric layer, a bottom portion of the opening
`that is opposite the top portion, and a sideWall portion
`of the opening that is disposed betWeen the top portion
`and the bottom portion;
`tapering the top portion of the opening using an aniso
`tropic etch process While removing the resist layer;
`depositing a material over portions of the upper surface of
`the dielectric layer and Within the opening; and
`polishing to remove the material over portions of the
`upper surface of the dielectric layer and the top portion
`of the opening including the taper and portions of the
`material contained Within the top portion.
`
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