--",.'-.~-
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`......
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`fiB 006120
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`!
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`!
`1
`•
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`""
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`001
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`P'i'Q-155/i
`(stS7)
`
`Petitioner Samsung - SAM1012
`
`

`
`BAR CODE LABEL
`
`I
`
`11111111111111111111111
`
`U.S. PATENT APPLICATION
`
`SERIAL NUMBER
`
`FILING DATE
`
`CLASS.
`
`-
`GROUP ART UNIT
`
`08/006,120
`lD
`
`.
`
`01/19/93
`OA- ,;),~-J._J
`
`lb ,~ .. '?"""· -·~· ~."""""'
`
`437
`
`1107
`
`T/ MALLOY, _OCEANSIDE,~
`
`RONALD M FINNILA, CARLSBAD, CA.~
`.
`-0)
`.
`
`,.
`
`**CONTINUING DATA*********************
`VERIFIED
`
`**FOREIGN/PCT APPLICATIONS***~********
`VERIFIED
`
`FOREIGN FILING LICENSE GRANTED 07/07/93
`
`STATE OR
`COUNTRY
`
`SHEETS
`DRAWING
`
`TOTAL
`CLAMS
`
`INDEPENDENT
`CLAMS
`
`FILING FEE
`RECEIVED
`
`ATTORNEY DOCKET NO.
`
`CA
`
`3
`
`21
`
`3
`
`$862.00
`
`PD-92654
`
`HUGHES AIRCRAFT COMPANY
`BLDG. C1 MAIL STATION A-126
`p, 0. BOX 80028
`LOS ANGELES, CA 90080-0028
`
`PROCESS OF MANUFACTURING A MICROELECTRONIC DEVICE USING A REMOVABLE
`SUPPORT SUBSTRATE AND ETCH-STOP
`
`!ll
`;
`
`~
`
`This is to certifJ, that annexed hereto is a true copy from the records of the United States
`Patent and Tra emark Office of the application wh1ch is identified above.
`By authority of the
`COMMISSIONER OF PATENTS AND TRADEMARKS
`
`Date
`
`Certifying Officer
`
`002
`
`

`
`PATENTS
`PD-92654
`
`METHOD OF FABRICATING A MICROELECTRONIC DEVICE
`
`Inventors:
`Joseph J. Bendik
`Gerald T. Malloy
`Ronald M. Finnila
`
`003
`
`

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`-
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`1:
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`-20-
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`0
`
`METHOD OF FABRICATING A MICROELECTRONIC DEVICE
`
`ABSTRACT 'OF THE DISCLOSURE
`
`5
`
`10
`
`15
`
`fabricated by
`is
`A microelectronic device
`furnishing
`a
`first substrate
`(40) having a silicon
`etchable
`layer
`(42),
`a
`silicon dioxide . etch-stop
`(44) overlying
`layer
`the silicon layer (42), and a
`single-crystal
`silicon wafer
`(46) overlying
`the
`(44),
`the wafer (46) having a front
`etch-stop
`layer
`surface
`(52) not contacting
`the etch stop
`layer
`( 44).
`A microelectronic circuit element
`(50) is
`in the· single-crystal silicon wafer (46). The
`formed
`method
`further
`includes attaching the front surface
`the single-crystal silicon wafer (46) to a
`(52) of
`second substrate
`(58),
`and etching away the silicon
`(42) of . the first substrate (40) down to the
`layer
`(44). The second substrate (58) may
`etch-stop
`layer
`also have
`a microelectronic circuit element (58')
`therein
`that can be electrically interconnected to
`the microelectronic circuit element (50) .
`
`. 004
`
`

`
`-------- -----
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`~ ­
`~
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`-1-
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`DB 006120
`J}f)-(j
`7 j;.o /'1)
`METHOD OF FABRICATING A MICROELECTRONIC DEVICE
`
`~CKGROUND OF THE INVENTION
`
`relates
`invention
`This
`to microelectronic
`devices, and, more particularly,
`to a microelectronic
`device
`that
`is moved
`from one
`support to another
`support during fabrication.
`
`5
`
`10
`
`15
`
`Microelectronic devices are normally prepared
`series of steps such as patterning, deposition,
`a
`by
`implantation, growth,
`and etching
`that build up an
`electronic circuit on or near the top surface of a
`thin
`substrate wafer.
`Interconnection pads are
`placed
`on
`the surface of
`the wafer
`to provide
`connec tions
`to
`external
`leads
`or
`to
`other
`microelectronic
`devices.
`Such
`a microelectronic
`device
`is considered
`a two-dimensional structure in
`the plane of the substrate wafer. There are usually
`multiple
`layers
`of
`deposited
`conductors
`and
`insulators, but each ·layer is quite thin. Any height
`of
`the device in the third dimension perpendicular to
`the
`substrate
`surface
`is much
`less
`than
`the
`dimensions
`in
`the plane of the substrate wafer, and
`is often no more than a few thousand Angstroms.
`The microelectronic devices or arrays of such
`devices
`are
`usually placed
`inside
`a protective
`housing
`c al l ed
`a package, with leads or connection
`pads
`extending
`out of
`the package.
`When
`the
`microelectronic devices are
`used,
`a
`number of the
`packages wi t h their contained
`microelectronic devices
`base such as a phenolic
`are normally affixed
`to
`a
`30 plastic board.
`Wires are
`run between the various
`devices
`to .· interconnect them . There may be metallic
`traces , imprinted onto
`the base
`to provide .common
`power, ground,
`and bus connections,
`and
`the base
`itself has external connections. Such boards with a
`
`20
`
`25
`
`005
`
`

`
`-2-
`
`interconnected devices are commonly found
`of
`number
`and military electronics
`both
`consumer
`inside
`For example, an entire microcomputer may
`equipment.
`be assembled as
`a number of microelectronic devices
`such as
`a processor, memory, and peripheral device
`controllers mounted onto a single board.
`The present inventors have determined that for
`some applications
`it would be desirable to stack and
`interconnect
`a
`number
`of
`such
`two-dimensional
`microelectronic devices,
`fabricated on
`a substrate
`wafer,
`the other
`form
`one
`on
`top
`of
`to
`a
`three-dimensional
`device.
`The
`stack might also
`include other circuit elements such as interconnect
`layers
`and
`thin
`film·
`sensors
`as. well.
`To
`interconnect
`the
`stacked wafers using
`leads
`that
`extend
`from
`the pads on the top of one wafer to the
`pads on the top of another wafer, around the sides of
`the wafers, or using plug interconnects or the like,
`would be clumsy,
`space consuming, and impossible to
`do
`for the case of highly complex circuitry requiring
`many interconnects.
`techniques
`to
`fabrication
`In
`considering
`the
`three-dimensional, stacked devices,
`produce
`such
`The
`fragility
`of
`the
`devices
`is
`a
`concern.
`individual substrate wafers and their microelectronic
`circuitry are usually made of fragile semiconductor
`materials,
`chosen
`for
`their
`electronic
`characteristics · rather
`than
`their
`strength or
`fracture
`resistance.
`The selected fabrication
`technique
`cannot
`damage
`the circuitry
`that has
`already been placed onto the substrate wafer.
`to
`Thus,
`there
`is
`a need
`for
`a method
`fabricate
`three-dimensional microelectronic devices
`using stacked substrate wafers with circuitry already
`on
`them.
`·The present invention fulfills this need,
`and further provides related advantages.
`
`5
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`10
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`15
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`20
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`006
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`-3-
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`SUMMARY OF THE INVENTION
`
`10
`
`20
`
`The present invention provides an approach for
`fabricating microelectronic
`devices
`that permits
`three-dimensional manipulations and fabrication steps
`5 with
`two-dimensional devices already deposited upon a
`wafer
`substrate.
`The
`invention
`permits
`microelectronic
`devices
`to
`be
`prepared
`using
`well-established,
`inexpensive
`thin-film deposition,
`etching,
`and patterning
`techniques,
`and then to be
`further processed singly or in combination with other
`such devices, into more complex devices.
`In accordance with the invention, a method of
`fabricating
`a microelectronic device comprises the
`steps of
`furnishing
`a
`first substrate having an
`15 etchable
`layer,
`an etch-stop
`layer overlying
`the
`etchable
`layer,
`and
`a wafer overlying the etch-stop
`layer,
`and
`forming a microelectronic circuit element
`in
`the
`wafer of
`the first substrate. The method
`further
`includes attaching
`the wafer portion of the
`first substrate
`to
`a
`second substrate, and etching
`away
`the etchable
`layer of the first substrate down
`to
`the etch-stop
`layer.
`The second substrate may
`include
`a microelectronic device, and the procedure
`may
`include
`the
`further step of interconnecting the
`25 microelectronic device on
`the first substrate with
`the microelectronic device on the second substrate.
`In
`a
`typical application,
`the
`"back side"
`etch-stop
`layer
`is patterned,
`and
`an electrical
`connection
`to
`the microelectronic circuit element on
`the wafer
`is
`formed
`through
`the etch-stop layer.
`This
`technique permits access to the microelectronic
`circuit element
`from
`the back side.
`Electronic
`connections can
`therefore be made directly to the
`back
`side of
`the wafer layer, and indirectly to the
`front
`side microelectronic circuit element by opening
`
`30
`
`35
`
`'
`i ···~.~.
`t+'"' 1
`
`I
`
`007
`
`

`
`-4-
`
`the back
`from
`interconnects
`front-side
`to
`access
`Such an ability to achieve electronic access
`side.
`can be valuable for some two-dimensional devices, and
`also permits multiple
`two-dimensional devices to be
`stacked one above the other to form three-dimensional
`devices by using
`techniques such as indium bumps to
`form interconnections between the stacked devices.
`the
`In
`a preferred approach
`to practicing
`invention,
`a method of fabricating a microelectronic
`device comprises
`the steps of
`furnishing
`a first
`substrate having
`a silicon etchable layer, a silicon
`dioxide etch-stop
`layer overlying the silicon layer,
`and
`a
`single-crystal silicon wafer overlying
`the
`etch-stop
`layer.
`The wafer has a front surface not
`contacting
`the
`silicon
`dioxide
`layer.
`A
`microelectronic circuit element
`is
`formed
`in
`the
`single-crystal silicon wafer on or through the front
`surface.
`The method further includes attaching the
`front
`surface of the single-crystal silicon wafer to
`a
`first side of a second substrate, and etching away
`the silicon etchable
`layer of
`the first substrate
`down
`to
`the silicon dioxide etch-stop layer using an
`etchant
`that attacks
`the silicon layer but not the
`silicon dioxide
`layer. As discussed previously, the
`silicon dioxide
`layer may
`then be patterned and
`connections formed therethrough.
`The present approach is based upon the ability
`transfer
`a
`thin
`film microelectronic circuit
`to
`element or device
`from one substrate structure to
`The circuit element
`another substrate structure.
`a relatively thick first
`usually
`is
`fabricated with
`support during
`initial
`substrate
`that
`provides
`However, it is difficult
`fabrjcation and handling.
`through
`such
`to achieve electrical connections
`a
`the difficulty
`in
`because
`of
`thick
`subst.rate,
`through-support vias precisely at the
`locating deep,
`insulating
`the
`in
`the difficulty
`required point,
`
`5
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`10
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`20
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`25
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`30
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`35
`
`008
`
`

`
`-5-
`
`10
`
`15
`
`20
`
`walls of deep vias, and the difficulty in filling a
`deep
`via with conducting material.
`The first
`substrate cannot
`simply be removed to permit access
`to
`the bottom side of the electrical circuit element,
`5 as
`the assembly could not be handled in that very
`thin form.
`the present approach, after initial circuit
`In
`element
`fabrication on
`a first substrate structure,
`the electrical circuit element
`is transferred to a
`second substrate structure.
`(If the second substrate
`another microelectronic circuit
`contains
`itself
`element,
`interconnections
`between
`the
`two
`microelectronic circuit elements are made at this
`point, as by using an
`indium-bump technique/epoxy
`technique.) With the circuit element thus supported,
`the
`etchable portion of
`the first substrate
`is
`removed by etching, down to the etch-stop layer. The
`terms
`''etchable"
`and
`•etch-stop" are used herein
`relative
`to
`a
`specific selected etchant. There is
`chosen an etchant
`that
`readily etches the etchable
`layer but has
`a much
`lower etching
`rate for the
`It is understood, however, that the
`layer.
`etch-stop
`may be generally or selectively
`layer
`etch-stop
`other
`techniques, after the etchable
`yet
`etched by
`layer is removed.
`the
`removed,
`is
`layer
`etchable
`the
`Once
`etch-stop layer may be patterned and
`thin
`relatively
`to the microelec-
`to provide access
`through-etched
`tronic
`circuit element,
`including
`its connection
`30 pads,
`through
`the etch-stop layer. Many alternative
`approaches
`are
`possible.
`For
`example,
`the
`two-dimensional
`structure may be used with direct
`back connections and indirect front connections. The
`the
`the bottom of
`on
`area
`surface
`additional
`for deposition of
`space
`l_ayer provides
`35 etch-stop
`The
`traces.
`metallization
`interconnection
`'
`two-dimensional structure may be stacked with other
`
`25
`
`009
`
`

`
`-6-
`
`5
`
`a
`form
`to
`structures
`two-dimensional
`three-dimensional structure. Further circuitry could
`be deposited upon
`the back side of the etch-stop
`layer,
`as needed and per~itted by constraints imposed
`by the front-side circuit element structure.
`Thus,
`the present approach provides a highly
`flexible
`approach
`to
`the
`fabrication of complex
`microelectronic
`devices
`using
`a
`building-block
`approach.
`Other
`features
`and advantages of
`the
`10 present
`invention will be apparent from the following
`more
`detailed
`description
`of
`the
`preferred
`embodiment,
`taken
`in
`conjunction with
`the
`illustrate, py way of
`accompanying drawings, which
`example, the principles of the invention.
`
`15
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`flow
`is a diagrammatic process
`Figure
`1
`the approach of the invention, with the
`diagram
`for
`structure at each stage of fabrication
`indicated
`schematically;
`2 is a schematic side sectional view of
`Figure
`a microelectronic device structure prepared according
`to the procedure of Figure 1;
`Figure
`is a schematic side elevational view
`3
`three-dimensional microelectronic device built
`a
`of
`devices
`using
`the present
`two-dimensional
`from
`approach; and
`is a schematic side elevational view
`Figure
`4
`of a "smart board" configuration.
`
`20
`
`25
`
`DETAILED DESCRIPTION OF THE INVENTION
`
`30
`
`Referring
`practiced by
`
`to Figure 1, the present invention
`first providing a first substrate 40,
`
`is
`
`010
`
`

`
`-7-
`
`15
`
`20
`
`10
`
`5
`
`includes an
`The first substrate 40
`numeral 20.
`etchable
`layer 42,
`an etch-stop layer 44 grown upon
`and overlying
`the etchable
`layer 42,
`and a wafer
`layer 46 bonded to and overlying the etch-stop layer
`44. Such substrates can be purchased commercially.
`In
`the preferred practi·ce ,·-the etchable layer
`a
`layer of bulk silicon about 500 micrometers
`is
`42
`thick and
`the etch-stop
`layer 44
`is
`a
`layer of
`silicon dioxide about 1 micrometer thick. The wafer
`layer 46 is normally thicker than required when it is
`bonded
`to
`the etch stop layer 44, and is thinned to
`the
`required
`final
`thickness.
`A typical thinning
`process
`involves
`·lapping
`followed
`by
`a
`chem-mechanical polish.
`·Preferably, the wafer layer
`46
`is
`a
`layer of single crystal silicon initially
`about 500 micrometers
`thick which becomes, after
`thinning,
`about
`30 nanometers
`to 50 micrometers
`thick.
`These dimensions are not critical, and may be
`varied
`as necessary · ·:foT particular applications.
`(The structure depictions
`in Figures 1-4 are not
`drawn
`to scale.)
`The wafer layer 46 may also be or
`include an
`interconnect material such as a metal or
`other
`structure
`as may
`be appropriate
`for
`a
`particular application.
`In
`the present case, an
`25 optional via opening 48 is provided through the wafer
`layer 46.
`Th·e use of
`this via 48 will become
`apparent from subsequent discussions .
`. The first substrate 40 is prepared by applying
`well-known microelectronic ·techniques.
`The silicon
`30 dioxide etch-stop
`layer 44
`is produced on a bulk
`silicon piece 42 by heating it in an oxygen-hydrogen
`atmosphere at a temperature of about 1100C for a time
`sufficient
`to
`achieve
`the
`desired
`thickness,
`typically about 2 hours.
`The wafer
`layer 46 is
`35 either deposited directly upon the etch-stop layer 44
`or
`fabricated
`separately and bonded to the etch-stop
`layer 46 by
`direct
`interdiffusion, preferably the
`
`011
`
`

`
`-8-
`
`5
`
`10
`
`15
`
`is produced by
`48
`The via
`thinned.
`and
`latter,
`techniques.
`(All
`standard patterning and etching
`or
`"well known"
`references
`herein
`to "standard"
`individual process
`techniques, or the like, mean that
`steps are known generally, not that they are known in
`the present context or combination, or to produce the
`present type of structure.)
`A microelectronic circuit element 50 is formed
`the wafer
`layer 46, numeral 22, working from a
`in
`front exposed side 52. The microelectronic circuit
`element 50 may be of any type, and may itself include
`multiple
`layers
`of
`metals,
`semiconductors,
`insulators, etc.
`Any combination of steps can be
`used,
`including;
`for
`example,
`deposition,
`implantation,
`film growth,
`etching,
`and patterning
`steps.
`As used herein,
`the term "microelectronic
`circuit element"
`is
`to be interpreted broadly, and
`can
`include active devices and passive structure.
`For example,
`the microelectronic circuit element 50
`can
`include many active devices such as transistors.
`Alternatively,
`it may
`be
`simply
`a patterned
`electrical
`conductor
`layer
`that
`is used as
`an
`interconnect between other
`layers of structure in a
`stacked
`three-dimensional device, or may be a sensor
`element.
`important virtue of the present invention
`An
`it
`is operable with
`a wide
`range of
`that
`is
`microelectronic circuit elements 50,
`and therefore
`the
`present
`invention
`is
`not
`limited
`to any
`30 particular circuit element 50.
`In
`the presently
`preferred case,
`the first substrate 40 is silicon
`based,
`and
`therefore
`the microelectronic circuit
`element 50
`is preferably a
`silicon-based device.
`Where
`the microelectronic circuit element 50 is based
`material systems, it may be preferred for
`upon other
`substrate
`to be made of a material
`the
`first
`to
`that material system.
`In this usage,
`compatible
`
`35
`
`20
`
`25
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`'.
`''
`\
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`' \
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`012
`
`

`
`-----------~-- ·--
`
`--------------- ----
`
`-9-
`
`10
`
`15
`
`the first substrate permits
`that
`"compatible" means
`fabrication of the microelectronic circuit element 50
`therein.
`the
`in Figure 1,
`illustrated
`is
`it
`As
`5 microelectronic circuit element 50 includes two types
`of electrical interconnects. A front-side electrical
`interconnect
`54
`permits
`direct
`electrical
`interconnection
`to
`the microelectronic
`circuit
`"above",
`and back-side electrical
`element
`50
`from
`interconnects 56
`and 56' permit indirect front-si~e
`electrical
`interconnection
`to
`the microelectronic
`circuit element
`50
`and direct back-side electrical
`interconnection
`to
`the wafer layer 46 from "below",
`respectively.
`The front-side electrical interconnect
`54
`is
`a metallic pad, and the back-side electrical
`interconnects 56
`and 56' are each an electrical
`conductor
`such as polysilicon or a metal deposited·
`in~o the via 48,
`The
`interconnect 54 is formed
`during
`the fabrication of the microelectronic circuit
`element 50,
`and
`the
`interconnects 56
`and 56' are
`formed by opening_ vias
`through
`the back side-and
`filling
`them with an electrical conductor, all
`well-known techniques.
`the
`to
`is attached
`A
`second substrate 58
`structure on
`the
`side corresponding
`to
`the front
`surface
`52,
`numeral 24.
`That
`is,
`the
`second
`substrate
`is
`on
`the opposite side of
`the
`58
`microelectronic circuit element 50
`from
`the first
`substrate 40.
`The
`second substrate 58 may be any
`suitable material,
`such as silicon or aluminum oxide
`(specifically sapphire).
`The
`second substrate may
`optionally
`include a microelectronic device deposited
`therein.
`(The illustration of Figure 1 does not show
`the structure of the second substrate 58 in detail to
`presented in more
`conserve
`space.
`That structure is
`and 3,
`and
`will be discussed
`detail
`in _Figures
`2,
`the selected
`material of
`the
`subsequently.)
`If
`
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`013
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`-10-
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`therein may be
`substrate or any devices
`second
`the
`subsequent
`by
`the etchant used
`in
`attacked
`it must be
`temporarily protected during
`etching,
`etching by a base in the manner to be described.
`The
`second substrate 58
`is attached by any
`appropriate
`technique, which
`must be chosen so that
`the
`attachment
`procedure
`does
`not damage
`the
`pre-existing structure
`such
`as
`the microelectronic
`circuit
`element 50.
`In one approach that achieves a
`attachment,
`permanent
`the
`second substrate 58
`is
`attached
`of epoxy 60 placed between the
`by
`a
`layer
`pre-existing structure and
`the second substrate 58,
`and
`thereafter degassed
`in a vacuum and cured. The
`epoxy
`is
`resistant to chemical attack in the etchant
`used
`in
`a
`subsequent step.
`To attain precise
`alignment,
`tooling may be used
`to position
`the
`structures
`to be
`joined.
`Interconnects
`such as
`indium bumps
`can be placed on
`the front-side
`61
`electrical
`contacts
`54
`to
`achieve
`electrical
`interconnection between
`the
`microelectronic circuit
`element 50 and any microelectronic circuit element in
`the second substrate 58.
`42 of the first substrate
`The etchable
`layer
`is, removed by an
`appropriate technique, preferably
`40
`etching, numeral
`26.
`To protect the structure
`by
`against, etch attack,
`it may be temporarily attached
`a piece of aluminum oxide,
`a base
`62
`such as
`to
`layer of wax 64. After
`preferably sapphire, by
`a
`etching,
`is melted and
`the etched
`the
`wax
`64
`structure removed from the base 62.
`The etchant
`is chosen so that it attacks the
`etchable
`layer
`42
`relatively
`rapidly, but
`the
`etch-stop
`layer 44
`relatively slowly or not at all.
`The
`terms ."etchable"
`and
`"etch-stop"
`indicate
`a
`relative
`relation
`to each other
`in
`a particular
`etchant, as used herein. They are relative to each
`other
`and
`to
`the selected etchant.
`Thus,
`the
`
`5
`
`10
`
`.15
`
`20
`
`25
`
`30
`
`35
`
`014
`
`

`
`-11-
`
`5
`
`preferred bulk silicon etchable layer 42 is attacked
`and etched
`away by a 5-10 molar potassium hydroxide
`(KOH)
`or
`sodium hydroxide
`(NaOH)
`solution at
`a
`temperature of bOG.
`The etch-stop silicon dioxide
`layer 44
`is attacked by the potassium hydroxide or
`sodium hydroxide solution at a much lower rate than
`layer 42.
`Waxes
`such as glycol
`the
`etchable
`softened by the potassium hydroxide or
`phthalate are
`sodium hydroxide solution only very slowly, and can
`10 be used
`to bond
`the base 62 to the structure for
`protection. When the etchable layer 42 is exposed to
`the etchant, bubbles evolve as the silicon reacts and
`etches
`away.
`The
`end point of the bulk etching is
`determined by the end of the bubble evolution and the
`15 appearance of
`the glassy silicon dioxide etch-stop
`layer 44.
`the completion of etching a back face 66 of
`At
`the etch-stop layer 44 is exposed, as depicted in the
`step 26.
`The base 62 may be removed by melting the
`20 wax 64, or
`it may be
`left as
`a
`.convenience in
`subsequent operations. Eventually, however, the base
`62 is removed at some point in the process.
`formed
`Back-side electrical connections are
`through
`the etch-stop layer 44 (for direct back-side
`interconnects 56') and through the etch stop layer 44
`and
`the wafer layer 46 to the microelectronic circuit
`element 50
`(for
`indirect
`front-side
`interconnects
`56),
`as
`shown
`at numeral 28.
`To
`form
`such
`connections,
`the etch-stop
`layer 44 is patterned by
`30 well-known
`patterning
`techniques
`to
`precisely
`identify
`the
`location to be penetrated. Material is
`removed
`from
`these
`locations of the etch-stop layer
`44 by any appropriate method. As discussed earlier,
`the
`term "etch-stop'' is.used relative to the etchant
`35 used
`to
`remove
`the etchable
`layer 42. There are
`other etches
`that can be used
`to etch openings
`through
`the etch-stop
`layer 44.
`In the case of the
`
`25
`
`•
`
`i
`
`l
`I,
`\
`"
`
`015
`
`

`
`-12-
`
`5
`
`10
`
`20
`
`a
`layer 44,
`silicon dioxide etch-stop
`preferred
`hydrofluoric acid-based etchant such as a mixture of
`hydrofluoric acid and ammonium fluoride is used after
`patterning
`to etch openings 68 and 68' through the
`etch-stop
`layer 44.
`Dry etching techniques such as
`plasma etching can also be used.
`The via 68 extends through the etch-stop layer
`and
`the wafer
`layer 46
`to the microelectronic
`44
`circuit element 50. When filled with an electrical
`conductor
`such as
`a metal, it provides an indirect
`back-side
`electrical
`connection
`to
`the
`microelectronic circuit element 50. Alternatively,
`the via may be extended through the etch-stop layer
`44
`to
`(but not through) the wafer layer 46, as shown
`68'.
`This via 68', when filled with an
`15 at numeral
`conductor,
`provides
`the direct back-side
`electrical
`electrical
`56' to the wafer layer 46.
`In
`connection
`some electronic devices,
`it is desirable to apply a
`voltage
`to
`the either or both sides of the active
`element
`for biasing purposes. The direct back-side
`electrical connection 56' permits biasing of one side
`of
`the active element, while the indirect front-side
`electrical connection 56 permits biasing of the other
`side of the active element.
`layer 70 may be
`An
`electrical
`conductor
`deposited overlying
`the etch-stop
`layer 44 and the
`back-side electrical connections 56
`and 56',
`and
`patterned.
`The electrical conductor material
`is
`preferably
`a metal
`such as
`aluminum.
`Electrical
`interconnection
`to
`the
`back-side
`electrical
`connections 56 and 56' is thereby accomplished.
`This
`final structure 71, with front and back
`side electrical connections, is useful by itself, or
`it may be used
`in many other contexts.
`In one
`35 possible application, anoth~r microelectronic device
`72
`is
`integrally
`joined
`to
`the back side of the
`structure 71.
`The device 72 is aligned so that it
`
`25
`
`30
`
`-·· f.
`I
`
`016
`
`

`
`- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - · ·
`
`.... · - - - - - - - - - - - - -
`
`-13-
`
`5
`
`the microelectronic
`to
`electrical contacts
`makes
`circuit element
`50
`through the electrical conductor
`layer 70.
`The
`three-dimensional structure 71, 72
`made by
`this approach is depicted in greater detail
`in Figure 2.
`the structure 71 is
`to Figure 2,
`Referring
`prepared as discussed
`in
`relation to the method of
`Figure 1.
`It
`includes the microelectronic circuit
`element 50, back-side electronic connections 56 and
`56',
`and
`indium bumps 61, as well as the wafer layer
`46,
`the etch-stop
`layer 44,
`and
`the electrically
`conducting
`layer 70.
`The
`second substrate 58,
`previously
`shown
`in Figure 1 without its detailed
`structure,
`includes a microelectronic circuit element
`50a
`fabricated
`in
`a wafer layer 46a, which in turn
`overlies
`an
`etch-stop
`layer
`44a.
`Back-side
`electrical
`connections 56a and 56'a connect with an
`electrically
`conducting
`layer 70a. The layer 70a in
`turn
`is
`in
`electrical
`communication with
`the
`20 microelectronic device 50
`through
`the indium bumps
`61.
`
`10
`
`15
`
`shown in Figure 1 without its
`The device 72,
`includes
`a microelectronic
`detailed
`structure,
`circuit element 50b fabricated in a wafer layer 46b,
`25 which overlies an etch-stop layer 44b. As depicted
`in Figure 2,
`an etchable layer 42b of the device 72
`is still present
`to provide strength t~ the stack.
`The device 72
`is
`joined to the device structure 71
`with an epoxy layer 60b.
`three
`thus has
`The structure of Figure 2
`microelectronic circuit elements 50, 50a,
`and 50b
`interconnected
`in
`a
`·three-dimensional array.
`The
`process of building up a three-dimensional stack of
`devices
`can
`continue
`indefinitely
`by
`adding
`additional microelectronic circuit elements "below"
`the device 72.
`To
`further process the device of
`Figure 2, process steps 26, and 28 of Figure 1 are
`
`35
`
`30
`
`.,
`'
`
`017
`
`

`
`i ,
`'
`
`-14-
`
`30
`
`35
`
`5
`
`20
`
`25
`
`15
`
`the device 72. The etchable layer 42b
`for
`repeated
`and
`indirect
`back-side electrical
`is
`removed,
`56b
`(and optionally direct back-side
`connections
`electrical connections) can be added in the manner
`discussed earlier.
`An electrical conduction layer
`70b is deposited and patterned.
`repeating
`results of
`Figure 3 depicts
`the
`process
`steps 26 and 28. At this point, yet another
`microelectronic device structure could be affixed
`10 with
`an
`epoxy
`layer below
`the device 72,
`and
`electrically
`interconnected
`through
`the back-side
`electrical connections.
`Rather
`than depict such a
`structure, Figure 3
`shows
`the manner of external
`electrical
`connections.
`To achieve an external
`electrical
`interconnect,
`a lead 74 is wire bonded to
`a pad region of the electrical conduction layer 70b.
`Thus,
`the structures depicted in Figures 2 and
`provide
`integrated
`three-dimensional
`3
`microelectronic
`device
`structures
`made
`from
`two-dimensional circuit elements, with internal ·and
`external
`electrical·
`interconnections.
`These
`structures are normally packaged with conventional
`procedures.
`Figure 4 depicts another use of the device
`structures
`prepared
`according
`to
`the
`present
`invention,
`as
`a
`"smart board" upon which other
`microelectronic
`components
`can
`be
`attached by
`wire-bonding
`techniques.
`The microelectronic device
`71,
`shown in Figure 4 in the form presented in Figure
`1
`and
`inverted
`from the orientation of Figure 1, is
`prepared
`at
`any
`level
`of
`complexity
`of
`three-dimensional structure as discussed in relation
`to Figures 2
`and 3. A separately fabricated device
`80
`is attached
`to
`the back
`face 66 with an epoxy
`layer 82.
`Electrical
`interconnect pads 84 on the
`device 80 are connected
`to pad
`locations of the
`patterned electrically conducting
`layer 70 on the
`
`018
`
`

`
`-15-
`
`5
`
`10
`
`by
`External
`leads 86.
`wire-bonded
`71
`device
`achieved through wire-bonded leads 88
`connections are
`electrically conducting layer 70.
`to the patterned
`approach and with
`the structure of
`By
`this
`device 71 fabricated according to the
`Figure 4,
`the
`approach of Figure 1 can be used as a "smart boar.d"
`containing microelectronic
`functions, for attachment
`of
`other
`devices
`80.
`The device 80
`is not
`electrically connected
`to
`the device 71 by in~ium
`bumps or similar technique, but instead is connected
`by wire bonding or a similar approach .
`The present
`invention
`thus provides a highly
`flexible
`microelectronic
`fabrication
`technique.
`Three-dimensional,
`multilayer
`structures
`with
`15 arbitrarily many
`layers of microelectronic circuit
`elements can be
`fabricated with external connection
`points.
`These structures can be used as-is, or as
`the
`"smart
`board"
`for attachment of yet other
`devices.
`the
`embodiment of
`a
`Although
`pa~ticular
`invent ion has been described in detail for purposes
`of
`illustration, various modifications may be made
`without departing
`from
`the spirit and scope of the
`invention.
`Accordingly,
`the invention is not to be
`limited except as by the appended claims.
`
`20
`
`25
`
`I
`l
`
`I ....
`·\: \
`
`•
`I
`·, ,,/
`
`019
`
`

`
`-16-
`
`CLAIMS
`
`What is claimed is:
`
`A method of fabr
`1.
`device, comprising the steps
`furnishing
`a
`fir
`etchable
`layer, an
`etchable
`layer,
`and
`layer;
`
`a
`
`a microelectronic
`
`having an
`substrate
`layer overlying
`the
`top
`fer overlying the etch-stop
`
`a
`forming
`the wafer of the .first
`attaching
`the·
`a second substrate: a
`etching away
`substrate down to t e
`
`lectronic circuit element in
`ubstrate;
`wafer of the first substrate to
`d
`
`etchable layer of the first
`etch-stop layer.
`
`5
`
`10
`
`The method of claim 1, further including
`2.
`an additional step, after the step of etching, of
`patterning the etch-stop layer.
`
`The method of claim 2, further including
`3.
`an additional step, after the step of patterning, of
`forming
`an
`electrical
`connection .to
`the
`microelectronic circuit element through the patterned
`etch-stop layer and through the wafer.
`
`5
`
`The method of claim _2' , further including
`4.
`an additional step, after the step of patterning, of
`forming an electrical connection to the wafer
`through the patterned etch-stop layer.
`
`/
`
`5.
`etchable
`silicon
`silicon.
`
`the
`The method of claim 1, wherein
`is silicon,
`the
`etch-stop layer is
`layer
`is single-crystal
`and
`the wafer
`diox-ide.
`
`020
`
`

`
`-------------------·-----
`
`5
`
`5
`
`5
`
`5
`
`6.
`substrate
`elemen t .
`
`The method of claim 1, wherein the second
`contains
`a
`second microelectronic circuit
`
`The method of claim 6, wherein the step of
`7.
`attaching i ncludes the step of
`the
`from
`contact
`making
`an
`electrical
`microel ect ronic circuit element on the wafer of the
`first substrate to the second microelectronic circuit
`element on the second substrate.
`
`· The me t hod of claim 1, wherein the step of
`8.
`attaching includes the steps of
`placing a
`layer of epoxy between the second
`substrate
`and
`the wafer portion of
`the first
`s ubstra te , and
`degassing and curing the epoxy.
`
`The method of claim 1, further including
`9.
`addi tiona! step. after the step of attaching and
`a·n
`before the ·step of. etching, of
`to an etching
`fixing
`the
`second substrate
`support that is resistant to attack by an etchant.
`
`The method of claim 1, wherein the step
`10.
`of etching includes t he step of
`liquid
`a
`t