(19) Japanese Patent Office (JP)
`(12) Kokai Unexamined Patent Application Bulletin (A)
`(11) Laid Open Patent Application No.
`3-108776
`
`(43) Publication Date
`May 8, 1991
`
`Number of Claims
`
`6
`
`Number of Pages
`35
`
`
`Examination Request
`not yet made
`
`
`
`
`
` H
`
` 01 L 27/14
`
`type
`
`semiconductor device
`
`SPECIFICATION
`1. Title of the Invention
`Multi-Layer Semiconductor Device and Method of
`Manufacturing the Same
`2. Claims
`(1) A multi-layer
`comprising:
`a substrate having a main surface;
`having
`layer
`a
`first
`semiconductor element
`semiconductor elements formed on the main surface of
`the substrate;
`an insulating film layer formed on the semiconductor
`element layer; and
`layer having
`a second semiconductor element
`semiconductor elements formed in the vertically opposite
`direction to the semiconductor elements of the first
`semiconductor element layer, on the insulating layer.
`(2) A multi-layer
`type
`semiconductor device
`comprising:
`a transparent substrate;
`transparent
`the
`a photosensor
`layer,
`formed on
`substrate, and having photosensor elements
`for
`receiving light passing through the transparent substrate
`and converting it into an electric signal;
`a circuit layer, formed on the photosensor layer, and
`having a processing circuit, connected
`to
`the
`photosensor layer via through holes, for processing the
`electric signal received from the photosensor layer;
`
`semiconductor device
`
`an insulating film layer formed on the circuit layer; and
`a display element layer having display elements
`formed
`in
`the vertically opposite direction
`to
`the
`photosensor elements of the photosensor layer, formed
`on the insulating film layer, and through-hole-connected
`to the circuit layer, for displaying the results of the
`processing of the circuit layer.
`(3) A multi-layer
`type
`comprising:
`a transparent substrate;
`a display element layer having display elements
`formed on the transparent substrate such that the
`display matter
`is visible
`through
`the
`transparent
`substrate;
`a circuit layer, formed on the display element layer,
`and
`having
`a
`processing
`circuit, which
`is
`through-hole-connected to the display element layer, for
`processing display matter to be displayed by the display
`elements;
`an insulating film layer formed on the circuit layer; and
`a sensor layer having a face that contacts the
`insulating film layer and another face that is exposed to
`the
`exterior,
`and
`having
`sensor
`elements,
`through-hole-connected
`to
`the circuit
`layer,
`for
`converting an information variable from the exterior to an
`electrical signal.
`
`Translation by Patent Translations Inc. 206-357-8508 mail@PatentTranslations.com
`
`(51)
`
`
`Int. Cl.5
`H 01 L 31/14
`G 02 F 1/136
`H 01 L 27/00
` 27/14
`H 04 N 5/335
`
`Identification Code
`
`A
`
`500
`301 A
`
`U
`
`(54)
`
`Title of the Invention:
`
`(21) Application No.:
`(22) Application Date:
`Inventor:
`(72)
`
`(71) Applicant:
`
`(74) Agent:
`
`
`
`
`
`
`
`Internal File No.
`7454-5F
`9018-2H
`7514-5F
`
`8838-5C
`8122-5F
`
`Multi-Layer Semiconductor Device and Method of
`Manufacturing the Same
`1-247156
`September 22, 1989
`KUSUNOKI, Shigeru
`Mitsubishi Electric Corporation, LSI Laboratory
`4-1 Mizuhara, Itami-shi, Hyogo-ken
`Mitsubishi Electric Corporation
`2-2-3 Marunouchi, Chiyoda-ku, Tokyo-to
`Patent Attorney, OIWA, Masuo
`And 2 other people
`
`001
`
`Petitioner Samsung - SAM1008
`
`

`
`JP-03-108776-A Page (2)
`
`first semiconductor layer;
`a step of forming a second electrical circuit with the
`first semiconductor layer on the insulating layer of the
`second substrate as a base, and forming second pads
`electrically connected to the second electrical circuit.
`3. Detailed Description of the Invention
`[Field of Use in Industry]
`type
`to multi-layer
`This
`invention
`relates
`semiconductor devices and to a manufacturing method
`for the same, and more particularly to multi-layer type
`semiconductor devices having semiconductor element
`layers stacked in mutually vertically opposite directions.
`[Prior1 Art]
`An ordinary integrated circuit is formed on a surface of
`a wafer and has, so to speak, a two-dimensional
`structure. As opposed to this, an integrated circuit in
`which semiconductor layers, on which semiconductor
`elements are formed, are stacked in multiple layers is
`called a three-dimensional integrated circuit. Because of
`the multi-layer
`structure,
`the
`three-dimensional
`integrated circuit has the advantage of realizing greatly
`improved integration and functions.
`Generally, in three-dimensional integrated circuits,
`semiconductor layers and insulating layers are stacked
`alternately, with each semiconductor layer having active
`elements formed therein. With the integrated circuit
`having elements formed in the semiconductor layers
`formed on the insulating layers in this manner, the
`elements have little excess electrical capacity, and
`hence there is a further advantage of the elements
`operating at high speeds.
`layers,
`The
`technique of
`forming semiconductor
`particularly silicon layers, on insulating layers will be
`described next.
`The technique of forming silicon layers on insulating
`layers, or the technique of producing a structure in which
`silicon layers have been formed on insulating layers is
`known as the SOI (Silicon On Insulator)
`
`
`(4) A multi-layer
`comprising:
`a substrate having through holes wherein conductors
`are formed in the through holes;
`a first circuit layer formed on the substrate and having
`an electrical circuit electrically connected
`to
`the
`conductors;
`an insulating film layer formed on the first circuit layer;
`a second circuit layer having an electrical circuit
`formed on the insulating film layer in the vertically
`opposite direction to the electrical circuit of the first
`circuit layer, and through-hole-connected to the electrical
`circuit of the first circuit layer; and
`layer, and
`film
`pads,
`formed on
`the
`insulating
`electrically connected to the electrical circuit of the
`second circuit layer.
`(5) A method of manufacturing a multi-layer type
`semiconductor device comprising:
`a step of bonding a first substrate, having a first
`semiconductor layer on a surface thereof, and a second
`substrate, having an insulating layer on a surface thereof
`and a second semiconductor layer below the insulating
`layer, with
`the
`insulating
`layer and
`the
`first
`semiconductor layer facing each other;
`a step of thinning the first substrate to expose the first
`semiconductor layer;
`a step of forming a first semiconductor element with
`the first semiconductor layer as a base, with the first
`semiconductor layer directed upward;
`a step of forming an insulating film on the first
`semiconductor element;
`a step of bonding a third substrate on the insulating
`film;
`a step of thinning the second substrate to expose the
`second semiconductor layer; and
`a step of forming a second semiconductor element,
`with the second semiconductor layer as a base, with the
`second semiconductor layer directed upward.
`(6) A method of manufacturing a multi-layer type
`semiconductor device comprising:
`a step of forming through holes through a first
`substrate;
`a step of filling the through holes in the first substrate
`with conductors;
`a step of forming a first semiconductor layer on a main
`surface of a second substrate having a main surface,
`forming an insulating layer on the first semiconductor
`layer, and forming and a second semiconductor layer on
`the insulating layer ;
`a step of forming a first electrical circuit with the
`second semiconductor layer on the insulating layer of
`the second substrate as a base, and forming first pads
`electrically connected to the first electrical circuit;
`a step of bonding the first substrate and the second
`substrate so as to electrically connect the conductors of
`the first substrate and the first pads of the second
`substrate;
`a step of thinning the second substrate to expose the
`
`type
`
`semiconductor device
`
`
`1 "Background" has been crossed out and replaced by "Prior"
`in a handwritten annotation. -- trans.
`Translation by Patent Translations Inc. 206-357-8508 mail@PatentTranslations.com
`
`002
`
`

`
`JP-03-108776-A Page (3)
`
`having approximately the same thickness as the first
`silicon wafer 101a is such that, formed on a surface
`region thereof, there is a boron-injected layer 103a with
`boron injected at a high concentration, on the order of 1
`x 1020/cm3, and a low concentration epitaxial layer 104a
`having a thickness of about 5,000 Å. The epitaxial layer
`104a is produced by causing silicon crystals to grow
`epitaxially on the single-crystal substrate 101b.
`Referring to FIG. 24B, the two wafers 101a and 101b
`are overlaid with the insulating layer 102 and epitaxial
`layer 104a facing each other, and are heat-treated in an
`atmosphere of approximately 800(cid:113)C. This heat treatment
`is called annealing. The annealing
`induces an
`interatomic junction at the joined faces, which bonds the
`two wafers 101a and 101b. Next, an upper surface of
`one of the wafers 101b is abraded until the thickness
`reaches 100 µm, and next the wafer 101b is etched until
`the thickness reaches 10 um.
`Next, the wafer 101b is etched with an aqueous
`solution of ethylenediamine and pyrocatechol. The
`etching rate with this aqueous solution is 1 µm/minute for
`semiconductor regions having a low concentration of
`boron, but 20 Å/minute for the regions of high boron
`concentration, and thus the etching action stops at the
`high concentration boron-injected layer 103a. Thus, as
`shown in FIG. 24C, the wafer 101b is removed, leaving
`the high concentration boron-injected layer 103a and
`epitaxial
`layer 104a. Next,
`to form semiconductor
`elements, the boron-injected layer 103a
`
`
`technique. A silicon layer formed on an insulating layer is
`called an SOI layer, and a structure having silicon layers
`formed on insulating layers an SOI structure.
`Methods are known which utilize epitaxial growth as
`SOI techniques. In these methods, liquid phase epitaxy
`methods, such as the melting/recrystallization method, in
`which a polycrystalline or amorphous semiconductor
`layer formed on an insulating layer is exposed to and
`melted by energetic light such as a laser beam, an
`electron beam or the like, and is thereafter allowed to
`solidify, the solid phase epitaxy method, in which an
`amorphous semiconductor layer is caused to grow in a
`solid phase, and vapor phase epitaxy methods such as
`graphoepitaxy, bridging epitaxy or the like are used.
`However, since these methods cause silicon crystals to
`grow on an insulating layer, there were problems in
`terms of it being more difficult to obtain a single-crystal
`layer over a large area, and problems in terms of it being
`more difficult to control film thickness, than in the case of
`causing silicon crystals
`to grow epitaxially on a
`single-crystal layer.
`Implanted
`(Separation by
`Furthermore, SIMOX
`Oxygen) is known as a technique for producing the SOI
`structure. SIMOX is a method of injecting ions such as
`oxygen
`ions,
`in high
`concentrations,
`into a
`semiconductor layer to form a buried insulating layer so
`as to obtain a structure having mutually separated
`semiconductor layers. With this method, however, it is
`difficult to obtain a multi-layer structure, and therefore
`this method is difficult to apply to three-dimensional
`integrated circuits.
`is known as
`Further, a wafer bonding method
`technique for producing a SOI structure. In the wafer
`bonding method, a single-crystal wafer or a wafer having
`a single-crystal layer is overlaid on a wafer having an
`insulating layer formed on the surface, and the two
`wafers are heat treated (annealed) in an atmosphere of
`600(cid:113)C to 1000(cid:113)C, whereby an interatomic junction is
`produced at the joined faces, bonding the wafers
`together, and the upper wafer is thinned, whereby the
`semiconductor layer is formed on the insulating layer.
`The semiconductor layer produced on the insulating
`layer in this manner is originally formed by epitaxial
`growth on a single-crystal silicon substrate, and thus has
`crystalline properties and a uniform film thickness, and is
`therefore suitable for manufacture of a three-dimensional
`integrated circuit.
`A multi-layer type semiconductor device manufactured
`using such a wafer bonding method, which serves as
`background for this invention will be described next.
`FIGS. 24A through 24K are sectional views describing
`a process of manufacturing
`the multi-layer
`type
`semiconductor device serving as background for this
`invention.
`Referring to FIG. 24A, a first silicon wafer 101a having
`a thickness of 500 to 600 µm is such that an insulating
`layer 102 is formed 1000 to 10,000 Å thick on a surface
`region thereof. Meanwhile, a second silicon wafer 101b
`Translation by Patent Translations Inc. 206-357-8508 mail@PatentTranslations.com
`
`003
`
`

`
`JP-03-108776-A Page (4)
`
`insulating layer 102 therebetween, and a second active
`layer L2 is formed on the first active layer L1 with the
`insulating layer 112 therebetween. The transistor of the
`first active layer L1 and the transistor of the second
`active layer L2 are electrically connected by conductors
`provided in through holes 114, as necessary.
`device
`The multi-layer
`type
`semiconductor
`manufactured by way of the steps described above
`employs a refractory metal wiring layer, instead of
`aluminum, for the metal wiring layer of the first active
`layer. This is because the wiring layer is subjected to
`high temperatures when the two wafers are bonded by
`annealing as shown in FIG. 24I. Thus, if a third active
`layer is formed on the second active layer, rather than an
`aluminum wiring layer, a refractory metal wiring layer is
`used.
`In the multi-layer type semiconductor device described
`above, the active layers are stacked in one direction2.
`Thus, if a large number of layers are stacked, in
`conjunction with this stacking direction being a fixed
`direction, distortion becomes pronounced, giving rise to
`the problems of fluctuating threshold voltages and
`increasing leakage currents.
`Furthermore, since the active layers are stacked on
`only one surface of the substrate, the active layers close
`to the substrate are heated more times than the active
`layers or layers farther away from the substrate and,
`therefore,
`
`
`is etched away, next the exposed surface is oxidized,
`and next the oxide film is etched away. Consequently, a
`thin SOI layer 104a having a thickness on the order of
`approximately 1000 Å is produced.
`Next, referring to FIG. 24D, field oxide layers 105a are
`formed by LOCOS (Local Oxidation of Silicon) in regions
`of the SOI layer 104a which are to serve as element
`isolation regions.
`Next, referring to FIG. 24E, a gate insulator film 107a
`is formed by oxidation of the SOI layer 104, and a
`polysilicon layer is formed on the gate insulator film 107a.
`This polysilicon layer is patterned into a shape of a gate
`electrode 106a. Next, impurities are ion implanted, with
`the gate electrode 106a as a mask, to form source and
`drain regions 108a.
`Next, referring to FIG. 24F, an interlayer insulating film
`109a is formed over the entire surface, and contact
`holes 110 are formed in the interlayer insulating film
`109a.
`Next, referring to FIG. 24G, a refractory metal wiring
`layer 111 is formed electrically connected to the source
`and drain regions 108a and extending on the interlayer
`insulating film 109a. The gate electrode 106a, the gate
`insulator film 107a and the source and drain regions
`108a constitute a transistor. Next, an insulating layer 112
`is formed over the interlayer insulating film 109a and the
`refractory metal wiring layer 111.
`Next, referring to FIG. 24H, the insulating layer 112 is
`flattened for the purpose of lamination. Thereafter the
`flattened insulating layer 112 is overlaid by a third silicon
`wafer 101c having a high concentration boron-injected
`layer 103b and an epitaxial layer 104b, in the same
`manner as the second silicon wafer 101b. The two
`wafers are annealed in an atmosphere of approximately
`the wafers are bonded, with the
`800(cid:113)C, whereby
`surfaces of the insulating layer 112 and the epitaxial
`layer 104b as the joined faces, as shown in FIG. 24I.
`Next, as described above, the wafer 101c is thinned by
`abrasion and etching with a mixed solution of
`hydrofluoric acid and nitric acid, and further etched with
`an
`aqueous
`solution
`of
`ethylenediamine and
`pyrocatechol, so as to leave the high concentration
`boron-injected layer 103b and epitaxial layer 104b on the
`wafer 101c, as shown in FIG. 24J. The epitaxial layer
`104b of the third silicon wafer 101c is used as a second
`SOI layer. Next, to form semiconductor elements, the
`high concentration boron-injected layer 103b is etched
`away.
`Next, referring to FIG. 24K, field oxide layers 105b, a
`gate insulator film 107b, a gate electrode 106b, source
`and drain regions 108b, an interlayer insulating film 109b,
`and a wiring layer 113 made from aluminum or an
`aluminum alloy are formed with the second SOI layer
`104b as a base, in the same manner as described for
`FIGS. 24D and 24E. The gate electrode 106b, gate
`insulator film 107b and source and drain regions 108b
`
`constitute a transistor. In this way, a first active layer L1
`2 See Amendment (1) in the Amendment to Proceedings of
`is formed on the semiconductor substrate 101a with the
`December 12, 1990. -- trans.
`Translation by Patent Translations Inc. 206-357-8508 mail@PatentTranslations.com
`
`004
`
`

`
`JP-03-108776-A Page (5)
`
`substrate, this method cannot be applied to the above
`system which requires a high degree of integration. Thus,
`it
`is very difficult
`to apply a multi-layer
`type
`semiconductor device having SOI layers stacked only on
`one surface of the substrate to an image processing
`system having a light-receiving unit and a display unit
`formed on one chip. Generally, therefore, as shown in
`FIG. 25, a light-receiving unit 20 and a display unit 30
`are
`fabricated
`separately and
`are electrically
`interconnected through leads 15.
`In FIG. 25, the light-receiving unit 20 includes a
`substrate 201, an insulating layer 202 formed on the
`substrate 201
`for
`forming an SOI
`layer, a
`three-dimensional integrated circuit 215 formed on the
`insulating layer 202 and including a processing circuit for
`processing an electric signal based on the light received
`by the light-receiving unit 20, a memory circuit for storing
`data for comparison with the electric signal and the like,
`a photoelectric sensor 216 wherein photodiodes are
`arranged in matrix, and an output circuit 217 having
`output pads. The three-dimensional integrated circuit
`215 includes active layers L1, L2 . . . Ln in which are
`formed, in individual layers or in units of multiple layers,
`circuits having independent functions, wherein signal
`transfer between the layers is performed via through
`holes. The display unit 30 includes a substrate 301, a
`circuit 318 including electrodes for driving a liquid crystal
`display, an input circuit 317 having input pads, a liquid
`crystal 319, a resin member 320 for sealing the liquid
`crystal, and a window 321 for the display unit 30.
`In the image processing system shown in FIG. 25, the
`photoelectric sensor 216 of the light-receiving unit 20
`receives light in the direction of arrow A from a
`photographic subject, and converts it into an electric
`signal. This electric signal is electrically processed by
`the three-dimensional integrated circuit 215 and, for
`example, contour extraction, enhancement, pattern
`recognition and the like are performed. This electric
`signal is transferred from the output pads 217 of an
`output circuit such as a shift register, via the leads 15, to
`the input pads 317 of the display unit 30. In the display
`unit 30,
`
`
`requires higher heat-resistance.
`Next, an image processing system employing the
`multi-layer type semiconductor device manufactured by
`way of the steps discussed above will be described. This
`image processing system includes a light-receiving unit
`for receiving light from a photographic subject, and a
`display unit for displaying a received optical signal as an
`image.
`In such an image processing system, generally, the
`light-receiving unit and display unit are formed separately.
`This is for the following reason. That is to say, it is
`necessary for light-receiving elements to receive light
`from outside, and it is necessary for display elements to
`be visible from outside. Both elements must face
`outward or be formed close to this. Meanwhile, with the
`multi-layer semiconductor device 10 that serves as
`background for this invention, since this is formed only
`on one face of the substrate, if the display elements and
`light-receiving elements are formed on the substrate, the
`display elements are formed closest to the substrate and
`the light-receiving elements are formed furthest from the
`substrate, or conversely, the light-receiving elements are
`formed closest to the substrate and the display elements
`are formed furthest from the substrate. However, since
`the active layers are stacked on one surface of the
`substrate, the elements formed closer to the substrate
`will be heated more times than the elements formed
`farther away from the substrate, and thus, a material
`having poor thermal resistance3 cannot be used for the
`layer close to the substrate.
`If, for example, a sensor made from an amorphous
`material were formed in the layer close to the substrate,
`this sensor would become
`inoperable since
`the
`amorphous material would become crystallized as a
`result of the long heat treatment. Furthermore, if a
`sensor comprising a pn junction were formed in the layer
`close to the substrate, the position of junction in the pn
`junction would shift or the junction would be buried in4
`semiconductor layer as a result of the long heat
`treatment,
`thereby
`lowering
`the
`light absorption
`efficiency of the sensor. Further, for example, if a liquid
`crystal display was formed near the substrate, the
`characteristics would be inferior due to the heat5.
`In order to avoid the problems described above, a
`method is conceivable wherein, for example, on the
`opposite face of the substrate on which an active layer
`including display elements is stacked, again for example,
`an active layer including sensor elements is formed.
`However, through holes have to be provided in the thick
`substrate in order to electrically connect this active layer
`and an active layer on the opposite side of the substrate.
`Since it is difficult to form many through holes in the
`
`3 See Amendment (2) in the Amendment to Proceedings of
`December 12, 1990. -- trans.
`4 See Amendment (3) in the Amendment to Proceedings of
`December 12, 1990. -- trans.
`5 See Amendment (4) in the Amendment to Proceedings of
`December 12, 1990. -- trans.
`Translation by Patent Translations Inc. 206-357-8508 mail@PatentTranslations.com
`
`005
`
`

`
`JP-03-108776-A Page (6)
`
`system having a sensor function and a display function
`is produced.
`The foregoing image processing systems or sensing
`systems may be broadly classified into two types based
`on differences in display mode.
`in FIG. 29, has a
`The
`first
`type, as shown
`light-receiving unit 20 and a display unit 30 formed from
`optically transparent materials, and a transmitted image
`of an object 25 that is to be sensed and an image
`expressing
`the
`results of sensing-processing are
`[arranged] to as to be seen superimposed by the naked
`eye 35. Here, the transmitted image is an image of the
`object 25 which can be seen via the light-receiving unit
`20 and display unit 30, and the image expressing the
`results of processing is an image displayed on a liquid
`crystal 319. With this type of system, a precise alignment
`of the light-receiving unit 20 and display unit 30 is
`necessary for the transmitted image and the image
`expressing the results of processing to be seen perfectly
`superimposed.
`The second type is made such that, as shown in FIGS.
`30 and 31, only the matter displayed on the display unit
`30 or 50 can be seen by the naked eye 35. In this type of
`system, a transmitted image of the object 25 cannot be
`seen.
`FIG. 30 shows [a system] employing the liquid crystal
`319 as the display means, while FIG. 31 shows [a
`system] employing the light emitting element 522.
`Furthermore, particularly where the signal processing
`functions and the like of the three-dimensional integrated
`circuit 215, 415 are disturbed by external light or light
`
`
`the liquid crystal 319 is driven on the basis of the signal
`that was transferred thereto, so as to display graphics
`such as contour lines. The displayed graphics can be
`seen through the window 321 in the direction of arrow
`B.
`Next, a method of manufacturing the light-receiving
`unit and display unit of the image processing system
`shown in FIG. 25 will be described in general terms.
`Referring to FIG. 26A, the light-receiving unit is such
`that the three-dimensional integrated circuit 215, serving
`for image processing, is made on the insulating layer
`202 on the silicon substrate 201 in the same way as
`described with reference to FIGS. 24A through 24K.
`Referring next to FIG. 26B, the photoelectric sensor 216
`and the output circuit 217 having the output pads are
`made on the three-dimensional integrated circuit 215.
`Meanwhile, referring to FIGS. 26C and 26D, the
`switching circuit 318 having the electrodes for driving the
`liquid crystal display and the input circuit 317 having the
`input pads are made on the substrate 301; next, the
`resin member 320 for sealing the liquid crystal is
`attached, and the transparent window 321 is attached to
`the resin member 320. Next, pressure in a gap between
`the switching circuit 318 and window 321 is reduced so
`as to introduce the liquid crystal 319 therein.
`Next, a sensing system to which foregoing multi-layer
`type semiconductor device described above having the
`three-dimensional integrated circuit will be described. In
`this sensing system, a sensor is provided at an input
`side for detecting light, pressure, temperature, radiation
`or the like, and light emitting elements such as light
`emitting diodes are provided at an output side for
`displaying sensing results. Such a sensing system is
`shown in FIG. 27.
`In FIG. 27, a sensor unit 40 includes a substrate 401,
`an insulating layer 402 formed on the substrate 401 for
`forming a sensor unit SOI element, a three-dimensional
`integrated circuit 415 comprising of a plurality of active
`layers L1, L2 . . . Ln and including a processing circuit
`for processing information detected by the sensor unit 40,
`and an output circuit 417 having output pads. An output
`unit 50 includes a substrate 501, display elements 522
`wherein red, green and blue light emitting diodes are
`arranged in matrix form, and an input circuit 517 having
`input pads.
`following
`the
`is made by
`This sensing system
`procedure. That is to say, as shown in FIG. 28A, the
`insulating layer 402 is formed on the substrate 401, and
`the three-dimensional integrated circuit 415 is formed on
`the insulating layer 402; next, as shown in FIG. 28B, the
`sensor 416 and the output circuit 417 having the output
`pads are formed.
`Meanwhile, as shown in FIGS. 28C and 28D, the
`display elements 522 which comprise light emitting
`diodes arranged in matrix form, and the input circuit 517
`having the input pads are formed on the substrate 501.
`Next, the output pads 417 and input pads 517 are
`connected via the leads 15. As a result, a sensing
`
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`
`006
`
`

`
`JP-03-108776-A Page (7)
`
`inevitably leads to an increased chip area.
`Next, the manner in which the input and output pads of
`the multi-layer type semiconductor device serving as
`background for this invention are arranged will be
`described.
`FIG. 34A is a plan view of the multi-layer type
`semiconductor device; FIG. 34B is a bottom view; and
`FIG. 34C is a sectional view along line C-C shown in FIG.
`34A. As shown in FIG. 34A through 34C, pads 617a and
`617b are provided only on one face of the multi-layer
`type semiconductor device 60, and no pads are provided
`on the other face.
`As shown in FIG. 34C, a first active layer 615a is
`formed on a substrate 601a, and a second active layer
`615b is formed on the first active layer 615a with an
`insulating layer 612 therebetween. In the first active
`layer 615a and second active layer 615b, electrical
`circuits are formed in keeping with the application of the
`semiconductor device 60. The electrical circuit in the first
`active layer 615a and the electrical circuit in the second
`active
`layer 615b are electrically connected by
`conductors provided in through holes 614b. A refractory
`metal wiring layer 611 leads out from the electrical circuit
`formed in the first active layer 615a. Pads 617a are
`formed on the insulating layer 612, and an aluminum
`wiring layer 613a that is connected to the pads 617a and
`the refractory metal wiring layer 611 are electrically
`connected via conductors provided in through holes
`614a. An aluminum wiring layer 613b leads out from the
`electrical circuit formed in the second active layer 615b,
`and the aluminum wiring layer 613b is electrically
`connected to pads 617b provided on the insulating layer
`612.
`Of the pads provided at the periphery of the electrical
`circuit 615b shown in FIG. 34A, the outer pads 617a
`
`
`from the object 25, a light shielding film 224, 424, which
`blocks external light, is inserted between the sensor 216,
`416 and the three-dimensional integrated circuit 215,
`415.
`The second type of system using a liquid crystal as the
`display means may be further classified
`into
`the
`reflection type and the transmission type. As shown in
`FIG. 30, in the reflection type a reflecting film is provided
`on a rear surface of the liquid crystal 319 and display is
`performed by reflected light resulting from the reflection
`of light from the front face of the liquid crystal 319. As
`shown in FIG. 32, in the transmission type, a light source
`323 is provided at the rear face of the liquid crystal 319
`and display is performed by transmitted light resulting
`from projecting light from the back of the liquid crystal
`319. Among these, the reflection type shown in FIG. 30
`employs a material having high reflectance, such as a
`silicon substrate, as the substrate 301a of the display
`unit 30.
`Furthermore, in the transmission type shown in FIG. 32,
`a transparent substrate is used as the substrate 301b of
`the display unit 30, and a light emitting body 323 is
`disposed at the exterior of the transparent substrate
`301b. However, in this case, if the substrate 201b and
`the insulating layer 202b of the light receiving unit are
`transparent, the light from the light emitting body 323 will
`enter the three-dimensional integrated circuit 215 having
`the signal processing
`functions and cause an
`disturbance to those functions. In order to avoid such
`disturbances, it is necessary to dispose a light shielding
`plate 324 between the light emitting body 323 and
`light-receiving unit 20, as shown in FIG. 33, or to employ
`an opaque material as the substrate 201c of the
`light-receiving unit 20.
`In the same matter as shown in FIGS. 30 and 31,
`where a disturbance
`to
`the
`functions of
`the
`three-dimensional integrated circuit 215 is caused by
`external light or light from the object 25, a light shielding
`film 224 or 424 must be provided between the sensor
`layer 216 and three-dimensional integrated circuit 215,
`as show in FIG. 33.
`liquid crystal
`Further, where
`the aforementioned
`display means is employed, there is a disadvantage of
`the system configuration being
`larger, since
`it
`is
`necessary to incorporate a light emitting body.
`The image processing system or sensing system
`employing the multi-layer type semiconductor device
`with active layers stacked only on one surface of a
`semiconductor substrate, as described above, has the
`sensor unit and display unit fabricated on separate chips,
`which results in the following disadvantage. That is to
`say,
`the sequential
`transmission system and
`the
`simultaneous parallel transmission system are available
`for trans