Paper No. ________
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`_______________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`_____________
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`Sony Corporation
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`Petitioner
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`v.
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`RAYTHEON COMPANY
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`(record) Patent Owner
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`Patent No. 5,591,678
`Issue Date: January 7, 1997
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`Title: Process of Manufacturing a Microelectronic Device using a Removable
`Support Substrate and Etch-Stop
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`DECLARATION OF DR. RICHARD A. BLANCHARD
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`Petitioner Samsung - SAM1002
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`I.
`I.
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`II.
`II.
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`TABLE OF CONTENTS
`TABLE OF CONTENTS
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`Engagement and compensation ....................................................................... 1
`Engagement and compensation ..................................................................... ..1
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`Summary of opinions ....................................................................................... 1
`Summary of opinions ..................................................................................... ..1
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`III. Qualifications ................................................................................................... 2
`III. Qualifications ................................................................................................. ..2
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`IV. My understanding of the relevant law ............................................................. 5
`IV. My understanding of the relevant law ........................................................... ..5
`A. Claim construction ......................................................................................... 5
`A. Claim construction ....................................................................................... ..5
`B. Anticipation .................................................................................................... 6
`B. Anticipation .................................................................................................. ..6
`C. Obviousness ................................................................................................... 7
`C. Obviousness ................................................................................................. ..7
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`Technical introduction ...................................................................................10
`V.
`Technical introduction ................................................................................. .. 10
`V.
`A. Background ..................................................................................................10
`A. Background ................................................................................................ .. 10
`B.
`’678 Patent Disclosure .................................................................................12
`B.
`’678 Patent Disclosure ............................................................................... ..12
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`VI. Level of ordinary skill in the art ....................................................................20
`VI.
`Level of ordinary skill in the art .................................................................. ..20
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`VII. Predictability of the art ..................................................................................22
`VII. Predictability of the art ................................................................................ ..22
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`VIII. Relevant time frame for determining obviousness ........................................22
`VIII. Relevant time frame for determining obviousness ...................................... ..22
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`IX. Overview of the claims ..................................................................................23
`IX. Overview of the claims ................................................................................ ..23
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`Construction of the claims .............................................................................23
`X.
`Construction of the claims ........................................................................... ..23
`X.
`A. Claims 1, 3, 6-7, 11, 13 and 15 — “Microelectronic circuit element” ........24
`A. Claims 1, 3, 6-7, 11, 13 and 15 — “Microelectronic circuit element” ...... ..24
`B. Claims 1, 11 and 13 — “Etching” and “etch-stop layer” ............................24
`B. Claims 1, 11 and 13 — “Etching” and “etch-stop layer” .......................... ..24
`C. Claims 1, 3-5, 11-13, 15-18 — “Wafer”......................................................25
`C. Claims 1, 3-5, 11-13, 15-18 — “Wafer” .................................................... ..25
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`XI. Claims 1-4, 6, 7, 10 and 11 are anticipated by Liu. .......................................25
`XI.
`Claims 1-4, 6, 7, 10 and 11 are anticipated by Liu ...................................... ..25
`A. Summary of opinions relating to Liu ...........................................................25
`A.
`Summary of opinions relating to Liu ......................................................... ..25
`B. Liu is prior art ..............................................................................................25
`B. Liu is prior art ............................................................................................ ..25
`C. Summary of Liu ...........................................................................................25
`C.
`Summary of Liu ......................................................................................... ..25
`D. Element-by-element analysis of claims 1-4, 6-7 and 10-11 over Liu .........29
`D. Element-by-element analysis of claims 1-4, 6-7 and 10-11 over Liu ....... ..29
`1.
`Independent claim 1 .................................................................................29
`1.
`Independent claim 1 ............................................................................... ..29
`2. Claim 2 .....................................................................................................34
`2.
`Claim 2 ................................................................................................... ..34
`3. Claim 3 .....................................................................................................36
`3.
`Claim 3 ................................................................................................... ..36
`4. Claim 4 .....................................................................................................38
`4.
`Claim 4 ................................................................................................... ..38
`5. Claim 6 .....................................................................................................39
`5.
`Claim 6 ................................................................................................... ..39
`6. Claim 7 .....................................................................................................40
`6.
`Claim 7 ................................................................................................... ..40
`7. Claim 10 ...................................................................................................41
`7.
`Claim 10 ................................................................................................. ..41
`8.
`Independent claim 11 ...............................................................................42
`8.
`Independent claim 11 ............................................................................. ..42
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`XII. Claims 2-4 and 11 obvious over Liu in combination with Black. .................44
`XII. Claims 2-4 and 11 obvious over Liu in combination with Black................ ..44
`A. Summary of opinions relating to Liu and Black ..........................................44
`A.
`Summary of opinions relating to Liu and Black ........................................ ..44
`B. Black is prior art ...........................................................................................44
`B. Black is prior art......................................................................................... ..44
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`C. Summary of Black .......................................................................................44
`D. There was motivation to combine Liu and Black ........................................47
`E. Element-by-element analysis of claims 2-4 over Liu in combination with
`Black ....................................................................................................................48
`1. Claim 2 .....................................................................................................48
`2. Claim 3 .....................................................................................................49
`3. Claim 4 .....................................................................................................50
`4.
`Independent claim 11 ...............................................................................51
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`XIII. Claims 5 and 12-16 are obvious over Liu in view of Riseman. ....................52
`A. Summary of opinions relating to Liu and Riseman .....................................52
`B. Riseman is prior art ......................................................................................52
`C. Summary of Riseman ...................................................................................52
`D. There was motivation to combine Liu with Riseman ..................................54
`E. Element by Element Analysis of Claims 5 and 11-16. ................................57
`1. Claim 5 .....................................................................................................57
`2. Claim 12 ...................................................................................................59
`3.
`Independent claim 13 ...............................................................................59
`4. Claim 14 ...................................................................................................61
`5. Claim 15 ...................................................................................................62
`6. Claim 16. ..................................................................................................63
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`XIV. Claim 8 is obvious over Liu in combination with Oldham. ..........................64
`A. Summary of opinions relating to Liu and Oldham ......................................64
`B. Oldham is prior art .......................................................................................64
`C. Summary of Oldham ....................................................................................64
`D. Element-by-element analysis of claim 8 in view of Liu and Oldham .........65
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`XV. Claim 10 is obvious over Liu in combination with Wen. .............................66
`A. Summary of opinions relating to Liu and Wen ...........................................66
`B. Wen is prior art ............................................................................................67
`C. Summary of Wen .........................................................................................67
`D. There was motivation to combine Liu and Wen ..........................................70
`E. Element-by-element analysis of claim 10 ....................................................71
`1. Claim 10 ...................................................................................................71
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`XVI. Claim 9 is invalid as obvious over Liu in combination with Wen and Ying. ...
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` .......................................................................................................................72
`A. Summary of opinions relating to Wen and Ying .........................................72
`B. Ying is prior art ............................................................................................72
`C. Summary of Ying .........................................................................................73
`D. There was motivation to combine Liu with Wen and Ying ........................73
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`E. Element-by-element analysis of claim 9 over Wen in combination with
`Ying ......................................................................................................................74
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`XVII. Claim 17 is obvious over Liu in combination with Riseman and Kusunoki.78
`A. Summary of opinion ....................................................................................78
`B. Kusunoki is prior art ....................................................................................78
`C. Summary of Kusunoki .................................................................................79
`D. Element-by-element analysis of claim 17 ....................................................80
`1. Claim 17 ...................................................................................................80
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`XVIII. Claim 18 is obvious over Liu in combination with Riseman and Oldham. .83
`A. Summary of opinion relating to Liu in combination with Riseman and
`Oldham .................................................................................................................83
`B. Element-by-element analysis of claim 18 over Liu in combination with
`Riseman and Oldham ...........................................................................................83
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`XIX. Oath ................................................................................................................85
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`1.
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`I, Richard A. Blanchard hereby declare as follows:
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`I.
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`Engagement and compensation
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`2.
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`I have been retained by Sony Corporation to serve as an expert in the
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`inter partes review proceeding described above. I have been asked to provide my
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`technical review, analysis, insights, and opinions regarding the references that form
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`the basis for the grounds of unpatentability set forth in the Petition for inter partes
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`review of US 5,591,678 (the ’678 Patent). For this service, my billing rate is an
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`hourly consulting fee of $375/hour, and I am reimbursed for actual expenses. My
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`compensation in no way depends on the outcome of this matter.
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`3.
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`I previously provided a declaration in support of Sony Corporation’s
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`Petition for inter partes review of the ’678 patent in IPR2015-01201.
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`II.
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`Summary of opinions
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`4.
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`It is my opinion that claims 1-4, 6-7 and 10-11 of the ’678 patent are
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`unpatentable as anticipated by Liu (Ex. 1003).
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`5.
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`It is further my opinion that claims 2-4 and 11 are obvious based on
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`Liu in combination with Black (Ex. 1007).
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`6.
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`It is further my opinion claims 5 and 12-16 are obvious based on Liu
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`in combination Riseman (Ex. 1009).
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`7.
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`It is further my opinion that claim 8 is obvious based on Liu in
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`combination with Oldham (Ex. 1005).
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`8.
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`It is further my opinion that claim 10 is obvious based on Liu in
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`combination with Wen (Ex. 1004).
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`9.
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`It is further my opinion that claim 9 is obvious based on Liu in
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`combination with Wen and Ying (Ex. 1006).
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`10.
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`It is further my opinion that claim 17 is obvious based on Liu in
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`combination with Riseman and Kusunoki (Ex. 1008).
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`11.
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`It is further my opinion that claim 18 is obvious based on Liu in
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`combination with Riseman and Oldham.
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`III. Qualifications1
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`12.
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`I am a consultant for InSciTech, Inc., a company specializing in
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`accident investigation and expert witness litigation support. I also provide
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`technical consulting services to the semiconductor and electronics industry through
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`Blanchard Associates.
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`13. My academic credentials include both a Bachelor of Science Degree
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`in Electrical Engineering (BSEE) in 1968 and a Master of Science Degree in
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`Electrical Engineering (MSEE) from the Massachusetts Institute of Technology in
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`1970. I subsequently obtained a Ph.D. in Electrical Engineering from Stanford
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`University in 1982.
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`1 Introductory sections II-X are essentially the same as set forth in my declaration
`in support of the Petition in IPR2015-01201. New subject matter begins in Section
`XI, p. 25.
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`14. My professional background and technical qualifications are stated
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`above and are also reflected in my curriculum vitae, which is attached as Appendix
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`1. These qualifications are summarized below.
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`15.
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`I have worked or consulted for more than 40 years as an
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`Electrical Engineer. My primary focus has been the development, manufacture,
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`operation and use of discrete devices and integrated circuits, the assembly of these
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`discrete devices and integrated circuits, products that use them, and their failures.
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`My employment history following my graduation from MIT began at Fairchild
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`Semiconductor in 1970. At Fairchild, my responsibilities included circuit and
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`device design, process development and product engineering in the Linear
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`Integrated Circuits Department.
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`16.
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`In 1974, I joined Foothill College as an Associate Professor in the
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`Engineering & Technology Division. My responsibilities included developing a
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`program in Semiconductor Technology as well as teaching other courses in the
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`division. While at Foothill College, I co-founded two companies, Cognition and
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`Supertex. Cognition developed and manufactured semiconductor pressure sensors
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`using a wafer bonding technique, while Supertex designed and manufactured
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`discrete semiconductor devices and integrated circuits. In 1978, I joined Supertex
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`as Vice President, where I developed discrete DMOS (double-diffused metal oxide
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`semiconductor) transistors as well as integrated circuits that contained DMOS
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`transistors. At Supertex, I also supervised the in-house assembly area, which
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`included responsibility for the packaging of discrete DMOS transistors as well as
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`integrated circuits that contained DMOS transistors.
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`17.
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`I left Supertex to join Siliconix in 1982, where I soon became Vice
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`President of Engineering, with the responsibility for directing all of the company’s
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`product design and development. At Siliconix, I directed and contributed to the
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`development of both discrete transistors and integrated circuits, including aspects
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`of their assembly.
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`18.
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`In 1987, I joined IXYS Corporation as a Senior Vice President with
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`the responsibility for organizing an integrated circuits department. At IXYS, I
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`developed integrated circuits that contained DMOS transistors or that interfaced to
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`DMOS devices. My responsibilities included the design, the fabrication, the
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`assembly, and the testing of these integrated circuits.
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`19. These duties continued until 1991, when I left IXYS to set up
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`Blanchard Associates, a consulting firm specializing in semiconductor technology,
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`including intellectual property. Soon, thereafter, I was invited to join Failure
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`Analysis Associates, which I did in late 1991. At Failure Analysis Associates, I
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`investigated failures in electrical and electronic systems in addition to performing
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`design and development consulting.
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`20.
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`I left Failure Analysis in 1998 to join IP Managers, which later
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`merged with the Silicon Valley Expert Witness group, which is now known as
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`Thomson Reuters Expert Witness Services (“Thomson Reuters”). At Thomson
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`Reuters, I worked with companies on patent and trade secret matters. I also
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`consulted for a number of semiconductor companies, working with them to
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`develop products and intellectual property, or assisting them in other technical
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`areas through Blanchard Associates.
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`21.
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`In 2014, I became a Staff Consultant at InSciTech, Inc., where I
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`continue to consult with clients on patent and trade secret matters. I also work
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`with semiconductor and electronics companies on other technical matters.
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`22. As shown in my resume (see Appendix 1), I am a named inventor on
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`more than 200 issued or pending U.S. patents, have co-authored a number of
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`articles, and have co-authored or contributed to a number of books.
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`23.
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`I am a member of a number of professional societies, including the
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`institute of Electrical and Electronic Engineers, the International Microelectronic
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`Device Failure Analysis Society, and the Electrostatic Discharge Society.
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`IV. My understanding of the relevant law
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`A. Claim construction
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`24.
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`I understand that, when a patent is expired, a claim term in an inter
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`partes review is to be interpreted in the following manner: First, the language of
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`the claims themselves is of primary importance in the effort to determine precisely
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`what it is that is patented. The terms used in a claim are generally given the
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`ordinary and customary meaning that the terms would have to a person of ordinary
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`skill in the art in question at the time of the alleged invention, unless the term is
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`expressly defined in the patent. The person of ordinary skill in the art reads the
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`claim in the context of the entire patent, including the specification. Next to the
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`language of the claims, the specification is the single best source for interpreting
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`the claim terms. The claims may also be interpreted using the record of
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`correspondence between the patent applicant and the Patent Office, and also with
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`reference to other sources of evidence that can help to define the meaning of terms
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`to a person of ordinary skill in the relevant time frame. I define the relevant time
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`frame in ¶62, below.
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`B. Anticipation
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`25.
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`I understand that a claim in an issued patent can be invalid if it is
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`anticipated. In this case, “anticipation” means that there is a single prior art
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`reference that discloses every element of the claim, arranged in the way required
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`by the claim.
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`26.
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`I understand that an anticipating prior art reference must disclose each
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`of the claim elements expressly or inherently. I understand that “inherent”
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`disclosure means that the claim element, although not expressly described by the
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`prior art reference, must necessarily be present based on the disclosure. I
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`understand that a mere probability that the element is present is not sufficient to
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`qualify as “inherent disclosure”.
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`C. Obviousness
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`27.
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`I understand that a claim in an issued patent can be invalid if it is
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`obvious. Unlike anticipation, obviousness does not require that every element of
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`the claim be in a single prior art reference. Instead, it is possible for claim
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`elements to be described in different prior art references, so long as there is
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`motivation or sufficient reasoning to combine the references.
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`28.
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`I understand that a claim is invalid for obviousness if the differences
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`between the claimed subject matter and the prior art are such that the subject
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`matter as a whole would have been obvious at the time the alleged invention was
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`made to a person having ordinary skill in the art to which said subject matter
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`pertains.
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`29.
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`I understand, therefore, that when evaluating obviousness, one must
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`consider obviousness of the claim “as a whole”. This consideration must be from
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`the perspective of the person of ordinary skill in the relevant art, and that such
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`perspective must be considered as of the “time the invention was made”.
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`30. The level of ordinary skill in the art is discussed in ¶¶55-60, below.
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`31. The relevant time frame for obviousness, the “time the invention was
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`made”, is discussed in ¶62, below.
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`32.
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`I understand that in considering the obviousness of a claim, one must
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`consider four things. These include the scope and content of the prior art, the level
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`of ordinary skill in the art at the relevant time, the differences between the prior art
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`and the claim, and any “secondary considerations”.
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`33.
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`I understand that “secondary considerations” include real-world
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`evidence that can tend to make a conclusion of obviousness either more probable
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`or less probable. For example, the commercial success of a product embodying a
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`claim of the patent could provide evidence tending to show that the claimed
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`invention is not obvious. In order to understand the strength of the evidence, one
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`would want to know whether the commercial success is traceable to a certain
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`aspect of the claim not disclosed in a single prior art reference (i.e., whether there
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`is a causal “nexus” to the claim language). One would also want to know how the
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`market reacted to disclosure of the invention, and whether commercial success
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`might be traceable to things other than innovation, for example the market power
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`of the seller, an advertising campaign, or the existence of a complex system having
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`many features beyond the claims that might be desirable to a consumer. One
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`would also want to know how the product compared to similar products not
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`embodying the claim. I understand that commercial success evidence should be
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`reasonably commensurate with the scope of the claim, but that it is not necessary
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`for a commercial product to embody the full scope of the claim.
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`34. Other kinds of secondary considerations are possible. For example,
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`evidence that the relevant field had a long-established, unsolved problem or need
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`that was later provided by the claimed invention could be indicative of non-
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`obviousness. Evidence that others had tried, but failed to make an aspect of the
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`claim might indicate that the art lacked the requisite skill to do so. Evidence of
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`copying of the patent owner’s products before the patent was published might also
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`indicate that its approach to solving a particular problem was not obvious.
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`Evidence that the art recognized the value of products embodying a claim, for
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`example, by praising the named inventors’ work, might tend to show that the claim
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`was non-obvious.
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`35.
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`I further understand that prior art references can be combined where
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`there is an express or implied rationale to do so. Such a rationale might include an
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`expected advantage to be obtained, or might be implied under the circumstances.
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`For example, a claim is likely obvious if design needs or market pressures existing
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`in the prior art make it natural for one or more known components to be combined,
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`where each component continues to function in the expected manner when
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`combined (i.e., when there are no unpredictable results). A claim is also likely
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`invalid where it is the combination of a known base system with a known
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`technique that can be applied to the base system without an unpredictable result.
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`In these cases, the combination must be within the capabilities of a person of
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`ordinary skill in the art.
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`36.
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`I understand that when considering obviousness, one must not refer to
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`teachings in the specification of the patent itself. One can, however, refer to
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`portions of the specification admitted to be prior art, including the
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`“BACKGROUND” section. Furthermore, a lack of discussion in the patent
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`specification concerning how to implement a disclosed technique can support an
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`inference that the ability to implement the technique was within the ordinary skill
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`in the prior art.
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`V. Technical introduction
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`A. Background
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`37. The following is a brief technical background covering some concepts
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`relevant to the ’678 patent specification and its claims.
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`38. The ’678 patent has the title “PROCESS OF MANUFACTURING A
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`MICROELECTRIC DEVICE USING A REMOVABLE SUPPORT SUBSTRATE
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`AND ETCH-STOP”. This title provides only a modest amount of information
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`about the problem that the ’678 patent addresses. However, the section of the ’678
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`patent title “Background of the Invention” contains the following information
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`concerning the problems the inventors address.
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`“The present inventors have determined that for some applications it
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`would be desirable to stack and interconnect a number of such two-
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`dimensional microelectronic devices fabricated on a substrate wafer,
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`one of top of the other to form a three-dimensional device. The stack
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`might also include other circuit elements such as interconnect layers
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`and thin film sensors as well.” (Ex. 1001, 1:44-50).
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`Stacking two or more semiconductor die has several possible advantages.
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`Typically, a circuit board is a rectangle of material, and may have to fit in a
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`compact computer or other device. Because of the size limitations of the housing
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`of the computer or other device, circuit boards often have limited area. Stacked die
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`will occupy less area on a substrate such as a printed circuit board, so allow
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`physically smaller electronic systems in applications that use die mounted on a
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`substrate. They also allow multiple die to be incorporated into a single package
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`that occupies approximately the same area on the circuit board as a single die,
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`resulting in both less surface area on a substrate and a smaller package volume,
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`which can further reduce the system size in an application that uses packaged ICs
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`mounted to the substrate. It is also possible to join ICs made using different
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`technologies, producing a circuit with the combined features of each IC. There
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`was an active industry in designing stack semiconductor die arrangements during
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`the relevant time frame.
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`B. ’678 Patent Disclosure
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`39. The specification of the ’678 patent provides a description of the
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`fabrication method (Ex. 1001 2:15-28) as well as showing a diagrammatic process
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`flow diagram of the steps used in the process in Figure 1 of the ’678 patent as
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`shown below.
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`“In accordance with the invention, a method of fabricating a
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`microelectronic device comprises the steps of furnishing a first
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`substrate having an etchable layer, an etch-stop layer overlying the
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`etchable layer, and a wafer overlying the etch-stop layer, and forming
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`a microelectronic circuit element in the wafer of the first substrate.
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`The method further includes attaching the wafer portion of the first
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`substrate to a second substrate, and etching away the etchable layer of
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`the first substrate down to the etch-stop layer. The second substrate
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`may include a microelectronic device, and the procedure may include
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`the further step of interconnecting the microelectronic device on the
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`first substrate with the microelectronic device on the second
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`substrate.” (Ex. 1001, 2:15-28).
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`Figure 1 of the ’678 patent. (Ex. 1001, Fig. 1).2
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`Figure 1 of the ’678 patent shows the technique described in this patent. The
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`specific steps shown in Figure 1 are discussed in ¶¶40-45 below.
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`2 Note: The drawing labeled 26 in Figure 1 appears to contain an error. The
`element labeled 56 in drawing 24 and 28 is missing in drawing 26.
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`40. Stacks are made using semiconductor-based building blocks referred
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`to as “substrates”. The first step, 20, (labeled
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`“Furnish First Substrate” in Fig. 1) is furnishing
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`a substrate, 40, shown in the portion of Fig. 1 of
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`the ’678 patent at right, with highlighting added.
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`The substrate has three layers:
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`42 – An etchable layer (colored blue);
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`44 – An etch stop layer (in this instance, a layer of silicon dioxide)
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`(colored green); and
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`46 – A layer of single crystal silicon (a “wafer”) (colored yellow),
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`containing integrated circuit elements, such as transistors.
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`The three-layer substrate, 40, was not new. The ’678 patent states that “[s]uch
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`substrates can be purchased commercially.” (Ex. 1001, 4:2). Also shown in
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`Figure 1, for the first step (labeled “20”) is a via, 48, etched through layer 46.
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`41. The second step, 22, (labeled “Form Microelectronic Circuit” in Fig.
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`1) is a process sequence consisting of well-known semiconductor fabrication steps
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`which is first used to form one or more microelectronic circuit elements (50). The
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`present substrate is next processed so that both front side conductors (indium
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`bumps, 61) and back side conductors (backside electrical interconnect) are present.
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`14
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`42.
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`In the third step, 24, (labeled “Attach Second Substrate” in Fig. 1), a
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`second substrate, 58, which may include devices, is attached to the front of the
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`structure, and is electrically contacted by the indium bumps, 61. An excerpt from
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`Fig. 1 is reproduced below, with the second substrate, 58, highlighted in yellow.
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`The second substrate, 58, and wafer, 46, are physically bonded (using, for
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`example, epoxy), and are electrically connected (using, for example, an indium
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`solder process). The second substrate may include its own microelectronic circuit
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`element.
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`43.
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`In th