UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`HTC CORPORATION, HTC AMERICA, INC.,
`and APPLE, INC.,
`Petitioner,
`
`v.
`
`PARTHENON UNIFIED MEMORY ARCHITECTURE LLC,
`Patent Owner.
`____________
`
`Case IPR2016-009231
`Patent 5,812,789
`____________
`
`Declaration of Mitchell A. Thornton, Ph. D., P.E.
`
`
`1 Case IPR2016-00847 has been joined with this proceeding.
`
`PUMA Exhibit 2003
`HTC v. PUMA, IPR 2016-00923
`Page 1
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`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`HTC CORPORATION, HTC AMERICA, INC.,
`and APPLE, INC.,
`Petitioner,
`
`v.
`
`PARTHENON UNIFIED MEMORY ARCHITECTURE LLC,
`Patent Owner.
`____________
`
`Case IPR2016-009231
`Patent 5,812,789
`____________
`
`Declaration of Mitchell A. Thornton, Ph. D., P.E.
`
`
`1 Case IPR2016-00847 has been joined with this proceeding.
`
`PUMA Exhibit 2003
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`Page 1
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`I.
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`Introduction
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`1.
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`I am over the age of eighteen (18) and otherwise competent to make
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`this declaration.
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`2. My name is Mitchell Aaron Thornton. I am offering this declaration
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`in the matter listed above on behalf of Parthenon Unified Memory Architecture
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`LLC and at the behest of their attorneys Ahmad, Zavitsanos, Anaipakos, Alavi &
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`Mensing P.C. I am being compensated at my usual rate and my compensation is
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`not dependent on any opinions that I may take in this matter, any testimony, or any
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`intermediate or final resolution in the matter.
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`3.
`
`I understand that the Board has issued an institution Decision in the
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`above-captioned IPR concluding that the Petitioner has established a reasonable
`
`likelihood of success with respect to the following grounds (collectively “Instituted
`
`Grounds”):
`
`a. Anticipation of claims 1, 3, 5, 11, and 13 by Lambrecht;
`
`b. Obviousness of claim 4 over Lambrecht and Artieri; and
`
`c. Obviousness of claim 6 over Lambrecht and Moore.
`
`4.
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`This declaration is directed to an analysis of these Instituted Grounds.
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`II. My Background and Qualifications
`
`5.
`
`I earned a Bachelor of Science degree in Electrical Engineering from
`
`Oklahoma State University in 1985. In 1990, I earned a Masters of Science degree
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`1
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`in Electrical Engineering from the University of Texas at Arlington. In 1993, I
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`earned a Masters of Science degree in Computer Science from Southern Methodist
`
`University. I earned a Ph.D. in Computer Engineering from Southern Methodist
`
`University in 1995. I am a Licensed Professional Engineer in the states of Texas,
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`Mississippi, and Arkansas. I also hold a Commercial General Radiotelephone
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`Operator License (GROL) with Ship Radar endorsement issued by the Federal
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`Communications Commission (FCC).
`
`6.
`
`I am currently the Cecil H. Green Chair of Engineering and Professor
`
`in the Department of Computer Science and Engineering and in the Department of
`
`Electrical Engineering at Southern Methodist University. Prior to 2002, I served as
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`a faculty member at Mississippi State University in the Department of Electrical
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`and Computer Engineering from 1999 through 2002. I served as a faculty member
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`at the University of Arkansas from 1995 through 1999 in the Department of
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`Computer Systems Engineering. In my university positions, my responsibilities
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`are research, teaching, and providing service in my profession. My teaching and
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`research area of expertise is generally in the area of computer engineering where I
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`specialize in hardware design for information processing systems.
`
`7.
`
`In addition to my academic rank of professor, I am also the Associate
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`and Technical Director of the Darwin Deason Institute for Cyber Security at
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`Southern Methodist University. The Institute mission is to advance the science,
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`policy, application and education of cyber security through basic and problem-
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`driven, interdisciplinary research. As Associate and Technical Director, I am
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`responsible for the coordination and oversight of all research projects within the
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`auspices of this multi-million dollar endowed research Institute that is comprised
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`of 11 principal investigators and their associated research teams. In this role, I am
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`routinely involved with several different state-of-the-art projects regarding the
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`technical aspects of information processing system processes, methods, software,
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`and hardware.
`
`8.
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`Prior to my academic career, I was employed in the commercial sector
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`as an engineer. I was employed full-time at E-Systems, Inc. (now L3
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`Communications) in Greenville, Texas from 1986 through 1991 and resigned from
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`my position as Senior Electronic Systems Engineer in 1991 to pursue full-time
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`graduate studies in Computer Science and Computer Engineering. My duties at E-
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`Systems involved the design, analysis, implementation, and test of a variety of
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`different electronic systems including various information processing systems
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`centered around signal processing, data transmission and processing, and
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`communications systems. The communications systems I was involved with
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`processed a variety of different types of signals including data, audio, and video
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`systems. These systems were comprised of components such as receivers,
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`transmitters, computers, and special purpose circuitry.
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`3
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`9.
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`During the time I was in graduate school pursuing the Ph.D. degree, I
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`also worked part-time and full-time during the summer of 1992 at a commercial
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`integrated circuit (IC) design company named the Cyrix Corporation. At Cyrix, I
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`was a member of a design team that ultimately produced a microprocessor that is
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`compatible with the Intel Pentium. My duties included the design of the bus
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`controller and memory interface circuitry for this IC.
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`10. My practice and research covers a range of topics centered around
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`hardware design and analysis including secure circuit and embedded system
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`design, electronic design automation (EDA) methods, and algorithms for quantum,
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`classical digital systems, and large systems design. I have also maintained an
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`independent professional engineering practice since 1993 as a sole proprietor that
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`is a registered engineering firm in the state of Texas.
`
`11.
`
`I am a named inventor on four (4) issued patents and one (1) patent
`
`application under consideration at the USPTO. I have authored or coauthored over
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`200 scholarly publications in the fields of electrical engineering and computer
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`science.
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`12. My curriculum vitae and testimony list are included in Appendix A to
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`this declaration, which more fully sets forth my qualifications.
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`4
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`III. Documents Considered
`In addition to my knowledge and experience, I have reviewed and
`13.
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`relied upon the following materials in performing my analysis:
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`• The `789 Patent (and the publications incorporated by reference therein)
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`and its file history;
`
`• Petition for Inter Partes Review of U.S. Patent No. 5,812,789 including
`
`all the exhibits [IPR2016-00923];
`
`• Decision on Institution in IPR2016-00923;
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`• Shanley, et al., “PCI System Architecture,” Addison-Wesley Publishing
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`Company, 1995 (3rd ed.) (“Shanley”)
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`• Gordon E. Moore, Cramming More Components onto Integrated
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`Circuits, 38 ELECTRONICS 114 (1965) [Ex. 1035] (“Moore”);
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`• U.S. Patent No. 5,682,484 [Ex. 1032] (“Lambrecht”);
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`• U.S. Patent No. 5,579,052 [Ex. 1036] (“Artieri”);
`
`• Declaration of Harold S. Stone, Ph.D. [Ex. 1030] (“Stone Decl.”); and
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`• Deposition testimony of Harold S. Stone, Ph.D. dated November 16,
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`2016 [Ex. 2004] (“Stone Depo.”).
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`5
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`IV. Summary of Opinions
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`14. As detailed below, it is my opinion that the challenged independent
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`claims are not anticipated by Lambrecht and that the challenged dependent claims
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`are also not anticipated or obvious for at least the same reasons.
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`V. Legal Standards
`
`15.
`
`I am not an attorney or patent agent, and thus, I have relied upon
`
`certain legal factors that have been explained to me. Some of these, which form the
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`legal framework for the opinions I am providing, are summarized below.
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`16.
`
`I understand that claims are to be interpreted from the perspective of
`
`one of ordinary skill in the art. I understand that in determining the level of
`
`ordinary skill in the art, the following factors may be considered: (1) the
`
`educational level of the inventor; (2) type of problems encountered in the art; (3)
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`prior art solutions to those problems; (4) rapidity with which innovations are made;
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`(5) sophistication of the technology; and (6) educational level of active workers in
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`the field.
`
`17.
`
`I understand from reading the Board’s decision that in this inter partes
`
`review, claim terms are to be given their broadest reasonable construction in light
`
`of the patent specification. I also understand that claim terms are presumed to be
`
`given their ordinary and customary meaning as would be understood by one of
`
`ordinary skill in the art. Furthermore, I understand that an inventor may provide a
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`contrary definition of a term in the specification, if it is done with reasonable
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`clarity, deliberateness, and precision. I also understand that care must be taken not
`
`to read a particular embodiment appearing in the specification into the claim if the
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`claim language is broader than the embodiment.
`
`18.
`
`I understand that a claim may be invalid as anticipated or as being
`
`obvious.
`
`19.
`
`I understand that a claim is not patentable and is anticipated if a single
`
`prior art reference discloses each and every element recited in the claim, expressly
`
`or inherently, such that a person of ordinary skill in the art could practice the
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`disclosed embodiment without undue experimentation. I also understand that the
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`claim elements must be arranged in the reference in the same way as in the claim.
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`20.
`
`I understand that an element is inherent in a reference if one of
`
`ordinary skill in the art would understand that the reference makes clear that the
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`element, while not expressly disclosed, is necessarily present in the reference.
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`Inherency, however, may not be established by probabilities or possibilities.
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`21.
`
`I understand that the obviousness standard is defined in the patent
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`statute (35 U.S.C. § 103(a)). I also understand that a claim is not patentable and is
`
`obvious if the differences between a claim and the prior art are such that the
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`claimed subject matter as a whole would have been obvious to a person having
`
`ordinary skill in the art at the time the invention was made. I understand that this
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`7
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`inquiry involves examination of number of factors including: (1) determining the
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`scope and content of the prior art; (2) ascertaining the differences between the
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`claim and the prior art; (3) resolving the level of ordinary skill in the prior art; and
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`(4) considering any secondary or objective evidence of non-obviousness. I
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`understand that secondary or objective evidence of non-obviousness include
`
`factors such as commercial success, long felt need for the invention, and failure of
`
`others.
`
`22.
`
`I understand that an obviousness analysis involves comparing a claim
`
`to the prior art to determine whether the claimed invention would have been
`
`obvious to a Person of Ordinary Skill in the Art (“POSA”) in view of the prior art,
`
`and in light of the general knowledge in the art. I also understand when a POSA
`
`would have reached the claimed invention through routine experimentation, the
`
`invention may be deemed obvious.
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`23.
`
`I also understand that obviousness can be established by combining or
`
`modifying the teachings of the prior art to achieve the claimed invention. It is also
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`my understanding that where there is a reason to modify or combine the prior art to
`
`achieve the claimed invention, there must also be a reasonable expectation of
`
`success in so doing. I understand that the reason to combine prior art references
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`can come from a variety of sources, not just the prior art itself or the specific
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`problem the patentee was trying to solve. And I understand that the references
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`themselves need not provide a specific hint or suggestion of the alteration needed
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`to arrive at the claimed invention; the analysis may include recourse to logic,
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`judgment, and common sense available to a person of ordinary skill that does not
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`necessarily require explication in any reference. Finally, it is my understanding that
`
`obviousness can be established by choosing from a finite number of identified,
`
`predictable solutions, with a reasonable expectation of success.
`
`24.
`
`I further understand that a patent composed of several elements is not
`
`proved obvious merely by demonstrating that each of its elements was,
`
`independently, known in the prior art. I further understand that a showing of a
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`suggestion, teaching, or motivation to combine the prior art references is an
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`essential evidentiary component of an obviousness conclusion. I further understand
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`that a claim is not obvious if the references relied upon in a proposed combination
`
`teach away from the claimed combination in a way that would deter any
`
`investigation into such a combination. For instance, it is my understanding that a
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`reference teaches way from a combination when using it in that combination would
`
`produce an inoperative result.
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`VI. Level of Ordinary Skill in the Art
`
`25.
`
`In formulating my opinions, I have also considered the viewpoint of a
`
`person of ordinary skill in the art (“POSA”) at the time of the filing of the `789
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`9
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`Patent.
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`26.
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`I understand that Dr. Stone has opined that a person of ordinary skill
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`in the art as of the effective filing date of the `789 Patent would have held an
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`accredited Bachelor’s degree in Electrical Engineering and/or Computer Science
`
`and/or Computer Engineering and had three years’ experience in the fields of data
`
`compression and overall computer system architecture. [Stone Decl., Ex 1030,
`
`¶75].
`
`27. Based upon my knowledge of this field, I conclude that a person of
`
`ordinary skill in this art at the time of the filing of the `789 Patent, and for that
`
`matter, at all subsequent times through the present, would have held at least a
`
`Bachelor’s degree in electrical engineering, computer engineering, or an equivalent
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`degree in a related discipline from an accredited institution of higher learning and
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`at least two to three years’ experience in signal and/or image processing and
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`computer architecture at both the systems and micro-architecture level. In lieu of
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`two to three years of experience, a person of ordinary skill in the art may hold, in
`
`addition to a Bachelor’s degree as described above, a Master’s or other graduate
`
`degree in electrical or computer engineering with a focus in computer architecture
`
`and signal and/or image processing with one year of relevant experience.
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`28. My analysis was performed from the perspective of such a person. If
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`I were to apply the level of ordinary skill as proffered by Dr. Stone in his
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`declaration, my analysis and conclusions would remain unchanged.
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`VII. State of the Prior Art and the `789 Patent
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`29. The computer memory storage requirements of a digital representation
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`of an uncompressed image is dependent on its resolution, color depth, and size in
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`pixels. Video files are comprised of sequences of images that are further enhanced
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`with a corresponding audio track to accompany them. As a result, a video file
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`quickly becomes large in size. The transmission of uncompressed video files is
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`prohibitively expensive.
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`30. Accordingly, video files are typically compressed at a transmitting
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`device. The compressed file is then transmitted to a receiving device where it is
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`decompressed. To that end, an encoder at the transmitter compresses the video file
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`and a decoder decompresses the file received at the receiver in order to retrieve a
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`facsimile of the original video and audio data. In order to ensure compatibility
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`between devices, a number of standards for encoding and decoding video files
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`were developed. One of those standards was developed by the Motion Picture
`
`Experts Group (“MPEG”) and has been adopted as a standard for the
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`communication of video.
`
`31.
`
`If a decoder does not operate in real time, the decoded video being
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`displayed would stop periodically between images until the decoder can access the
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`memory and process the subsequent image frame. Moreover, when using a
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`temporal (intercompression) technique such as the MPEG Standard, some of the
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`images are decoded based on previous images and some based on previous and
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`subsequent images. Accordingly, dropping an image on which the decoding of
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`other images depends is unacceptable as it can result in poor or unrecognizable
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`decoded images. Therefore, it is typically the case that a decoder requires its own
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`dedicated memory. For instance, traditional MPEG decoders require a 2 Mbyte
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`dedicated memory that is utilized during the decoding process. This dedicated
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`memory is necessary to allow the decoder to decode images in real-time without
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`dropping frames that would result in a deterioration of the video quality at the
`
`receiver.
`
`32.
`
`It is generally desirable to reduce the die area of an integrated circuit
`
`device for a given functionality. Such a reduction allows for an increase in the
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`number of the die that can be manufactured on a silicon wafer having a given size.
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`For example, a video decoder die would be reduced in size if it did not include a
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`dedicated memory circuit. Moreover, such a dedicated memory of a decoder may
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`remain unused when an image is not being decoded which is inefficient.
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`Accordingly, it is desirable to permit the decoder to share the main memory of the
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`system with other system components.
`
`33. To that end, the `789 Patent is generally directed to sharing both a
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`memory interface and a memory between a video and/or audio decoder and
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`another device contained in an electronic system. [`789 Pat. [Ex. 1001],
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`12
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`Abstract; 4:12-22; 4:30-34; 4:40-48; independent claim 1]. Accordingly, the
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`electronic system includes a first device that requires access to the memory and
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`a decoder that requires access to the memory sufficient to maintain real time
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`operation. Id. at claim 1. A memory interface is coupled to the memory, the first
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`device and the decoder. Id. The memory interface includes an arbiter for
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`selectively providing access for the first device and the decoder to the memory.
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`Id. A shared bus is coupled to the memory, the first device and the decoder. Id.
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`The shared bus has sufficient bandwidth to enable the decoder to access the
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`memory and operate in real time when the first device simultaneously accesses
`
`the shared bus. Id.
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`34. A video decoder only requires access to memory during its operation.
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`In accordance with the implementation of the `789 Patent, other devices such as a
`
`first device may have exclusive access to a shared memory when the decoder is not
`
`operating. In such instances, the first device can use the entire bandwidth of the
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`fast bus to support memory accesses.
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`35. The fast bus (70) of the `789 Patent has a bandwidth that is at least
`
`twice the required bandwidth to support the memory accesses needed to support
`
`real time video decoding. [`789 Pat., 6:67-7:2]. Accordingly, the video decoder
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`will typically be using less than 40% of the bandwidth of the fast bus (70) during
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`decoding. [`789 Pat., 7:18-20]. This frees up the remaining bandwidth to be used
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`by other devices such as a first device during the decoder operation. [`789 Pat.,
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`7:20-22]. Because the decoder does not use the entire available bandwidth of the
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`fast bus (70) during real time decoding, the remaining bus bandwidth may be used
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`by other devices, such as a first device, simultaneously while real time decoding is
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`occurring. [`789 Pat., 7:5-15].
`
`VIII. Claim Construction
`I understand that the Board has construed the term “video decoder” to
`36.
`
`mean “hardware and/or software
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`that
`
`translates data streams
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`into video
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`information.” (Institution Decision, Paper 10, at 8-9).
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`37.
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`I understand that the Board has construed the term “real time” as
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`“pertaining to a data-processing system that controls an ongoing process and
`
`delivers its outputs (or controls its inputs) not later than the time when these are
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`needed for effective control.” (Institution Decision, Paper 10, at 11).
`
`38.
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`I have used the Board’s construction of the terms “video decoder” and
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`“real time” in performing my analysis. I have used the plain and ordinary meaning
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`of the remaining claim terms when performing my analysis.
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`IX. Analysis of Instituted Grounds
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`A. Anticipation of Claims 1, 3, 5, 11, and 13 by Lambrecht
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`1) Lambrecht does not disclose “a shared bus … having a sufficient
`bandwidth to enable the decoder to access the memory and operate in
`real time” [Independent claim 1]
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`14
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`39. The Petition identifies multimedia device (142D) as the first device;
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`the main memory (110) as the memory; the multimedia device (144D) as the
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`decoder; and the PCI expansion bus (120) as the shared bus. [Pet. at 16]. The
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`Petitioner then contends that the PCI expansion bus (120) provides real time
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`access by the multimedia device (144D) (alleged decoder) to the main memory
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`(110) (alleged memory) when operating in the multimedia mode, which is a
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`special mode, optimized for real-time data transfers. [Pet. at 17-19]. I disagree
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`with that conclusion. Specifically, in my opinion, when operating in the
`
`multimedia mode, the PCI expansion bus (120) does not enable the multimedia
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`device (144D) (alleged decoder) to access the main memory (110) (alleged
`
`memory). Accordingly,
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`the PCI expansion bus (120) does not permit
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`communication between multimedia device (144D) and the main memory (110)
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`when it is placed in the multimedia mode.
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`40. The petitioner relies on the embodiment of Figure 21 of Lambrecht
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`for its contention that independent claim 1 is anticipated. [Pet. at 10-19]. With
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`respect to the embodiment of Figure 21, Lambrecht states that “[t]he computer
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`system of FIG. 21 is similar to the computer system of FIG. 1” except that “the
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`mode logic in the computer system of FIG. 21 is operable to place the PCI bus
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`120 in either a normal PCI mode or in a real-time/multimedia mode optimized
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`for multimedia transfers of periodic data.” [Lambrecht, Ex. 1032, 26:48-56].
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`Accordingly, the embodiment of Figure 21 replaces the PCI expansion bus
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`(120) and the real time bus (130) of Figure 1 with a single PCI expansion bus
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`(120) which has two different modes of operation: (1) a first mode of operation
`
`where the PCI Expansion Bus (120) operates like the PCI Expansion Bus (120)
`
`of Figure 1; and (2) a second mode of operation where the PCI Expansion Bus
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`(120) operates like the real time bus (130) of Figure 1. The mode logic (960)
`
`selects which of the two modes is enabled. [Lambrecht, 27:18-22]. Figure 1 and
`
`Figure 21 of Lambrecht are reproduced below, highlighting the difference
`
`between the two systems:
`
`
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`41. Because Lambrecht states that “[t]he computer system of FIG. 21 is
`
`similar to the computer system of FIG. 1,” one of ordinary skill in the art would
`
`understand that when the PCI Expansion Bus (120) of Figure 21 is in the
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`“normal PCI mode” it operates like the PCI Expansion Bus of the embodiment
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`of Figure 1. Conversely, when the PCI Expansion Bus (120) of Figure 21 is in
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`the multimedia mode it operates like the multimedia bus (130) of the
`
`embodiment of Figure 1. Therefore, for at least three reasons, the PCI Expansion
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`Bus (120) of the embodiment of Figure 21 does not enable the multimedia device
`
`(144D) (alleged decoder) to access the main memory (110) (alleged memory)
`
`when operating in the multimedia mode.
`
`42. First, as shown in Figure 1, the multimedia bus (130) (which
`
`operates “similar” to the PCI Expansion Bus (120) of Figure 21 operating in the
`
`multimedia mode) is not in communication with the PCI Bridge Chipset (106)
`
`and the main memory (110) and cannot transfer data from the multimedia
`
`device (144) (alleged decoder) to the main memory (110) (alleged memory).
`
`Second, with respect to the operation of the multimedia bus (130) of Figure 1,
`
`Lambrecht explicitly states
`
`that
`
`the multimedia bus (130) facilitates
`
`communication between the multimedia devices (142-146) – not between the
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`multimedia device (144D) (alleged decoder) and the main memory (110)
`
`(alleged memory):
`
`The multimedia devices 142-146 use the multimedia bus 130 to
`communicate data, preferably only periodic data, between the
`respective devices. … Thus, the multimedia devices 142-146
`communicate with each other via the PCI bus 120 and also
`communicate with the CPU and main memory 110 via the PCI bus
`120, as is well known in the art. The multimedia devices 142-146
`17
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`PUMA Exhibit 2003
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`also communicate data between each other using the real-time bus
`or multimedia bus 130. When the multimedia devices 142-146
`communicate using the real-time bus 130, the devices are not
`required to obtain PCI bus mastership and they consume little or no
`PCI bus cycles.”
`
`
`[Lambrecht, Ex. 1032, 8:8-28 (emphasis added)]. Accordingly, the multimedia
`
`bus (130) of Figure 1 does not enable the multimedia device (144D) (alleged
`
`decoder) to access the main memory (110) (alleged memory). Because the
`
`multimedia mode of the PCI Expansion Bus (120) of the embodiment of Figure
`
`21 operates similar to the multimedia bus (130) of the embodiment of Figure 1
`
`[Lambrecht, 26:51-52], the PCI Expansion Bus (120) of Figure 21 operating in
`
`the multimedia mode also does not enable the multimedia device (144D)
`
`(alleged decoder) to access the main memory (110) (alleged memory).
`
`43. Third, that the multimedia mode of the PCI Expansion Bus (120) does
`
`not enable the multimedia device (144D) (alleged decoder) to access the main
`
`memory (110) (alleged memory) is evident from a closer analysis of the
`
`embodiment of Figure 21. As is well known to those of ordinary skill in the art,
`
`bus standards such as the PCI standard are not defined solely based on their
`
`physical hardware assets. Instead, a bus is typically defined as a collection of
`
`assets including the hardware and the protocol for data transfer. For example,
`
`the Peripheral Component Interconnect (or PCI) specification is one that defines
`
`18
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`the PCI bus. The PCI bus is intended to define the interconnect and bus transfer
`
`protocol between highly-integrated peripheral adapters that reside on a common
`
`local bus on a system board or add-in expansion cards that are on the PCI bus
`
`[Shanley, Ex. 1019, p. 545]. Accordingly, Lambrecht introduces the use of a
`
`new, non-standard bus referred to as the “real-time/multimedia mode” or
`
`“multimedia mode” of the PCI Expansion Bus (120). The purpose of this new
`
`“multimedia mode” of the PCI Expansion Bus (120) is to allow periodic data
`
`transfers. [Lambrecht, 26:53-60]. In order to support the use of this new
`
`“multimedia mode” of the PCI Expansion Bus (120), specialized hardware
`
`(and/or software) must be included with all devices that enable them to use this
`
`new and non-standard protocol for data transmission. Accordingly, Lambrecht
`
`discloses interface logic (966) “for interfacing to the PCI bus 120 when the PCI
`
`bus 120 is in the multimedia mode.” [Lambrecht, 27:38-40] (“The bus interface
`
`circuitry 962 also includes interface logic 966 for interfacing to the PCI bus 120
`
`when the PCI bus 120 is in the multimedia mode. The bus interface circuitry 962
`
`also includes interface logic 968 for interfacing to the optional multimedia bus
`
`130”). As a result, all devices disclosed in Figure 21 that benefit from the new
`
`and non-standard “multimedia mode” of the PCI Expansion Bus (120) which
`
`enables real-time data transmission must necessarily include the interface logic
`
`19
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`(966) of the bus interface circuitry (962) to enable the use of the real-time
`
`multimedia mode of the PCI Expansion Bus (120). In contrast, one of ordinary
`
`skill in the art would appreciate that the components in Figure 21 which do not
`
`have the interface logic (966) of the bus interface circuitry (962) cannot utilize
`
`the “multimedia mode” of the PCI Expansion Bus (120) because they are not
`
`equipped to interface with it.
`
`44. Furthermore, because the new non-standard multimedia mode
`
`utilizes the same collection of signal lines as those used for the bus when it is in
`
`the standard or “normal” PCI mode of operation, a controlling circuit referred to
`
`as “mode logic” (960) must be present within the system that is operable to
`
`place the PCI bus 120 in either a normal PCI mode or in a real-time/multimedia
`
`mode optimized for multimedia transfers of periodic data. [Lambrecht, 26:48-
`
`56; 27:18-22]. The mode logic 960 is disclosed as being present in the chipset
`
`(106). [Lambrecht, 27:2-3; FIG. 21]. A POSA would therefore appreciate that
`
`the PCI bus (120) in Figure 21 of Lambrecht must either be operable in a
`
`normal PCI mode or in a non-standard real-time/multimedia mode optimized for
`
`multimedia transfers, but that the PCI bus cannot simultaneously support both
`
`modes of operation. [Lambrecht, 27:18-22]. A POSA would further appreciate
`
`that the non-standard real-time/multimedia mode is used only for periodic
`
`20
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`multimedia data and the normal PCI mode is utilized for addressing and control
`
`data. [Lambrecht, 26:56-60; 27:57-62; 27:66-28:11; 28:15-19].
`
`45. The only devices in Figure 21 that are equipped with the interface
`
`logic (966) of the bus interface circuitry (962) are the multimedia devices 142D,
`
`144D, and 146D. [Lambrecht, Figure 22; 27:32-42]. Therefore, one of ordinary
`
`skill in the art would recognize that only the multimedia devices (142D, 144D,
`
`146D) are equipped to utilize the “multimedia mode” of the PCI Expansion Bus
`
`(120). The main memory (110) is not equipped with the interface logic (966) of
`
`the bus interface circuitry (962) nor is the PCI bridge chipset (106). This further
`
`underscores the fact that the multimedia mode of the PCI Expansion (120) can
`
`only be used for data transmission between the multimedia devices (142D,
`
`144D, 146D), not between the multimedia device (144D) (alleged decoder) and
`
`the main memory (110) (alleged memory).
`
`2) Lambrecht does not disclose “a decoder that requires access to the
`memory sufficient to maintain real time operation” [Independent
`claim 1]
`46. The Petition identifies the multimedia device (144D) as the
`
`decoder; the PCI expansion bus (120) as the shared bus, and the main memory
`
`(110) as the memory. [Pet. at 11, 16]. The alleged decoder (144D) does not have
`
`the capability to maintain real time operation while also accessing the alleged
`
`21
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`main memory (110). As discussed in Section IX.A.1), supra, Lambrecht does
`
`not disclose a bus that would allow the alleged decoder (144D) to access the
`
`alleged main memory (110) in real time.
`
`47.
`
`In fact, Lambrecht contemplates multimedia devices that contain
`
`dedicated multimedia memory. [See, e.g., Lambrecht Figs. 15 & 16 and related
`
`text]. The multimedia devices have access to this dedicated multimedia memory
`
`(160) in real time through the multimedia/real-time bus. [Lambrecht, 20:57-65
`
`(“In one embodiment, devices use the PCI bus 120 for arbitration, addressing
`
`and setup, and devices use the multimedia or real-time bus 130 for high speed
`
`data transfers between each other and also to/from the multimedia memory 160.
`
`Thus, in one embodiment, devices use the PCI bus 120 to provide addressing
`
`and control signa
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