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`UNITED STATES PATENT AND TRADEMARK OFFICE
`______________________________
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`______________________________
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`APPLE INC., HTC CORPORATION, and HTC AMERICA, INC.
`Petitioners,
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`v.
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`PARTHENON UNIFIED MEMORY ARCHITECTURE LLC,
`Patent Owner
`______________________________
`
`
`Case IPR2016-009231
`U.S. Patent 5,812,789
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`PATENT OWNER’S NOTICE OF APPEAL
`35 U.S. § 142 & 37 C.F.R. § 90.2
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`1 Case IPR2016-00847 has been joined with this proceeding.
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`Pursuant to 37 C.F. R. § 90.2(a), Patent Owner, PARTHENON UNIFIED
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`MEMORY ARCHITECTURE LLC, hereby provides notice of its appeal to the
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`United States Court of Appeals for the Federal Circuit for review of the Final Written
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`Decision of the United States Patent and Trademark Office (“USPTO”) Patent Trial
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`and Appeals Board (“PTAB”) in Inter Partes Review 2016-00923, concerning U.S.
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`Patent 5,812,789 (“the ’789 patent”), entered on August 4, 2017, attached hereto as
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`Appendix A.
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`ISSUES TO BE ADDRESSED ON APPEAL
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` A. Whether the PTAB erred in finding that claims 1, 3, 5, 11, and 13 of
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` the ’789 patent are unpatentable as anticipated by Lambrecht under
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` §102(e)?
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` B. Whether the PTAB erred in picking, choosing, and combining various
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` disclosures of Lambrecht that are not directly related to each other to
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` support its anticipation finding?
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` C. Whether the PTAB erred in concluding that claims 4 and 6 of the ‘789
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` patent would have been obvious under 35 U.S.C. § 103(a)?
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` D. Whether the PTAB in its final written decision improperly relied upon
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` arguments that were raised for the first time at the oral argument and/or
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` in the Petitioner’s reply?
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`Simultaneous with submission of this Notice of Appeal to the Director of the
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`United States Patent and Trademark Office, this Notice of Appeal is being filed with
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`the Patent Trial and Appeal Board. In addition, this Notice of Appeal, along with the
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`required docketing fees, is being filed with the United States Court of Appeals for
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`the Federal Circuit.
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`Respectfully submitted,
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`Masood Anjom
`Reg. No. 62,167
`AHMAD, ZAVITSANOS, ANAIPAKOS,
`ALAVI &MENSING, P.C.
`1221 McKinney Street, Suite 2500
`Houston, TX 77010
`Telephone: 713-655-1101
`manjom@azalaw.com
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`
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`Dated: September 28, 2017 /s/ Gregory J. Gonsalves
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`Dr. Gregory Gonsalves
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`Reg. No. 43,639
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`2216 Beacon Lane
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`Falls Church, Virginia 22043
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`gonsalves@gonsalveslawfirm.com
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`CERTIFICATE OF SERVICE
`The undersigned certifies that in addition to being filed electronically through
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`the Patent Trial and Appeal Board’s Patent Review Processing System the foregoing
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`PATENT OWNER’S NOTICE OF APPEAL was served on the Director of the
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`United States Patent and Trademark Office, at the following address (in accordance
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`with 37 C.F.R. §§ 90.2(a), 104.2):
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`Director of the United States Patent and Trademark Office
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`c/o Office of the General Counsel
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`United States Patent and Trademark Office
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`P.O. Box 1450 Alexandria, Virginia 22313-1450
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`CERTIFICATE OF FILING
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`The undersigned certifies that on September 28, 2017, a true and correct copy
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`of the foregoing PATENT OWNER’S NOTICE OF APPEAL was filed
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`electronically with the Clerk’s Office of the United States Court of Appeals for the
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`Federal Circuit at the following address:
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`Clerk of Court
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`United States Court of Appeals for the Federal Circuit
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`717 Madison Place NW
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`Washington, DC 20005
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`3
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`CERTIFICATE OF SERVICE
`The undersigned hereby certifies that a copy of the foregoing PATENT
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`OWNER’S NOTICE OF APPEAL was served on September 28, 2017, by filing this
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`document though the PTAB’s E2E system as well as by delivering a copy via
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`electronic mail to the attorneys of record for the Petitioners as follows:
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`Lead Counsel for Apple, Inc.
`Andrew S. Ehmke
`HAYNES AND BOONE, LLP
`2323 Victory Avenue, Suite 700
`Dallas, TX 75219
`Email:
`andy.ehmke.ipr@haynesboone.com
`
`Lead Counsel for HTC Corporation
`Joseph A. Micallef
`Sidley Austin LLP
`1501 K Street, N.W.
`Washington, DC 20005
`Tel: (202) 736-8492
`Email: jmicallef@sidley.com
`
`
`
`Back-up Counsel for Apple, Inc.
`David W. O’Brien
`Michael S. Parsons
`HAYNES AND BOONE, LLP
`2323 Victory Avenue, Suite 700
`Dallas, TX 75219
`Email:
`david.obrien.ipr@haynesboone.com
`michael.parsons.ipr@haynesboone.com
`
`David L. Alberti
`Feinberg Day Alberti & Thompson
`LLP
`1600 El Camino Real, Suite 280
`Menlo Park, CA 94025
`Email: dalberti@feinday.com
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`Back-up Counsel for HTC Corporation
`Samuel A. Dillon
`Sidley Austin LLP
`1501 K Street, N.W.
`Washington, DC 20005
`Email: samuel.dillon@sidley.com
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`Curt Holbreich
`Sidley Austin LLP
`555 California Street, Suite 2000
`San Francisco, CA 94104
`Email: cholbreich@sidley.com
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`Dated: September 28, 2017 /s/ Gregory J. Gonsalves
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`Dr. Gregory Gonsalves
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`Reg. No. 43,639
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`2216 Beacon Lane
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`Falls Church, Virginia 22043
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`(571) 419-7252
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`gonsalves@gonsalveslawfirm.com
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`Masood Anjom
`Reg. No. 62,167
`AHMAD, ZAVITSANOS, ANAIPAKOS,
`ALAVI &MENSING, P.C.
`1221 McKinney Street, Suite 2500
`Houston, TX 77010
`Telephone: 713-655-1101
`manjom@azalaw.com
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`5
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`Appendix A
`Appendix A
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` 7
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`Trials@uspto.gov
`571-272-7822
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` Paper 39
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`Entered: August 4, 2017
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`____________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`____________
`
`APPLE INC., HTC CORP., and HTC AMERICA, INC.,
`Petitioners,
`
`v.
`
`PARTHENON UNIFIED MEMORY ARCHITECTURE LLC,
`Patent Owner.
`____________
`
`Case IPR2016-009231
`Patent 5,812,789
`____________
`
`
`
`Before MICHAEL R. ZECHER, JAMES B. ARPIN, and
`MATTHEW R. CLEMENTS, Administrative Patent Judges.
`
`ZECHER, Administrative Patent Judge.
`
`
`
`
`FINAL WRITTEN DECISION
`Inter Partes Review
`35 U.S.C. § 318(a) and 37 C.F.R. § 42.73
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`
`
`1 Case IPR2016-00847 has been joined with this proceeding.
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`
`
`IPR2016-00923
`Patent 5,812,789
`
`
`
`
`I. BACKGROUND
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`Apple Inc. (“Apple”) filed a Petition requesting an inter partes review
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`of claims 1, 3–6, 11, and 13 (“the challenged claims”) of U.S. Patent No.
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`5,812,789 (Ex. 1001, “the ’789 patent”). Paper 2 (“Pet.”). Patent Owner,
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`Parthenon Unified Memory Architecture Limited Liability Corp., waived its
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`right to file a Preliminary Response. Paper 8. We determined that the
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`information presented in the Petition established that there was a reasonable
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`likelihood that Apple would prevail in challenging claims 1, 3, 5, 11, and 13
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`of the ’789 patent as unpatentable under 35 U.S.C. § 102(e), and claims 4
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`and 6 of the ’789 patent as unpatentable under 35 U.S.C. § 103(a). Pursuant
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`to 35 U.S.C. § 314, we instituted this inter partes review on August 23,
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`2016, as to all the challenged claims. Paper 10 (“Dec. on Inst.”).
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`Upon instituting this proceeding, we considered a Petition filed by
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`HTC Corp., HTC America, Inc., and LG Electronics, Inc. in Case IPR2016-
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`00847 that challenged the same claims of the ’789 patent at issue in this
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`proceeding based on the same grounds of unpatentability. The Petition in
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`Case IPR2016-00847 was accompanied by a Motion for Joinder that
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`requested we join HTC Corp., HTC America, Inc., and LG Electronics, Inc.
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`as parties to Case IPR2015-01944, which also challenged the same claims of
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`the ’789 patent at issue in this proceeding based on the same grounds of
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`unpatentability. HTC Corp. v. Parthenon Unified Memory Architecture
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`LLC, Case IPR2016-00847 (PTAB Apr. 7, 2016) (Papers 1 and 2). Based
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`on a joint request by the parties in Case IPR2015-01944, we terminated that
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`proceeding. Samsung Elecs. Co. v. Parthenon Unified Memory Architecture
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`LLC, Case IPR2015-01944 (PTAB May 25, 2016) (Paper 12). We,
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`nonetheless, authorized HTC Corp., HTC America, Inc., and LG
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`2
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`IPR2016-00923
`Patent 5,812,789
`
`Electronics, Inc. to file a renewed or second motion for joinder seeking to
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`join this proceeding. Case IPR2016-00847, Paper 11. Shortly thereafter,
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`HTC Corp., HTC America, Inc., and LG Electronics, Inc. filed a Second
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`Motion for Joinder. Case IPR2016-00847, Paper 12. Based on a joint
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`request between LG Electronics, Inc. and Patent Owner, we terminated Case
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`IPR2016-00847 only as to LG Electronics, Inc. Case IPR2016-00847,
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`Paper 15. Pursuant to § 314(a), we instituted another inter partes review
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`proceeding as to claims 1, 3–6, 11, and 13 of the ’789 patent, and granted
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`the Second Motion for Joinder only as to HTC Corp. and HTC America, Inc.
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`(collectively, “HTC”). Paper 12.
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`During the course of trial, Patent Owner filed a Patent Owner
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`Response. Paper 22 (“PO Resp.”). Apple and HTC (collectively,
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`“Petitioners”) jointly filed a Reply to the Patent Owner Response. Paper 27
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`(“Pet. Reply”). A consolidated oral hearing with Case IPR2016-00924 was
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`held on May 18, 2017, and a transcript of the hearing is included in the
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`record. Paper 38 (“Tr.”).
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`We have jurisdiction under 35 U.S.C. § 6. This decision is a Final
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`Written Decision under 35 U.S.C. § 318(a) as to the patentability of
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`claims 1, 3–6, 11, and 13 of the ’789 patent. For the reasons discussed
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`below, we hold that Petitioners have demonstrated by a preponderance of the
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`evidence that claims 1, 3, 5, 11, and 13 of the ’789 patent are unpatentable
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`under § 102(e), and claims 4 and 6 of the ’789 patent are unpatentable
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`under § 103(a).
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`A. Related Matters
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`According to the parties, the ’789 patent is involved in the following
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`ten district court cases: (1) Parthenon Unified Memory Architecture LLC v.
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`3
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`IPR2016-00923
`Patent 5,812,789
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`LG Electronics MobileComm, USA, No. 2:15-cv-01950 (E.D. Tex.);
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`(2) Parthenon Unified Memory Architecture LLC v. Huawei Techs. Co.,
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`No. 2:14-cv-00687-JRG-RSP (E.D. Tex.); (3) Parthenon Unified Memory
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`Architecture LLC v. Motorola Mobility, Inc., No. 2:14-cv-00689-JRG-RSP
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`(E.D. Tex.); (4) Parthenon Unified Memory Architecture LLC v. HTC Corp.,
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`No. 2:14-cv-00690-RSP (E.D. Tex.); (5) Parthenon Unified Memory
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`Architecture LLC v. LG Electronics, Inc., No. 2:14-cv-00691-JRG-RSP
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`(E.D. Tex.); (6) Parthenon Unified Memory Architecture LLC v. Samsung
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`Electronics Co., No. 2:14-cv-00902-JRG-RSP (E.D. Tex.); (7) Parthenon
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`Unified Memory Architecture LLC v. Qualcomm Inc., No. 2:14-cv-00930-
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`JRG-RSP (E.D. Tex.); (8) Parthenon Unified Memory Architecture LLC v.
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`ZTE Corp., No. 2:15-cv-00225-JRG-RSP (E.D. Tex.); (9) Parthenon Unified
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`Memory Architecture LLC v. Apple, Inc., No. 2:15-cv-00621-JRG-RSP
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`(E.D. Tex.); and (10) STMicroelectronics, Inc. v. Motorola Inc., No. 4:03-
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`cv-00276-LED (E.D. Tex.). Pet. 1–2;2 Paper 32, 2. Petitioners also filed
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`other petitions challenging the patentability of a certain subset of claims in
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`related U.S. Patent No. 5,960,464 (Case IPR2016-00924).
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`B. The ’789 Patent
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`The ’789 patent, titled “Video and/or Audio Decompression and/or
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`Compression Device That Shares a Memory Interface,” issued September
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`
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`2 The Petition and supporting evidence filed by HTC in Case IPR2016-
`00847 are essentially the same as the Petition and supporting evidence filed
`by Apple in Case IPR2016-00923. For clarity and ease of reference, all
`references to the Petition and supporting evidence throughout this Final
`Written Decision are to the Petition and supporting evidence filed by Apple
`in Case IPR2016-00923.
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`4
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`IPR2016-00923
`Patent 5,812,789
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`22, 1998, from U.S. Patent Application No. 08/702,911, filed on August 26,
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`1996. Ex. 1001, at [54], [45], [21], [22]. Because the application that led to
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`the ’789 patent was filed August 26, 1996, the ’789 patent expired on
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`August 26, 2016.
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`The ’789 patent generally relates to an electronic system having a
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`video or audio decompression/compression device and, in particular, to
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`sharing a memory interface between such a device and another device in the
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`electronic system. Ex. 1001, 1:18–23. In the Background section, the ’789
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`patent discloses advantages associated with using encoders and decoders to
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`compress and decompress video and audio sequences, respectively. Id. at
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`1:32–2:3. The ’789 patent then proceeds to disclose the architecture of a
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`conventional encoder/decoder prior to asserting that there are a number of
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`problems associated with such an architecture. Id. at 2:4–25, Figs. 1a, 1b.
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`According to the ’789 patent, one of the problems includes dedicating
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`memory to both the encoder and decoder, thereby increasing the cost of
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`adding these components to an electronic system. Id. at 2:29–37.
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`The ’789 patent purportedly solves this problem because the disclosed
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`video or audio decompression/compression device does not need its own
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`dedicated memory, but instead may share memory with another device and
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`still operate in real time. Ex. 1001, 4:30–34. Figure 2 of the ’789 patent,
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`reproduced below, illustrates a diagram of an electronic system containing a
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`device having a memory interface, as well as an encoder and decoder. Id. at
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`5:1–3.
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`5
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`IPR2016-00923
`Patent 5,812,789
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`As shown in Figure 2 above, electronic system 40 includes first device
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`42, decoder 44, encoder 46, memory interface 48, and memory 50.
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`Ex. 1001, 5:23–26. Each of first device 42, decoder 44, and encoder 46
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`access memory 50 through memory interface 48. Id. at 5:15–19. Memory
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`interface 48 further includes arbiter 54 that is configured to arbitrate between
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`first device 42, decoder 44, and encoder 46, when these components request
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`access to memory 50. Id. at 6:15–18, 9:43–49.
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`C. Illustrative Claim
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`
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`Of the challenged claims, claim 1 is independent. Independent claim
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`1 is directed to an electronic system coupled to a memory. Each of claims
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`3–6, 11, and 13 directly or indirectly depends from independent claim 1.
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`Independent claim 1 is illustrative of the challenged claims and is
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`reproduced below:
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`1.
`comprising:
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`An electronic system coupled to a memory,
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`a first device that requires access to the memory;
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`a decoder that requires access to the memory sufficient to
`maintain real time operation; and
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`a memory interface for coupling to the memory, and
`coupled to the first device and to the decoder, the memory
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`6
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`IPR2016-00923
`Patent 5,812,789
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`interface having an arbiter for selectively providing access for
`the first device and the decoder to the memory and a shared bus
`coupled to the memory the first device, and the decoder, the bus
`having a sufficient bandwidth to enable the decoder to access the
`memory and operate in real time when the first device
`simultaneously accesses the bus.
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`Ex. 1001, 12:29–41.
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`D. Prior Art Relied Upon
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`Petitioners rely upon the following prior art references:
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`Inventor
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`U.S. Patent No. Relevant Dates
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`Exhibit No.
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`Artieri
`
`Lambrecht
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`5,579,052
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`5,682,484
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`issued Nov. 26, 1996,
`filed May 24, 1994
`issued Oct. 28, 1997,
`filed Nov. 20, 1995
`
`1036
`
`1032
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`
`
`
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`Non-Patent Literature
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`Gordon E. Moore, Cramming more components onto
`integrated circuits, 38 ELECTRONICS (1965) (“Moore”)
`
`Exhibit No.
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`1035
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`E. Instituted Grounds of Unpatentability
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`We instituted a trial based on the asserted grounds of unpatentability
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`(“grounds”) set forth in the table below. Dec. on Inst. 18.
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`Reference(s)
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`Lambrecht
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`Basis
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`Claim(s) Challenged
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`§ 102(e) 1, 3, 5, 11, and 13
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`Lambrecht and Artieri
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`§ 103(a) 4
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`Lambrecht and Moore
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`§ 103(a) 6
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`IPR2016-00923
`Patent 5,812,789
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`II. ANALYSIS
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`A. Claim Construction
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`In an inter partes review proceeding, we generally construe claims in
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`an unexpired patent by applying the broadest reasonable interpretation in
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`light of the specification. 37 C.F.R. § 42.100(b). As we explain above,
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`however, the ’789 patent expired on August 26, 2016. Petitioners
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`acknowledge as much when they assert that the ’789 patent was set to expire
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`in August 2016. Pet. 9–10.
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`As we explained in the Decision on Institution, because the ’789
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`patent would expire shortly after we initiated this trial, we analyzed
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`Petitioners’ arguments through the lens of the claim construction standard
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`that would apply to our Final Written Decision. See Dec. on Inst. 6–8.
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`Thus, we construed the claims in accordance with the principles followed in
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`district court. See Phillips v. AWH Corp., 415 F.3d 1303, 1314 (Fed. Cir.
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`2005) (en banc); cf. In re Rambus Inc., 694 F.3d 42, 46 (Fed. Cir. 2012)
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`(“While claims are generally given their broadest possible scope during
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`prosecution, the Board’s review of the claims of an expired patent is similar
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`to that of a district court’s review.” (citation omitted)).
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`“In determining the meaning of the disputed claim limitation, we look
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`principally to the intrinsic evidence of record, examining the claim language
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`itself, the written description, and the prosecution history, if in evidence.”
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`DePuy Spine, Inc. v. Medtronic Sofamor Danek, Inc., 469 F.3d 1005, 1014
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`(Fed. Cir. 2006) (citing Phillips, 415 F.3d at 1312–17). The words of a
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`claim generally are given their ordinary and customary meaning, and that is
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`the meaning the term would have to a person of ordinary skill at the time of
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`the invention, in the context of the entire patent, including the specification.
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`8
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`IPR2016-00923
`Patent 5,812,789
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`See Phillips, 415 F.3d at 1312–13. Claims are not interpreted in a vacuum,
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`but are a part of, and are read in light of, the specification. See Slimfold Mfg.
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`Co. v. Kinkead Indus., Inc., 810 F.2d 1113, 1116 (Fed. Cir. 1987). Although
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`it is improper to read a limitation from the specification into the claims, the
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`claims still must be read in view of the specification of which they are a part.
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`See Microsoft Corp. v. Multi-Tech Sys., Inc., 357 F.3d 1340, 1347 (Fed. Cir.
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`2004).
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`In the Decision on Institution, we addressed Petitioners’ proposed
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`constructions for the following two claim terms: (1) “video decoder” (claim
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`3); and (2) “real time” (all challenged claims). Dec. on Inst. 8–11. Upon
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`reviewing the ’789 patent in its entirety, we construed these claim terms as
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`follows:
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`Claim Term
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`Construction
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`“real time”
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`“video decoder” “hardware and/or software that translates data streams
`into video information”
`“[p]ertaining to a data-processing system that controls
`an ongoing process and delivers its outputs (or controls
`its inputs) not later than the time when these are needed
`for effective control”
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`In its Patent Owner Response, Patent Owner does not address separately our
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`initial constructions of these claim terms. See Paper 11, 3 (“The patent
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`owner is cautioned that any arguments for patentability not raised in the
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`response will be deemed waived.”). Nor do Petitioners address our
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`determinations in this regard in their Reply. See 37 C.F.R. § 42.23(b) (“A
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`reply may only respond to arguments raised in the corresponding . . . patent
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`owner response.”). We, therefore, discern no reason to address or alter our
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`initial construction of the claim terms “video decoder” and “real time” for
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`the purposes of this Final Written Decision.
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`9
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`Patent 5,812,789
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`B. Anticipation by Lambrecht
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`
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`Petitioners contend that claims 1, 3, 5, 11, and 13 of the ’789 patent
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`are anticipated under § 102(e) by Lambrecht. Pet. 10–23. Petitioners
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`explain how Lambrecht purportedly describes the subject matter of each
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`challenged claim (id.), and rely upon the Declarations of Harold S. Stone,
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`Ph.D. (Ex. 1030 ¶¶ 78–82; Ex. 1044 ¶¶ 2–20) to support their positions. In
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`its Patent Owner Response, Patent Owner presents four arguments with
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`respect to independent claim 1. PO Resp. 5–24. Patent Owner relies upon
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`the Declaration of Mitchell A. Thornton, Ph.D., P.E., to support its positions.
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`Ex. 2003 ¶¶ 39–60.
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`We begin our analysis with the principles of law that generally apply
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`to a ground based on anticipation, followed by a brief overview of
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`Lambrecht, and then we address the parties’ contentions with respect to
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`independent claim 1.
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`1. Principles of Law
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`To establish anticipation, “all of the elements and limitations of the
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`claim must be shown in a single prior reference, arranged as in the claim.”
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`Karsten Mfg. Corp. v. Cleveland Golf Co., 242 F.3d 1376, 1383 (Fed. Cir.
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`2001). When evaluating a single prior art reference in the context of
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`anticipation, the reference must be “considered together with the knowledge
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`of one of ordinary skill in the pertinent art.” In re Paulsen, 30 F.3d 1475,
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`1480 (Fed. Cir. 1994) (citing In re Samour, 571 F.2d 559, 562 (CCPA
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`1978)). “‘[T]he dispositive question regarding anticipation[, therefore, i]s
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`whether one skilled in the art would reasonably understand or infer from the
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`[prior art reference’s] teaching’ that every claim element was disclosed in
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`that single reference.” Dayco Prods., Inc. v. Total Containment, Inc., 329
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`10
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`IPR2016-00923
`Patent 5,812,789
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`F.3d 1358, 1368 (Fed. Cir. 2003) (alterations in original) (quoting In re
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`Baxter Travenol Labs., 952 F.2d 388, 390 (Fed. Cir. 1991)). We analyze
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`this asserted ground based on anticipation with the principles stated above in
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`mind.
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`2. Lambrecht Overview
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`Lambrecht generally relates to a computer system that includes a
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`system expansion bus, such as the Peripheral Component Interconnect
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`(“PCI”) bus, as well as a real time or multimedia bus that transfers periodic
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`and/or multimedia data for real time, multimedia applications in order to
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`increase system performance. Ex. 1032, 1:8–13. Figure 21 of Lambrecht,
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`reproduced below, illustrates one embodiment of a computer system having
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`a PCI bus that operates in different modes, one of which is a multimedia
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`mode for high speed multimedia transfers. Id. at 6:59–61, 26:48–51.
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`As shown in Figure 21, the computer system includes central
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`processing unit (“CPU”) 102 coupled through CPU local bus 104 to PCI
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`bridge chipset 106. Ex. 1032, 26:64–66. PCI bridge chipset 106 further
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`includes various bridge logic, peripheral logic, arbitration logic 107, and
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`mode logic 960. Id. at 26:66–27:3. PCI bridge chipset 106 is coupled to
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`main memory 110 through memory bus 108. Id. at 27:4–5. Main memory
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`11
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`IPR2016-00923
`Patent 5,812,789
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`110 is preferably a dynamic random access memory, an extended data out
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`memory, or other type of memory, as desired. Id. at 27:5–8. PCI bridge
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`chipset 106 also interfaces with PCI bus 120 and uses mode logic 960 to
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`place PCI bus 120 in either a normal PCI mode or in a real-time/multimedia
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`mode optimized for multimedia transfers of periodic data. Id. at 27:10–11,
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`27:19–22. In this particular embodiment, multimedia bus 130 (not
`
`illustrated in Figure 21) optionally may augment or supplement PCI bus 120
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`when it is placed in multimedia mode. Id. at 27:29–31; see also id. at
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`27:62–65 (disclosing the same).
`
`As further shown in Figure 21, one or more multimedia devices
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`142D–146D are coupled to PCI bus 120 and multimedia bus 130. Ex. 1032,
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`27:32–34. Multimedia devices 142D–146D are similar to multimedia
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`devices 142–146 illustrated Figure 1 and may include, among other things,
`
`encoder or decoder devices. Id. at 27:43–50; see also id. at 8:13–19
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`(disclosing that various types of devices that may constitute multimedia
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`devices 142–146 illustrated in Figure 1).
`
`3. Level of Skill in the Art
`
`There is evidence in the record before us that enables us to determine
`
`the knowledge level of a person of ordinary skill in the art. Relying on the
`
`testimony of its declarant, Dr. Stone, Petitioners assert that a person of
`
`ordinary skill in the art at the time of the invention of the ’789 patent would
`
`be an individual who possesses (1) an accredited Bachelor’s degree in
`
`electrical engineering, computer science, or computer engineering; and (2) at
`
`least three years of experience in the fields of data compression and overall
`
`computer system architecture. Pet. 10 (citing Ex. 1030 ¶¶ 74–77). Patent
`
`Owner’s declarant, Dr. Thornton, testifies that a person of ordinary skill in
`
`12
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`IPR2016-00923
`Patent 5,812,789
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`the art at the time of the invention of the ’789 patent would be an individual
`
`who possesses (1) an accredited Bachelor’s degree in electrical engineering,
`
`computer engineering, or an equivalent degree; and (2) at least two to three
`
`years of experience in signal/image processing and computer architecture at
`
`both the systems and micro-architecture levels. Ex. 2003 ¶ 27. In lieu of the
`
`two to three years of experience, Dr. Thornton testifies that a person of
`
`ordinary skill in the art at the time of the invention of the ’789 patent may
`
`hold a Master’s or other graduate degree in electrical or computer
`
`engineering with a focus in computer architecture and signal/image
`
`processing, along with one year of relevant experience. Id.
`
`Putting aside the subtle distinctions in the assessments of the level of
`
`skill in the art put forth by both declarants, Dr. Thornton testifies that, if he
`
`were to apply Dr. Stone’s assessment of the level of skill in the art, his
`
`“analysis and conclusions would remain unchanged.” Ex. 2003 ¶ 28.
`
`Because Dr. Stone’s assessment of the level of skill in the art is consistent
`
`with the ’789 patent and the asserted prior art, we adopt it and apply it to our
`
`evaluation below, but note that our conclusions would remain the same
`
`under Dr. Thornton’s assessment.
`
`4. Claim 1
`
`In their Petitions, Petitioners rely upon the computer system in Figure
`
`21 of Lambrecht to account for all the features required by independent
`
`claim 1. Pet. 10–19. An annotated version of Lambrecht’s Figure 21 with
`
`Petitioners’ corresponding claim mapping is reproduced below.
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`13
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`IPR2016-00923
`Patent 5,812,789
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`Pet. 16; Pet. Reply 4. As shown in this annotated version of Lambrecht’s
`
`Figure 21 above, Petitioners rely upon main memory 110, multimedia device
`
`142D, multimedia device 144D, PCI bridge chipset 106, and PCI bus 120 to
`
`account for the shared “memory,” “first device,” “decoder,” “memory
`
`interface,” and “shared bus,” respectively, as recited in independent claim 1.
`
`Pet. 12–19.
`
`Petitioners then argue that Lambrecht discloses “a first device that
`
`requires access to memory” because multimedia device 142D accesses main
`
`memory 110 via PCI bus 120. Pet. 12–13 (citing Ex. 1032, 27:4–9,
`
`27:32–34, 27:43–59; Ex. 1030 ¶ 78). Petitioners further argue that
`
`Lambrecht discloses “a decoder that requires access to the memory
`
`sufficient to maintain real time operation” because, when Lambrecht’s PCI
`
`bus 120 is placed in multimedia mode, it allows multimedia device 144D
`
`sufficient access to main memory 110 in order to maintain real time
`
`operation. Id. at 13–14 (citing Ex. 1032, 27:32–34, 27:43–59; 27:66–28:2;
`
`Ex. 1030 ¶ 78). In addition, Petitioners argue that Lambrecht discloses “a
`
`memory interface for coupling to the memory, and coupled to the first
`
`device and to the decoder, the memory interface having an arbiter for
`
`selectively providing access for the first device and the decoder to memory,”
`
`14
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`IPR2016-00923
`Patent 5,812,789
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`because PCI bridge chipset 106 includes arbitration logic 107 that
`
`selectively provides multimedia devices 142D and 144D access to (shared)
`
`main memory 110. Id. at 15–17 (citing Ex. 1032, 7:30–47, 26:66–27:9;
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`Ex. 1030 ¶ 78).
`
`Lastly, Petitioners argue that Lambrecht’s PCI bus 120 describes the
`
`claimed “shared bus” because it is of “sufficient bandwidth to enable the
`
`decoder to access the memory and operate in real time when the first device
`
`simultaneously accesses the bus.” Pet. 17 (citing Ex. 1032, 5:33–48,
`
`27:66–28:11; Ex. 1030 ¶ 78). According to Petitioners, Lambrecht’s PCI
`
`bus 120 operates in a version of the multimedia mode called special “byte
`
`sliced mode,” which allows for simultaneous, real time video and audio
`
`transfers and, as a result, provides sufficient bandwidth for both multimedia
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`devices 142D and 144D to access (shared) main memory 110
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`simultaneously. Id. at 17–19 (citing Ex. 1032, 5:17–48, 19:39–54,
`
`26:48–63, 27:66–28:11; Ex. 1030 ¶ 78).
`
`In its Patent Owner Response, Patent Owner presents the following
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`four arguments: (1) Lambrecht does not disclose “a shared bus . . . having a
`
`sufficient bandwidth to enable the decoder to access the memory and operate
`
`in real time”; (2) Lambrecht does not disclose “a decoder that requires
`
`access to the memory sufficient to maintain real time operation”;
`
`(3) Lambrecht does not disclose “a shared bus . . . having a sufficient
`
`bandwidth to enable the decoder to access the memory and operate in real
`
`time”; and (4) Lambrecht does not disclose “the bus having a sufficient
`
`bandwidth to enable the decoder to access the memory and operate in real
`
`time when the first device simultaneously accesses the bus.” PO Resp. 6–24
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`15
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`IPR2016-00923
`Patent 5,812,789
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`(emphasis added by Patent Owner). We group Patent Owner’s first and third
`
`arguments identified above and then address these arguments in turn.
`
`a. Lambrecht discloses “a shared bus . . . having a sufficient bandwidth to
`enable the decoder to access the memory and operate in real time,” as
`recited in independent claim 1
`
`Independent claim 1 recites, in relevant part, “a shared bus . . . having
`
`a sufficient bandwidth to enable the decoder to access memory and operate
`
`in real time.” Ex. 1001, 12:37–40.
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`In their Petitions, Petitioners contend that Lambrecht’s PCI bus 120
`
`describes the claimed “shared bus” because it is of “sufficient bandwidth to
`
`enable the decoder to access the memory and operate in real time.” Pet. 17
`
`(citing Ex. 1032, 5:33–48, 27:66–28:11; Ex. 1030 ¶ 78). According to
`
`Petitioners, Lambrecht’s PCI bus 120 operates in a version of the
`
`multimedia mode called special “byte sliced mode,” which allows for
`
`simultaneous, real time video and audio transfers and, as a result, provides
`
`sufficient bandwidth for both multimedia devices 142D and 144D to access
`
`(shared) main memory 110 simultaneously. Id. at 17–19 (citing Ex. 1032,
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`5:17–48, 19:39–54, 26:48–63, 27:66–28:11; Ex. 1030 ¶ 78); see also id. at
`
`13–14 (arguing that, when Lambrecht’s PCI bus 120 is placed in multimedia
`
`mode, it allows multimedia devices 142D and 144D sufficient access to
`
`main memory 110 in order to maintain real time operation) (citing Ex. 1032,
`
`27:32–34, 27:43–59; 27:66–28:2; Ex. 1030 ¶ 78).
`
`In its Patent Owner Response, Patent Owner’s first and third
`
`arguments as to why Lambrecht does not disclose this disputed limitation
`
`presents the following layers of complexity: (1) whether Lambrecht
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`discloses that multimedia device 144D is capable of accessing main memory
`
`110 when PCI bus 120 is placed in multimedia mode; and (2) even assuming
`
`16
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`IPR2016-00923
`Patent 5,812,789
`
`Lambrecht discloses that multimedia device 144D is capable of accessing
`
`main memory 110 when PCI bus 120 is placed in multimedia mode, whether
`
`Lambrecht discloses that such access enables the multimedia device 144D to
`
`operate in real time. PO Resp. 6–13, 15–21. We address each in turn.
`
`i. Lambrecht’s multimedia device 144D is capable of accessing
`main memory 110 when PCI bus 120 is placed in multimedia mode
`
`Patent Owner contends that, when Lambrecht’s PCI bus 120 is placed
`
`in multimedia mode, it does not enable multimedia device 144D to access
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`main memory 110. PO Resp. 6. According to Patent Owner, because the
`
`computer system illustrated in Lambrecht’s Figure 21 is similar to the
`
`computer system illustrated in Lambrecht’s Figure 1, one of ordinary skill in
`
`the art would have understood that these computer systems essentially
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`operate in the same way. Id. at 7–8 (citing Ex. 2003 ¶ 41). Patent
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