United States Patent
`Artieri
`Nov. 26, 1996
`[45] Date of Patent:
`
`{I11 Patent Number:
`
`5,579,052
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`[19]
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`||||l|l||||||||l|llllIlllllllll|||||lllllllllllllllIllllllllllllllllllllll
`USO0SS79052A
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`[54] PICTURE PROCESSING SYSTEM
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`[T5]
`
`Inventor: Alain Arlieri, Meylan, France
`
`[73] Assignee: SGS-Thomson Microelectronics S.A.,
`Saint Genis Pouill y, France
`
`[21] Appl. No; 247,996
`
`[22]
`
`Filed:
`
`May 24, 1994
`
`[30]
`
`Foreign Application Priority Data
`
`May 2?, 1993
`Oct. 29, I993
`
`[FR]
`[FR]
`
`France ................................... 93 06612
`France ................................. .. 93 13293
`
`Int. Cl.“ .............................. .. H04N 7:30; H{}4N 7:32
`[51]
`[52] U.S. Cl.
`....... ..
`3481416
`
`[58] Field of Search ................................... .. 348F416, 699;
`382156, 43; 375E245, 246, 253; J-l{l4N TU30,
`7132
`
`[561
`
`References Cited
`
`U.S. PATENT DOCUNTENTS
`
`4,800,441 M989 Fumitaka Sate ................... .. 3581261.]
`5.253.078
`1031993 Balkanski etai.
`348!-416
`5,379,356
`H1995 Purcell cl al.
`.......................... .. 332.56
`
`FOREIGN PATENT DOCUMENTS
`
`3545106
`
`611987 Germany ...................... .. G{}6F 15168
`
`OTHER PUBLICATIONS
`
`Digital Image Processing Applications, Los Angeles, CA.
`Jan. 17-20, 1989, 140-147, Yusheng. T. Tsai, “Real—timc
`architecture for crror—tolerant color picture cornprc.ssion~
`
`24
`
`."IEEE Colloquim on Parallel Architectures for Image Pro-
`cessing Applications, Digest No. 086, London, UK, Apr. 22,
`1991, M. N. Chong, et al., “Pipeline Functional Algorithms,
`Data Partitioning for Adaptive Transform Coding Algo-
`rithrns.'"‘A One Chip VLSI for Real Time Two—Dimensional
`Discrete Losine", Circuits & Systems, 1988 IEEE Internal
`Sypos, Artieri et al, pp. 701-704.
`"A Realtime Image Processing Chip Set", Solid State Cir-
`cuits, 1989 36th Conference, IEEE.
`“Designing a I-ligh-Throughput VLC Decoder Parts [—II-
`——Parallel Decoding Methods", Lin ct al, IEEE Trans. in
`Circuits & Systems for Video technology, vol. 2, No. 2, Jun.
`1992, pp. 187-206.
`
`Primary Examt'rzer—Tommy P. Chin
`Assistant Examiner—-Vt: Le
`Attorney, Agent, or Fim:—-David M. Driscoll; James H.
`Morris; Brett N. Domy
`
`[57]
`
`ABSTRACT
`
`A system that processes compressed data arriving in packets
`corresponding to picture blocks, the packets being separated
`by headers containing decoding parameters of the packets. A
`memory bus is controlled by a memory controller
`to
`exchange data between the processing elements and a pic-
`ture memory. A pipeline circuit contains a plurality of
`processing elements. A parameter bus provides packets to be
`processed to the pipeline circuit, as well as the decoding
`parameters to elements of the system. The parameter bus is
`controlled by a variable length decoder that receives the
`compressed data from the memory has and that extracts the
`packets and the decoding parameters therefrom.
`
`13 Claims, 7 Drawing Sheets
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`U.S. Patent
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`Nov. 26, 1996
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`Sheet 1 of 7
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`Nov. 26, 1996
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`Nov. 26, 1996
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`U.S. Patent
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`Nov. 26, 1996
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`Sheet 6 of 7
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`U.S. Patent
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`Nov. 26, 1995
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`1
`PICTURE PROCESSING SYSTEM
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`5,579,052
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`order, with respect to the currently reconstructed picture.
`Thus, encoded pictures arrive in an order different from the
`display order.
`In addition. each predicted or bidirectional macroblock is
`of a progressive or an interlaced type. When the macro-
`block is progressive, the DCT" circuit provides the lines of
`the macro-block in successive order. When the macro-block
`is interlaced, the DCT” circuit first provides the even lines
`of the macro—hloclt, then the odd lines. In addition,
`the
`predictor macro-block that serves to decode a predicted or
`bidirectional macro-block is also of the progressive or
`interlaced-type. When the predictor macro-block is of the
`interlaced-type, it is partitioned into two half-macro—blocks;
`one half macro-block corresponds to even lines, and the
`other half macro-block corresponds to odd lines, each half
`macro-block being fetched at tlilferent positions in a same
`previously decoded picture.
`A picture is also of the intra, predicted or bidirectional
`type. An intra picture contains only intra macro-blocks; a
`predicted picture contains intra or predicted macro-blocks;
`and a bidirectional picture contains intra, predicted or bidi-
`rectional macro-blocks.
`
`To provide the various decoding parameters to the various
`circuits of the decoder, especially vectors V and the macro-
`bloclt
`types.
`the flow of encoded data includes headers.
`There are several types of headers:
`a picture sequence header that includes in particular two
`quantizer tables to provide to the inverse quantizer
`circuit 12, one serving for the intra macro-blocks of the
`sequence, and the second serving for the predicted or
`bidirectional rnacro—blocks;
`a group of picture header, that does not include useful data
`for decoding;
`a picture header that includes the type (predicted, intra,
`bidirectional) of the picture and information on the use
`of the movement compensation vectors;
`a picture slice header including error correction informa-
`tion; and
`
`a macro-block header including the macro-block's type, a
`quarttizer scale to be provided to the inverse quantizer
`circuit 12, and the components of the movement com-
`pensation vectors. Up to four vectors are provided
`when processing an interlaced bidirectional macro-
`block.
`'
`
`In addition, the high hierarchy headers (picture, group,
`sequence) can include private data serving, for example, for
`on-screen display. Some private data can also be used by
`components external to the decoder.
`The various processing circuits of an MPEG decoder are
`frequently arranged in a pipeline architecture which can
`process high data flow rates but which is very complex and
`inflexible, that is. which is diflicult to adapt to modifications
`of the standards and which is inadequate to exploit on-screen
`display and private data.
`The simplest and most inexpensive solution is to couple
`the various processing circuits to the memory through a
`common bus that is controlled by a multi—task processor.
`Patent application EP-A—0,503,956 (C-Cube) describes
`such a system including a processor that controls transfers of
`data on the bus and three coprocessors that execute the
`processing steps corresponding to circuits 10-14. Each type
`of transfer to be achieved via the bus corresponds to a task
`carried out by the processor. All tasks are concurrent and are
`executed at processor interrupts generated by the coproces-
`sors. The coprocessors exchange the data to be processed
`and receive the instructions provided by the processor via
`the bus.
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`
`The present invention relates to picture processing sys-
`tems and more particularly to a system for decoding pictures
`encoded in accordance with an MPEG standard.
`2. Discussion of the Related Art
`
`FIG. 1 represents the main elements of an MPEG decoder
`8. All MPEG decoders. especially for the MPEG-2 standard,
`generally include a variable length decoder (VLD) 10. a
`run-level decoder (RLD) 11, an inverse quarttizer circuit
`(Q4) 12. an inverse discrete cosine transform circuit (DCT’
`r} 13. a half—pixcl filter 14, and a memory 15. The encoded
`data are provided to the decoder via a bus CDin and the
`decoded data are output via a bus VIDout. Between the input
`and the output,
`the data pass through processing circuits
`10-13 in the order indicated above, which is illustrated by
`arrows in dashed lines. The decoder output is provided by an
`adder 16 that sums the outputs of filter 14 and of the cosine
`transform. circuit 13. The filter 14 needs a portion of a
`previously decoded picture stored in memory 15.
`FIG. 2A illustrates a decoding step of a portion of a
`currently reconstructed picture IM1. Picture decoding is
`carried out one macro-block at a time. A macro—block
`generally corresponds to one 16x16-pixel picture block.
`FIG. 2B illustrates an exemplary format, noted 4:2:O, of
`a macro-block MB. The macro-block MB includes a lurni-
`nance block formed by four 8x8-pixel blocks Y1—Y4 and by
`one chrominance block formed by two 8x8-pixel blocks U
`and V. An alternative format is the 4:2:2 format where the
`chrominance block includes two 8x16-pixel blocks.
`In the current picture [M1 of FIG. 2A. a current macro-
`block MBe is being decoded. the macro—bloclts that were
`previously decoded being represented by hatched lines.
`Generally. rnacro-block MBe is reconstructed by using a
`predictor macro—block MBp fetched in a previously decoded
`picture IMO. To find the predictor macro-block MBp, the
`data that serve to decode macro-block MBe provide a
`movement compensation vector V that defines the position
`of die predictor macro-block MBp with respect
`to the
`position P of macro-block M.Bc in the picture.
`The predictor macro-block MBp is fetched in the memory
`15 that stores the previously decoded picture IMO. and is
`provided to filter 14 while the cosine transform circuit 13
`processes data corresponding to the macro—block MBe.
`The decoding described above is a so-called “predicted"
`decoding. The decoded macro-block is also referred to as
`being of predicted type. In accordance with MPEG stan-
`dards, there are three main types of decoding, referred to as
`“intra", "predicted". and “bidircctional".
`An intra macro-block directly corresponds to a picture
`block, that is. the intra macro-block is not combined with a
`predictor macro-block when it is output from the cosine
`transform circuit 13.
`
`A predictor nracro—block. as described above, is combined
`with one macro—block of a previously decoded picntre, and
`that comes, in the display order. before the currently recon-
`structed picture.
`A bidirectional macro-block is combined with two pre-
`dictor macro-blocks of two previously decoded pictures,
`respectively. These two pictures are respectively forrner
`(forward) and subsequent (backward) pictures, in the display
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`This system is simple, but it is incapable of handling the
`high data flow rates needed.
`
`SUMMARY OF THE INVENTION
`
`An object of the present invention is to provide a par-
`ticularly fast picture decompression system with a relatively
`simple structure.
`Another object of the invention is to provide such a
`decompression system that can be easily connected in par-
`allel with identical decompression systems in order to pro-
`cess very high data flow rates.
`To achieve these objects, the invention provides a decoder
`of composite architecture, that is, some of the processing
`elements are connected together and to a picture memory
`through a first bus, and some other elements are connected
`in a pipeline architecture. These other elements are referred
`to hereinafter as a "pipeline circuit". A second bus is
`provided to supply data to be processed to the first element
`of the pipeline circuit as well as the required decoding
`parameters to the elements of the system.
`With this strt.tcture,
`the pipeline circuit processes data
`serially without it being necessary to exchange them with
`the memory through the first bus. In addition, the first bus is
`relieved of the transmission of decoding parameters, these
`parameters being transmitted by the second bus. Thus, the
`number of exchanges on the first bus corresponding to a
`given decoding step is
`substantially reduced, which
`increases the system's performance. The system has a high
`flexibility resulting from the use of a bus system. This
`flexibility is increased by an optimal choice of the elements
`to be included in the pipeline circuit.
`The present invention more particularly addresses a sys-
`tem for processing compressed data arriving in packets
`corresponding to picture blocks, these packets being sepa-
`rated by headers containing decoding parameters of the
`packets. The system includes a plurality of processing
`elements using said decoding parameters, and a memory bus
`controlled by a memory controller to exchange data between
`the processing elements at rates adapted to the processing
`rates of these elements, and to store in a picture memory data
`to be processed or re-used. The system includes a pipeline
`circuit containing a plurality of processing elements con-
`nected to process packets serially, and a parameter bus to
`provide packets to be processed to the pipeline circuit, as
`well as the decoding parameters to elements of the system.
`The parameter bus is controlled by a master processing
`element that receives the compressed data from the memory
`bus and that extracts the packets and the decoding param-
`eters therefrom.
`
`According to an embodiment of the invention, each
`packet of compressed data is preceded by a block header,
`and the packets come in successive groups, each group of
`packets being preceded by a group header containing group
`decoding parameters as well as, possibly, private and on-
`screen display information. The system further includes a
`processor bus controlled by a microprocessor to supply the
`group decoding parameters and the private and on-screen
`display information to the system elements requiring them;
`a bulfcr memory accessible by the processor bus, receiving
`the compressed data through the memory bus; and a group
`header detector cooperating with this bulfer memory to
`generate interrupts of the microprocessor.
`According to an embodiment of the invention, a transfer
`of data between two elements connected to the memory bus
`corresponds to a specific task that is initiated or continued
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`when one of the two elements issues a request to provide or
`to receive data, all the possible tasks being concurrent tasks
`that are carried out by the memory controller according to a
`task priority management.
`According to an embodiment of the invention, the ele-
`ments which exchangc data with the picture memory are
`connected to the memory bus through respective writc— or
`read-only buffer memories. A write—only buffer memory is
`emptied by the associated element and issues a request to
`receive data through the memory bus when its content
`reaches a lower limit. A read-only buffer memory is filled by
`the associated element and issues a request to provide data
`on the memory bus when its content reaches an upper limit.
`According to an embodiment of the invention, the system
`includes a variable length decoder (VLD)
`forming the
`master processing element; a run-level decoder {RLDJ form-
`ing a first element of the pipeline circuit and receiving
`through the parameter bus the packets processed by the
`VLD; an inverse quantizer circuit forming a second element
`of the pipeline circuit and receiving quantizer scale cocfii—
`cients through the parameter bus; an inverse cosine trans-
`form circuit forming a third element of the pipeline circuit;
`the memory controller receiving movement compensation
`vectors through the parameter bus; a filter receiving block
`types through the parameter bus, this filter issuing distinct
`requests, according to the block types,
`to receive corre-
`sponding deta provided on the memory bus as a function of
`the vectors received by the memory controller; and an adder
`to provide on the memory bus the sum of the outputs of the
`filter and of the cosine transform circuit.
`
`According to an embodiment of the invention. the group
`header detector generates interruptions of the microproces-
`sor when the associated buflier memory contains a picture
`sequence header or a picture header.
`the microprocessor
`being programmed to respond to these interruptions by
`reading, in the bufi‘er memory associated with the group
`header detector, quantizcr tables that
`the microprocessor
`provides to the inverse quantizer circuit, information on the
`picture type and on the amplitude of the movement com-
`pensation vectors that the microprocessor provides to the
`VLD, and information on the display configuration that the
`microprocessor provides to a display controller which
`receives the decoded data through the memory bus.
`the
`According to an embodiment of
`the invention,
`memory controller includes an instruction memory (inde-
`pendent of the memory bus),
`in which are stored the
`program instructions corresponding respectively to transfer
`tasks on the memory bus; an instruction processing unit that
`is connected to the instruction memory in order to receive
`therefrom successive instructions to be executed, and that is
`connected to act on the memory bus in response to these
`instructions; a plurality of instruction pointers associated
`respectively to possible tasks and each including the current
`instruction address to be executed of the associated task, one
`only of these pointers is enabled at a time to provide its
`content as an instruction address to the instruction memory;
`a priority decoder assigning a predetermined priority level to
`each request and enabling the instruction pointer associated
`with the active request having the highest priority level; and
`means for incrementing the content of the enabled instruc-
`tion pointcr and for reinitializing it at the address of the
`associated program start when its content reaches the end
`address of the associated program.
`According to an embodiment of the invention, each
`instruction includes a command field that is provided to the
`processing unit and a feature field provided to a prefix
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`decoder that includes means for authorizing the enabling of
`a new instruction pointer by the priority decoder if the
`feature field of the current instruction is at a first predeter-
`mined value, and means for initializing the content of the
`enabled instruction pointer to the start address of the current
`program if the feature field of the current instruction is at a
`second predetermined value.
`According to an embodiment of the invention, the prefix
`decoder includes means for inhibiting the inercmcrttation of
`the enabled instruction pointer if the feature field is at a third
`predetermined value, so that
`the current
`instruction is
`executed consecutively several times, the number of execu-
`tions being determined by this third value.
`According to an embodiment of the invention, each
`instruction includes a command field that is provided to the
`instruction processing unit and an acknowledge field that is
`provided to means
`for, when the instruction is being
`executed, enabling at least one buffer memory connected to
`the memory bus.
`According to an embodiment of the invention, the pro-
`cessing unit includes a plurality of hard wired functions for
`the calculation of addresses, each function being selected by
`a field of a read or write instruction that is being executed.
`According to an embodiment of the invention, with each
`hard wired function is associated an address register con-
`nected to the memory bus; the hard wired function suitably
`modifies the content of its address register each time an
`instruction is executed in the processing unit.
`The present invention also addresses a system for pro-
`cessing compressed data corresponding to pictures, includ-
`ing decoding means that provide decoded picture data to a
`picture memory,
`these means requiring. for decoding a
`current block of a. picture being reconstructed, a predictor
`block of a previously decoded picture. In fact, the processing
`system includes a plurality of decoders associated with
`respective picture memories. each storing a specific slice of
`corresponding blocks of a plurality of pictures, as well as at
`least one margin in which is liable to be a predictor block
`used for reconstructing a block of the specific slice.
`According to an embodiment of the invention, each
`considered decoder includes means for storing in its picture
`memory, as a margin, a boundary area of at
`least one
`additional specific slice and for providing to at least one
`second decoder, as a margin, a boundary area of the specific
`slice associated with the considered decoder.
`According to an embodiment of the invention, each
`considered decoder includes a first buffer memory receiving
`picture blocks from the specific slice; at least one second
`bufier memory receiving picture blocks from an adjacent
`area of another specific slice; a terminal processing circuit
`providing the blocks of the specific slice to the first bulfer
`memory of the considered decoder and to the second buffer
`memory of another decoder; and a memory controller to
`read the blocks in the first buffer memory and to write them
`in the picture memory at addresses corresponding to the
`specific slice, and to read the blocks in the second buffer
`memory and to write them at addresses corresponding to a
`margin.
`According to an embodiment of the invention, each
`second bufl’er memory is preceded by a barrier circuit in
`order to store in the second buffer memory only the data
`corresponding to the desired margin.
`According to an embodiment of the invention, the pic-
`tures to be processed are high definition television pictures
`that are partitioned in horizontal slices of equal height.
`The foregoing and other objects, features, aspects and
`advantages of the invention will become apparent from the
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`invention
`following detailed description of the present
`which should be read in conjunction with the accompanying
`drawings.
`
`BRIEF DESCRIPTION OF DRAWINGS
`
`FIG. 1, above described, shows the main elements of an
`MPEG decompression system;
`FIG. 2A illustrates a decoding step of a macro-block;
`FIG. 2B represents an exemplary macro-block structure;
`FIG. 3 represents an embodiment of a decompression
`system architecture, or MPEG decoder, according to the
`invention;
`
`FIG. 4 is a timing diagram illustrating the operation of the
`decompression system of FIG. 3;
`FIG. 5 represents an advantageous embodiment of a
`memory controller according to the invention;
`FIG. 6 represents another embodiment of a decompres-
`sion syslem architecture according to the invention;
`FIG. 7 illustrates a high definition television picture that
`is to be processed by slices by a plurality of parallel
`decompression systems;
`FIG. 8 represents a plurality of decompression systems
`connected in parallel to process a high definition picture; and
`FIG. 9 partially represents an embodiment of an internal
`structure of a decoder according to the invention that allows
`an easy parallel connection.
`
`GENERAL ARCHITECTURE OF THE MPEG
`DECODER
`
`the elements already shown in FIG. 1 are
`In FIG. 3,
`designated with the same reference numerals.
`
`A bus, hereinafter memory bus MBUS, couples the pic-
`ture memory 15 to the compressed data input bus CDin, to
`the input of the variable length decoder (VLD) 10, to the
`input of the half-pixel filter 14, and to the input of a display
`controller 18. Bus CDin, decoder 10 and display controller
`13 are connected to the memory bus MBUS through respec-
`tive buffer memories (FIFOs) 20, 21, and 22. The half—pixcl
`filter 14 includes two internal FIFOS that are connected to
`the memory bus MBUS. Exchanges on the memory bus
`MBUS are controlled by a memory controller [MCU) 2.4
`that serves to carry out, upon request of the FIFl0s, transfer
`operations between these FIFOs and the picture memory. To
`achieve this purpose, the memory controller 24 receives a
`plurality of
`requests RQ and provides corresponding
`acknowledgements ACK. The memory controller 24 can be
`such as the one described in the above patent application
`EP-A—0,503,956. A more advantageous embodiment of this
`memory controller will be described hereinafter.
`According to the invention, the rtm-level decoder (RLD)
`11, the inverse quantizer circuit (Q‘1) 12, and the inverse
`discrete cosine transform circuit [DCT' 1] 13 are connected
`according to a pipeline architecture, that is, these circuits
`11-13 successively process data to decode, without these
`data temporarily transitting through a memory 15. The set of
`circuits 11-13 is referred to as a pipeline circuit hereinafter.
`Tlte output of the halfwpixel filter 14 is summed to the output
`ofthe DCT" circuit 13 by an adder 16 that is coupled to the
`bus MBUS through a FIFO 26 controlled by the memory
`controller 24. I-Iartd-shake lines H81 and HS2 connect the
`adder 16 to the VLD circuit and to the DCT" circuit,
`respectively.
`
`(cid:51)(cid:68)(cid:74)(cid:72) (cid:20)(cid:20) (cid:82)(cid:73) (cid:21)(cid:19)
`Page 11 of 20
`
`

`
`5,579,052
`
`8
`not be used to calculate another picture. Thus, the recon-
`struction of picture P1 requires picture It], the reconstruction
`of pictures B2 and B3 requires pictures 10 and P1,
`the
`reconstruction of picture P4 requires picture P1, and the
`reconstruction of pictures B5 and B6 requires pictures P4
`and P1.
`These pictures are displayed in the following order:
`
`I0. B2, B3. P1. 35, P4. B6
`
`since a predicted picture P is reconsuucted from a former
`picture in the display order, and since a bidirectional picture
`B is reconstructed from two pictures, one former and the
`other subsequent in the display order.
`To determine the memory area IMl——IM3 which the
`memory controller 24 must access, four picture pointers RP.
`FP, BP, and DP are used, respectively indicating the loca-
`tions of the currently reconstructed picture, of the former
`(forward) picture, of the subsequent (backward) picture. and
`of the currently displayed picture. The following table sums
`up the values of the picture pointers during the decoding of
`the above succession.
`
`
`
`ma
`on
`lid}
`[M3
`uviz
`‘LMI
`RP
`[M2
`1M2
`than
`up
`um
`—
`Ft-"
`en 1
`—
`IM2
`IM2
`—
`—
`BP
`
`
`
`
`
`
`— um IM3 IM3 IM2or IM3
`
`When the first picture 19 is decoded, no picture is displayed
`yet. The reconstructed picture pointer RP indicates an empty
`area, for example area IM1, to store picture It).
`When picture P1 is decoded, picture I0 must be displayed.
`The reconstructed picture pointer RP indicates for example
`area IM2, and the displayed picture pointer DP indicates the
`area IMI in which picture 10 is located. Since the predicted
`picture P1 needs the forward picture It] in its reconstniction,
`the forward picture pointer FP also indicates area IM 1.
`When the bidirectional picture B2 is decoded. this picture
`B2 is also the picture to be displayed, The reconstructed
`picture pointer RP and the displayed picture DP both indi-
`cate the area IM3 that is still free. In its decoding, picture B2
`needs the forward picture 10 and the backward picture P1;
`the forward picture pointer FP and the backward picture BP
`indicate areas [M1 and IM2, respectively.
`To be able to display a picture as it is being decoded. the
`eflfective display is generally delayed by approximately one
`half picture; the area IM3 is sullieicntly filled when picture
`B2 starts to be displayed.
`When picture B3 is decoded, it is also the picture to be
`displayed. Since picture B3 also needs pictures 10 and P1 in
`its decoding, pictures 10 and P1 remain stored in the areas
`[M1 and IM2 that are still indicated by of the forward picture
`FF and backward picture BP pointers. Picture B3 can only be
`stored in area IM3, that is indicated by the reconstructed
`picture RP and the displayed picture DP pointers.
`However, when picture B3 sharks to be reconstructed in
`area IM3, the picture B2, that is also stored in area [M3, is
`being displayed. If the displayed picture B2 is liable to be
`overwritten by the reconstructed picture B3, the VLD circuit
`that is providing the data of picture B3 is stopped. The role
`of the above sequencer 28 is to stop the VLD circuit by
`disabling the enable signal EN when the number of decoded
`macro-blocks corresponds to a picture fraction greater than
`the displayed picture fraction. The size of this fraction is
`determined by counting the number of horizontal synchro-
`
`Decode
`Display
`
`to
`—
`
`P1
`to
`
`B2
`B2
`
`133
`B3
`
`P4
`P1
`
`:35
`135
`
`7
`According to an aspect of the invention, the VLD circuit
`10 controls a bus VLDBUS intended to provide to the RLD
`circuit 1] data to be processed by the pipeline circuit 11- 13,
`as well as parameters to the half-pixel filter 14, to the inverse
`quantizer circuit 12, to the display controller 18, and to the
`memory controller 24. A VLD circuit generally decodes the
`headers of the compressed data that it receives. As men-
`tioned above, these headers include decoding parameters to
`be provided to the various elements of the system.
`A macro—block header includes a quantizer scale to pro-
`vide to the inverse quantizer circuit 12, a macro—block type
`parameter, and the components of the movement compen-
`sation vectors. These decoding parameters arc decoded by
`the VLD circuit and respectively written in specific registers
`of the inverse quantizer circuit 12, of the half-pixel filter 14,
`and of the memory controller 24.
`A picture header includes, as mentioned above, a picture
`type parameter and information on the use of the movement
`compensation vectors. These parameters are used by the
`VLD circuit itself to decode the vectors and data of the
`macro-blocks.
`
`A sequence header includes two quantizer tables that are
`extracted by the VLD circuit and provided to two respective
`registers of the inverse quantizer circuit 12. The picture
`headers contain scaling or truncating parameters concerning
`the displayed picture. that are decoded by the VLD circuit
`and provided to the display controller 18.
`The VLD circuit executes write operations on the bus
`VLDBUS as it decodes the headers. The write operations of
`the VLD circuit on bus VLDBUS can be interrupted by the
`RLD circuit 11 when the latter can no longer receive data to
`be processed. This is represented by a hand-shake connec-
`tion HS3.
`
`A sequencer 28 provides an enable signal EN of the VLD
`circuit. Sequencer 28 receives display (horizontal, vertical)
`synchronization signals HNSYNC through the display con-
`troller 18, a macro-block synchronization signal MBS from
`the hall'—pixel filter 14, and an end of picture signal EOP
`from the VLD circuit 10. The sequencer 28 provides the
`memory controller 24 with a picture synchronization signal
`ISYNC thatis active when the end of picture signal EOP and
`the vertical synchronization signal VSYNC are both active.
`The role of sequencer 28 will be explained subsequently.
`As previously indicated,
`to reconstruct a picture, it is
`often necessary to use picture portions of two previously
`decoded pictures. To achieve this purpose, memory 15 must
`include three picture areas IM1, IM2, and IM3 to store the
`currently reconstructed picture and two previously decoded
`pictures. Memory 15 further includes an area CD to tem-
`porarily store compressed data arriving on bus CDin prior to
`being processed.
`Control of the picture memory areas
`To know in which memory areas IMl—IM3 the memory
`controller 24 must write, the latter uses four picture pointers
`ImPt provided by the VLD circuit. The VLD circuit includes
`a unit for calculating the picture pointers from the picture
`type parameters that are provided by the picture headers.
`Hereinafter, an exemplary picture succession and the
`method for calculating the picture pointers are described.
`Consider the following succession of compressed pictures
`arriving on bus CDin:
`