Conference Materials
`
`Fainnont Hotel, San Jose
`October 10-11, 1995
`
`‘O
`
`Sponsored by
`MICRODESIGN
`Resounces
`
`5i3‘E1Tr‘1‘]53L.1 n g :.:<:hifoit il
`
`f._i);:1>>/1
`
`

`
`AGENDA
`
`WELCOME Michael Slater
`
`KEYNOTE: SEMICONDUCTOR TECHNOLOGY AND THE GROWTH OF THE PC INDUSTRY
`
`Craig Banett, Intel
`
`X86 MICROPROCESSORS Moderator: Michael Slater, MicroDesign Resources
`
`Shifting Sands in the x86 Landscape
`Michael Slater
`
`P6: The Myths and Realities
`Robert Colwell, Intel
`
`BREAK: SPONSORED BY NEC ELECTRONICS
`
`AMD-K5 Performance and Microarchitecture Tradeoffs
`David Witt, AMD
`
`Optimizing the M1 for Windows 95
`Mark Bluhm, Cyrix
`
`_ Overview of the Nx686 Processor
`
`1 Greg Favor, NexGen
`Q&A Panel
`All Speakers above
`LUNCH
`
`Market Trends for x86 Microprocessors
`Aaron Goldberg, Computer Intelligence InfoCorp
`
`PROCESSORS FOR MULTIMEDIA Moderator: Yong Yao, MicroDesign Resources
`
`Implementation Strategies for Multimedia
`Yong Yao
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`Architecture of a Broadband Mediaprocessor
`John Moussouris, Microunity
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`A VLIW and SIMD Vector Processor for PC Multimedia
`
`Stephen Purcell, Chromatic
`The TriMedia VLIW-Based PCI Multimedia Processor
`Gerrit Slavenburg, Philips Semiconductors
`BREAK: SPONSORED BY LSI LOGIC
`
`M.F.A.S.'I': A Highly Parallel, Scalable, Single-Chip DSP
`Gerald Pechaneh, IBM Microelectronics
`
`UltraSPARC’s Instruction Set Extensions for Multimedia
`Marc Tremblay, Sun Microsystems
`A Multimedia 586 Processor for Consumer PCs
`Forrest Normd, Cyrix
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`5200
`
`QSIA Panel
`All speakers above
`MICROPROCESSOR REPORT AWARDS
`Nick Tredermick, Tredenniclz, Inc.
`
`5:30
`
`RECEPTIONILITERATURE & DEMONSTRATION CENTER OPENING
`
`8:30PM-10:30PM
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`AFFINITY SESSIONS
`
`Open Session on Cryptography
`
`Benchmarks & Workloads Roundtable
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`Packaging Technology Directions
`
`The Issue of Branding Microprocessors
`
`Sponsored by
`IVIICRODESIGN
`if
`
`1995 Microprocessor Forum
`
`Page 2 of 16
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`

`
`
`
`AGENDA
`
`EMBEDDED PROCESSORS
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`Moderator: james L. Turley, MicroDesign Resources
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`Ubiquitous Computers: The New Embedded Applications
`James L. Turley
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`Bringing RISC Technology to Communications
`Robert O'Dell, Motorola
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`An Integrated i960 to Enhance Server and Network I/O
`Elliot Garbus, Intel
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`SH-DSP & SH-FPU: Optimized Communication & Consumer Microprocessors
`Jim Slager, Hitachi
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`StrongARM Reaches for Ever Higher Performance
`Rich Witch, Digital
`
`10:20
`
`BREAK: SPONSORED BY FUJITSU MICROELECTRONICS
`
`A Scalable 64-bit RISC for Custom Designs
`Bob Caulk, LSI Logic
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`A PowerPC Core for Cost-Sensitive Consumer Applications
`Kim O'Donnell, IBM
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`A Next-Generation DSP Solution for Communications Applications & Beyond
`Roman Robles, Motorola
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`12:00
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`1:10
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`Q&A Panel
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`All speakers above
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`LUNCH
`
`HIGH-PERFORMANCE RISC MICROPROCESSORS
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`Moderator: Linley Gwennap, MicroDesign Resources
`RISC Processors: Generations
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`Linley Gwenrlap
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`PA-73OOI.C: A Highly Integrated System on a Chip
`Tom Meyer; Hewlett-Packard
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`The Performance of PowerPC 603a and 604e Microprocessors
`Kaivalya Dixit, IBM
`Colorado 4- Extends 32-bit SPARC Performance
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`2:30
`
`Mitch Alsup, Ross Technology
`BREAK: SPONSORED BY MIPS TECHNOLOGIES
`
`UltraSPARC2: Advancing SPARC Performance
`Anant Agrawal, Sun Microsystems
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`Alpha 21 164A: Continued Performance Leadership
`Pete Bannon, Digital Semiconductor
`
`4:10
`
`Q&r:A Panel
`All speakers above
`PANEL: FUTURE OF MICROPROCESSOR SYSTEM ARCHITECTURE
`Moderator: Michael Slater
`
`Dirk Meyer; Digital
`Lin Nease, Hewlett—Packard
`Don North, Apple
`
`Richard Oehler; IBM
`Fred Pollack, Intel
`George White, Corollary
`
`5:00
`
`5:10
`
`WRAP-UP Michael Slater
`
`CONFERENCE ADJOURNED
`
`Sponsored by
`MICRODESIGN
`EEEIEIE
`
`1995 Microprocessor Forum
`
`-
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`Page 3 of 16
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`Anant Agrawal is Vice President of Engineering for Sun’s
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`SPARC Technology Business. He has been involved in the
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`design and development of the SPARC microprocessors at Sun
`since 1984.
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`Mitch Alsup is ROSS Technology’s Chief Architect for its
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`SPARC CPU product line. Mitch joined ROSS in 1991 from
`Motorola, where he was the Architect of Motorola’s 88000.
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`Peter Batman is a Consulting Engineer with Digital
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`Semiconductor, Pete has participated in the design or verifica-
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`tion of several microprocessor chips and was a member of the
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`Alpha 21164 architecture team.
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`is the Chief Architect of Cyrix's M1 as well as director
`Mark Bll.|l1l'I'I
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`of engineering responsible for all future superscalar processors. As one
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`of Cyrix’s initial design engineers, Mark helped define and design sev-
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`eral generations of wholly original x86 processors and math coproces-
`sors.
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`Bob caulk has spent the last six years at LSI Logic leading
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`architecture definition and product development for LS1’s MIPS
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`RISC processor family of embedded cores and derivative
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`products.
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`Robert coiwell manages the P6 architecture organization at
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`Intel. Bob joined Intel in 1990 as a Senior Architect on the P6
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`project. and became manager of the architecture group two
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`years later. Prior to Intel he was a CPU architect at Multiflow
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`Computer.
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`Kaivalya Dlxit is IBM's Director of Perfomance. Previous to
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`joining IBM, he was Engineering Program Manager at SUN
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`Microsysterns.
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`Gregory Favor is NexGen's Director of 686 Processor
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`Development. Previous to his appointment to the Director
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`position he was the Chief Processor Architect.
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`Elliot Garbus is Strategic Development Manager i.n Intel’s
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`Semiconductor Products Group. Elliot has participated in the
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`definition of the three generations of 80960 microprocessor
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`products. He is currently working on products to enhance the
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`U0 performance of servers.
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`Aaron Goldberg is Executive Vice President of Computer
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`Intelligence InfoCorp. Prior to joining InfoCorp in 1992. Aaron
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`was Senior Vice President ofthe Desktop Computing Group at
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`International Data Corporation.
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`Dirk Meyer is the Lead Architect of Digital’s third-generation
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`high-end Alpha microprocessor. Dirk was a co-microarchitect
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`of Digital’s first-generation Alpha 21064 microprocessor and an_
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`original member of the Alpha CPU tearn.
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`Tom Meyer is currently a member ofHewlett-Packarcl’s
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`Systems Technology Division and Project Manager for the
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`PA7300I.C integrated memory and IIO controller. Previously he
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`worked on the PA7l00I_C and the memory controller for sever-
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`al of the I-IP9{}U0 Series computers."
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`0 speaker biographies
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`Michael Slater, moderator
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`Founder and President of MicroDesign Resources, Michael
`Slater serves as the Editorial Director and Publisher of
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`Microprocessor Report and Director of the Microprocessor
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`Forum. He is internationally recognized as a leading authority
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`on microprocessor technology and system trends. Michael has
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`lectured at Stanford University, Santa Clara University. and
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`National Technological University. He has presented hundreds
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`of seminars and consults regularly for companies including
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`IBM, Apple, Sun, Intel, Motorola, AMD, Arndahl, Digital, and
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`Tektronix. He is a columnist for Electronic Engineering Times,
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`Nikkei Electronics Asia, and Computer Shopper, and he has writ-
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`ten for many computer publications.
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`Llnley Gwennap, moderator
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`is Editor-in-Chief of Microprocessor Report and Director of
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`Product Development for MicroDesign Resources. He joined
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`MDR in 1992 after eight years at Hewlett-Packard working on
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`RISC systems. His positions at HP included Product Manager
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`for the HP PA710D microprocessor, Program Manager for the
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`HP9000 model 815, and System Designer for the I-IP90fl0 model
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`870. He currently consults on microprocessor developments and
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`strategies for leading processor and system vendors.
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`James Turley, moderator
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`Senior Analyst and Senior Editor of Microprocessor Report, spe-
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`cializing i.n high-performance embedded microprocessors, Iirn
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`joined MDR in 1994 after devoting more than a dozen years to
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`design engineering, engineering management, product market-
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`ing, and program management. He has designed embedded
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`processors into a variety of products and developed both hard-
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`ware and software for leading companies around Silicon Valley
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`and in Europe. He has also conducted numerous seminars and
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`training courses.
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`Yong Yao, moderator
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`Director of the Technology Roadmap Service and Senior
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`Analyst for PC technology for Microprocessor Report, is the most
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`recent addition to the MicroDesign Resources staff of analysts.
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`Prior to joining MDR, Yong was with Vitesse Semiconductor,
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`where he was the director of product planning as well as the
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`designer of the multiprocessor V-Bus.
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`Craig Barrett, keynote speaker
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`is Executive Vice President and Chief Operating Officer of Intel
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`Corporation, having corporate-wide responsibility for internal
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`operations of the company. He joined Intel in 1974 and served
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`in various technical and business management positions. In
`1984 Dr. Barrett was named a Vice President, and he became
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`General Manager of the Components Technology and
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`Manufacturing Group in 1985. Dr. Barrett was named a Senior
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`Vice President in 1987 and became comanager of the
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`Microcomputer Components Group in 1989. He was promoted
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`to the post of Executive Vice President in 1990. Dr. Barrett was
`elected to the Board of Directors in 1992 and was named Chief
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`Operating Officer in January 1993.
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`3D
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`MICROPROCESS
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`n
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`Page4of1
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`Page 4 of 16
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`speaker biographies
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`JOII1 Moussouris is President and CEO of MicroUnity Systems
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`Engineering, which he founded i.n 1988. Prior to that John was
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`Vice President ofVLSI Development at MIPS Computer Systems.
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`i.il'I H8398 has been a System Architect for several of Hewlett-
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`Pacl-card's UNIX server products, including the G-, H-, and 1-
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`class midrangeflow-end systems. He has been involved in the
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`development of HP's commercial UNIX servers since the
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`advent of that product line.
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`Forrest Norrotl is Program Manager and Principal Architect of
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`the multimedia 586 CPU at Cyrix. Prior to joining Cyrix in
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`1993, Forrest was with Hewlett-Packard, where he designed
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`advanced 3D graphic systems.
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`Don North has been associated with the Advanced Technology
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`Group at Apple since its inception in 1985, and currently man-
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`ages a systems architecture research group. His current research
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`interests include high-performance system interconnect issues
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`and multiprocessor systems architecture.
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`Richard Oehler is the Director of Systems Software in the
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`Power Personal Systems Division at IBM. In over 20 years with
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`IBM he has been involved in development of the 801, the first
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`RISC machine, was lead architect for the the RISC Systemr'6000,
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`and is responsible for all dealings on PowerPC. In 1994 Rich
`became an IBM Fellow.
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`Robert 0’Defl has played a significant role in the definition of
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`Motorola's integrated communications controller family of
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`products. Robert is currently the Applications Manager for the
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`Data Communications Operation in the High Performance
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`Embedded Systems Division of Motorola’s Semiconductor
`Products Sector.
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`Jim slager specializes in microprocessor and multimedia prod-
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`ucts, Iim is Director of Advanced Product Planning at Hitachi
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`Micro Systems. He participated in the design of the 286, 386,
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`and 486 at Intel and was involved in SPARC design at Sun
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`Microsystems.
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`Genil: Slavenberg, Chief Scientist, 'I'riMedia technology, for
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`Philips Semiconductors, Gert is responsible for development of
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`current and future TriMedia products.
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`Nick Tredennick is President of Tredennick, Inc. He created the
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`logic design for the 68000 at Motorola and for the Microl370
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`microprocessor at IBM.
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`Marc Tremblay, as a computer architect involved in the
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`research and development of high-performance processors at
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`Sun Microsystems Marc’s main contributions have focused on
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`the microarchitecture definition and performance evaluation
`for the 64-bit UltraSPARC Processor.
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`Geolge White, a cofounder and President of Corollary, George
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`has pioneered a new category of computer, the PC-compatible
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`multiprocessor system. He was instrumental in the develop-
`ment of the NuBus and was the chairman of the IEEE commit-
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`tee that standardized the NuBus.
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`Rich Witek, a principal designer of the Alpha architecture and
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`co-architect of the first Alpha chip, Rich is currently the Chief
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`Architect for the StrongARM microprocessor family at Digital.
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`David will is a Product Development Manager at AMD, where
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`he is in charge of the Argon.iI(7 processor development. David
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`was in charge of the K5 development effort at AMD, where he
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`has been working for the past 11 years.
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`Kim O'Donnell, as Senior Engineering Manager for IBM, is
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`responsible for the design and development of the IBM
`PowerPC 400 Series of Embedded Controllers.
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`Gerald Pechmek, at IBM Microelectronics Mwave group, is
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`involved in the research and development of parallel computer
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`architectures for graphics-, video-, neural-, and signal-process-
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`ing multimedia applications.
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`Fred Pollack is director of the group responsible for all Intel
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`platform architecture and performance analysis. He also directs
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`the planning for Intel’s future microprocessors. Prior to this, he
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`was the manager of the P6 architecture. In Ianuary of 1993 he
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`was promoted to an Intel Fellow, one of nine in the company.
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`Stephen Purcell is co-founder of Chromatic. He was previous-
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`ly a founder and Chief Architect at C-Cube Microsystems where
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`he created the architecture for four generations of video
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`CODECs, including the VideoRISC processor.
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`ROITIHI Robles is manager of Motorola's 24- and 32-bit DSP
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`applications group. He has worked in Motorola's DSP applica-
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`tions group for the past five years, focusing primarily on
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`Motorola’s industry-standard 24-bit DSP5600D architecture and
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`applications.
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`Page 5 of 16
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`MICROPROCESS
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`M
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`Page 5 of 16
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`

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`The TriMedia VLIW-Based
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`PCI Multimedia Processor
`
`................................................................... --,
`
`Gerrit Slavenburg
`Philips Semiconductors
`
`Sponsored by
`
`MICRODESIGN
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`Page 6 of 16
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`12
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`

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`The Trimedia VLIW—Based PCI Multimedia Processor
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`The Trimedia VLIW-based PCI
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`Multimedia Processor System
`
`Gerrit Slavenburg - Philips Semiconductors
`
`TM-1 : outside
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`multl-standard, as In “any"
`
`Video and Audio (de)compression
`3D graphics
`customer programmable, using
`standard C
`
`CCIR 601/656
`
`ccm 501/555
`YUV 4:2:2
`
`Microprocessor Forum
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`October 10-11, 1995
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`Page 7 of 16
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`

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`The Trimedia VLIW-Based PCI Multimedia Processor
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`TM-1 configurations
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`accellerator
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`(dig) VCR
`TV monitor
`audio
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`stand alone
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`TV m°nit°r
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`TM-1 : inside
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`Serial
`digital audio
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`synchronous
`setial in for
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`Pclmuurlslnvo "
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`Microprocessor Forum
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`12-2
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`October 10-11, 1995
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`Page 8 of 16
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`

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`The Trimedia VLIVV-Based PCI Multimedia Processor
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`TM-1 Functional
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`
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`hardware
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`
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`hardware
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`
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`Video DIUIA in:
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`»:- cCIFtED1:’656 ‘(UV 4:2:2 input
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`0 horizontal scaling by 1:1 or 2:1
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`Video DMA out:
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`-:. cclnsmrese vuv 4:2:2 out
`-i- horizontal scaling by 1:1 or 1:2
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`-:- graphics overlay (alpha blending}
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`
`h-"age co..p,-ocessor
`,:_ memoI.y_to_mam°w
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`-3- memory to PCI windows, with YUV to FIGB
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`-9 V resizing, H resizing
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`VLD co-processor
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`_
`-:- memory-to-memory de-tokenize
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`4- MPEG-2, MPEG-1 sliceitime
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`Audio DMA inloutz
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`4- 5 or 16 bit
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`-3-
`|T|'I0i"I0 Of SMYBO
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`«a» programmable D - 80 kHz sampling
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`sgftware
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`ml-|“i't3SkiU9 in C 0“ DSPCPU3
`4'
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`compression (any standard)
`4'
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`decompression (any standard}
`-9
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`3'3 9""P"i°3
`'fi'
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`5V5‘°'“ °°"t'°'
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`° PC Am 3""'°°"
`using powerful custom multimedia
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`
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`operations
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`TM-1 Highway Arbitration
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`-5- software assigns bandwidth to each master
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`-a- every master is guaranteed:
`— minimum bandwidth as assigned
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`— associated max. latency
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`-:o all unused bandwidth is available:
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`— to the D5PCPU!caches within 1 cycie
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`— to any other master within a few cycles from request
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`this is an essential function for audiolvideo
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`Microprocessor Forum
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`October 10-11, 1995
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`Page 9 of 16
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`Page 9 of 16
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`

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`The Trimedia VLIW—Based PCI Multimedia Processor
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`Image Co-Processor capabilities
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`+ unlimited number of
`live video windows
`+ arbitmry H & V scaling
`using quality filters
`+ can drive RGB or YUV
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`graphics cards
`+ up to 50 Mpixel/sec refresh
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`AudioNideo synchronization
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`Video In :
`Video Out :
`
`Audio In,
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`cameraloutside world is pixel clock master
`programmable 1 0 MHz - 38 MHz, resolution 0.02 Hz
`(very low jitter synthesizer)
`
`Audio Out:
`
`programmable 256 or 3841!. of 0 - 20 MHz, 0.02 Hz
`
`Synchronization is achieved by software PLL's that vary the sampling
`frequencies/phase by minute amounts. This powertul method is universal
`and avoids application speclflc external hardware.
`
`Microprocessor Forum
`
`12-4
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`October 10-11, 1995
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`Page 10 of 16
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`

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`The Trimedia VLIVV-Based PCI Multimedia Processor
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`TM-1 DSPCPU block diagram
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`TM-1 DSPCPU functional units
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`Fllnctional Unit
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`constant
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`integer ALU
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`load/store
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`DSP ALU
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`DSP MUL
`shifter
`branch
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`intlfloat mul
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`float. ALI!
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`float comnare
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`float sort/div
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`—‘-‘I*3I~)'J3h3I~’l\)l\3LlIlII
`
`Latencv
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`Recoverv Time
`
`;‘,--'.»:»'..a—-uN:n-—-
`
`;_n-n—A—A—A—A-nu-5-5.:
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`Microprocessor Forum
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`October 10-11, 1995
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`Page 11 of 16
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`

`
`The Trimedia VLIW-Based PCI Multimedia Processor
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`TM-1 instruction format
`
`9 5 operations issued every clock cycle (10 nsec)
`9 Functional units are pipelined - each can start one operation per cycle
`o Issue slots are “guarded" for branch avoidance, delay slot utilization
`o lnterruptable opcodes facilitate lightweight context switching
`o Instructions compressed in memory and lcache, decornpressed on the fly
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`umei
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`lfir8il
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`Trimedia programmer’s model
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`registers
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`'“°"'°'V map
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`Microprocessor Forum
`
`12-6
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`October 10-11, 1995
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`Page 12 of 16
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`

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`The Trimedia VLIW-Based PCI Multimedia Processor
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`Trimedia operation examples
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`Typical 32 bit RISC CPU operations
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`-:- Integer, unsigned, logical, floating point (32 bit IEEE compatible)
`-9 Conditional branches
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`«a» Loadslslores with address modes
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`Typical 8, 16 and 32 bit DSP operations
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`«:- Saturation arithmetic (add, multiply-add, ...)
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`Branch-avoiding operations
`-9- Min, max
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`-:- Select one of two operands depending on a third
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`(implemented as branch-free three-operation sequence)
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`35 Multimedia-enhancing operations
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`(motion estimation)
`-:o me8(abcd,efgh)
`la-el+|b-i|+lc-gl+ld-hi
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`(FIR filters)
`-:- fir16(ab,cd) Dual multiply-add —ac+bd
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`4- quadavg(abcd,eigi1)
`1%-A’ ltséifl’ E331’ %‘:isubsampling filters)
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`TM-1 DSPCPU key features
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`'3'
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`-9
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`'5'
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`‘S’
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`‘E0
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`-3
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`*2‘
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`dual bytesex, determined by PCSW flag
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`byte addressed memory, natural alignment required
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`speculative loads 8: floating point supported
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`precise IEEE exceptions, even when using speculation
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`5 opslcycle, sustained
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`conditional (guarded) execution of each operation
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`compressed, byte aligned VLIW instructions
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`vectored interrupts, zero overhead enterfreturn
`— compiler inserts interruptable points
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`— CPU can handle simple interrupts at > 100 kHz with low loading
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`-:- instruction 8: data (addresslvalue) breakpoint hardware
`-:»
`level-1 boot from l2C resident serial xxFl0M
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`Microprocessor Forum
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`October 10-11, 1995
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`Page13of16
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`Page 13 of 16
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`

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`The Trimedia VLIW-Based PCI Multimedia Processor
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`Example TM—1 (simplified to 3lcycle)
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`101
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`cycle
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`102
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`103
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`104
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`105
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`106
`107
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`#13—)r11
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`Id32 r12(4)—>r13
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`iaddi 112,220->rl7
`ileq r11,r1S—>r11
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`ld32x r17,r19 —>r16
`rl1:st32 1-12(8) 1-14
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`r11:st32 1-12(l2) 1'13
`bitinv r1l—>r21
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`r21:st32 r12(l2) r17 r2l:fir8 rl01,r102->r23
`
`
`r21:#1234—>r24
`r2l:fil'8 rl03,1'16—>l'25
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`
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`t'lr8 rl04,r105—>r26 fir8 1'106,rl07 ->127
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`
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`mes rl01,rl|}0—>r14
`
`
`#LABEL—)r18
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`
`
`cjmpt rl1,r18
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`1-11:me8 r99,r98->r42
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`r11:me8 r97,r96—>r43
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`r1I:me8 r95,r94->r44
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`iadd r42,r43—>r45
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`
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`107 mes r93,r92—)r45
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`nte8 r91,r90—)r46
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` %rl8
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`TM—1 system key stats
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`9 consumer electronics price level, ranging to sub $50
`9 Early Access Program:
`
`
`
`
`— software development tools (now)
`
`
`
`— samples 02 ‘96
`
`
`
`9 application performance:
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`
`
`—- MPEG-2 main level, main profile, 15 Mbitisec.
`
`
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`
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`Video+Audio-a-System decoding
`
`
`— H.320 coder: Video-I-Audio
`
`
`
`— H.324 codec Video+Audlo-rsoftware V34 modem
`
`
`
`
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`— any custom WA algorithms with similar compute requirements
`
`
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`-
`0 typical 4 W (0 100 MHZ, 3.3 V)
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`
`, I‘.I.5u OM05, 4L metal with shrink to 0.351.: to follow
`
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`o available in 240 pin EDOUAD or Super8GA package
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`Microprocessor Forum
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`12-8
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`October 10-11, 1995
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`Page14of16
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`Page 14 of 16
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`

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`The Trimedia VLIW-Based PCI Multimedia Processor
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`Software development
`
`
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`
`
`
`‘human assisted microcode compilation’
`
`
`
`
`
`
`
`oz» sophisticated compilerfdebugger environment
`
`
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`
`
`
`
`-:- compile, run, recompile for automatic fine grain
`
`parallelization
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`
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`-:- programmer feedback (where is time spent, where is
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`
`parallelism limited)
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`TM-1 Innovations
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`-9 very high performance CPU on a chip at a consumer
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`price point
`— enhanced VLIW architecture with conditional execution
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`— VLIW Instruction compression : sub FIISC code size
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`
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`— multimedia operation set based on actual application ports
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`— zero overhead interrupt handling
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`— sophisticated compiler: profile driven program transformation and
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`instruction scheduling
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`-:- complete audiofvideo system + CPU on single chip
`— software controlled Audiolifideo synchronization
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`— DMA mastering U0 units
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`— DMA mastering co-processors (image & VLD co-processor)
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`-:- 100 MHz SDI-'tAl'ii'l interface, under worst-case conditions
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`Microprocessor Forum
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`October 10—1 1, 1995
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`Page15of16
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`Page 15 of 16
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`

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`The Trimedia VLIVV-Based PCI Multimedia Processor
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`
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`Trimedia
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`A “Family” of software compatible media processors
`-:- continuous renewal of CPU cores
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`-:- interfaces addressing different market segments (PC, settop, TV, ..)
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`4» mainline 8: derivative product strategy
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`-z- a single architecture for all audio, video, graphics, communication, user-
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`interiace and system control
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`Superior flexibility and programmability
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`-r- "Any" compression standard
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`a:- All programming in Standard C
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`«a Appilcationsflibraries available for Audio, Video, Graphics
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`-:- SUN and PC hosted programming environment
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`-:- Automatic fine-grain parallelization
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`-:- Sophisticated source-level debugging of Device Under Test
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`Microprocessor Forum
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`
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`12-10
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`October 10-11, 1995
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`Page 16 of 16
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`Page 16 of 16