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`Samsung Exhibit 1002
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`Page 6 of 280
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`=3:
`t‘,
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`SGS'THOMS0N
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`; I® lilfiU©E‘%©ElE©W3©lilJfl@S
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`3‘)
`,_
`H
`‘V,
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`THE ASSISTANT COMMISSIONER FOR PATENTS
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`Washington, D.C. 20231
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`Re:
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`For:
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`lnventor(s): Raul Z. Diaz and Jefferson E. Owen
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`Video and/or Audio Decompression and/or Compression Device that Shares a
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`Memory Interface
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`Our File No: 96-S-11
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`Sir:
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`Enclosed with this transmittal letter are:
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`_
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`(1)
`(2)
`(3)
`(4)
`(5)
`(5)
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`Subject patent application with Declaration and Power of Attorney;
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`Five (5) sheets of informal drawings;
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`Certificate of Express Mail;
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`Assignment and Recordation Cover Sheet;
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`Check in the amount of $1,396.00;
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`Return postcard which we would appreciate your date stamping and returning to
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`us upon receipt;
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`The total filing fee has been calculated as follows:
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`=
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`=
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`$ 750.00
`40.00
`638.00
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`156.00
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`= $1.584.00
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`Basic fee
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`Recordation of Assignment
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`29 claims in excess of 20
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`2 independent claim in excess of 3
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`Total filing fee
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`I authorize the Commissioner to charge any additional fees which may be required, or
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`credit any overpayment to Account No. 19-1353. A duplicate copy of this sheet is
`enclosed.
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`Irena Lager 2;
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`Reg. No. 39, 60
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`SGS.-THOMSON Microelectronics, Inc. - 1310 Electronics Drive - Carrolllon, TX 75006-5039
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`Telephone (214) 466-6000, Telex 730643
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`STWZ-CAR
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`Page 7 of 23826123313
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`Page 7 of 280
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`III! /"7fl')Q1 1 STATES PATENT AND TRADEMARK OFFICE
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`In Re Application of:
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`Raul Z. Diaz and Jefferson E. Owen
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`Docket No. 96-S-O11
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`For: Video andlor Audio Decompression andlor Compression Device that Shares
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`a Memory Interface
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`CERTIFICATE OF EXPRESS MAIL
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`"EXPRESS MAIL" NO. EG9473I32259US
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`Date of Deposit: August 23, 1996
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`I hereby certify that this paper or fee is being deposited with the United States
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`Postal Service "Express Mail Post Office to Addressee" service under 37 CFR 1.10 on
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`the date indicated above and is addressed to the Assistant Commissioner for Patents,
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`Box Patent Application, Washington, D.C. 20231.
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`Signature of person mailing paper or fee
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`Page 8 of
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`Page 8 of 280
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`Cross-reference to Related Applications
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`This application contains some text and drawings in common with pending
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`U.S. Patent Applications entitled: "Video and/or Audio Decompression and/or
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`. Diaz,
`Compression Device that Shares a Memory" by Jefferson E. Owen, Raul
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`5;
`~<$'.o
`* \*OQU~x\
`0%))-ta/<%
`"7
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`5[N 0( sm2), and has the
`and Osvaldo Colavin
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`same effective filing date and ownership as the present application, and to that
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`is related to the present application, which is incorporated herein by
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`extent
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`10
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`reference.
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`15
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`Background
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`The present invention relates to the field of electronic systems having a video
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`and/or audio decompression and/or compression device, and is more specifically
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`directed to sharing a memory interface between a video and/or audio decompression
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`and/or compression device and another device contained in the electronic system.
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`The size of a digital representation of uncompressed video images is
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`dependent on the resolution, and color depth of the image. A movie composed of
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`a sequence of such images, and the audio signals that go along with them, quickly
`becomes large enough so thatiuncompressed such a movie typically cannot fit
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`It is also typically‘
`entirely onto conventional recording medium, such as a CD.
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`A25
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`vvvvvvv»
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`:4
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`SGS-THOMSON Microelectronics Inc.
`96-S-11
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`Page 1
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`now prohibitively expensive to transmit such a movie uncompressed. \
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`It is therefore advantageous to compress video and audio sequences before
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`they are transmitted or stored. A great deal of effort is being expanded to develop
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`systems to compress these sequences. There are several coding standards currently
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`used that are based on the discrete cosine transfer algorithm including MPEG-1,
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`(MPEG stands for "Motion Picture Expert Group",
`MPEG-2, H.261, and H.263.
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`a committee of the International Organization for Standardization, ISO.) The
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`MPEG-1, MPEG-2, H.261, and H.263 standards are decompression protocols that
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`describe how an encoded bitstream‘ is to be decoded. The encoding can be done
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`in any manner, as long as the resulting bitstream complies With the standard.
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`Video and/or audio compression devices (hereinafter encoders) are used to
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`encode the video and/or audio sequence before it is transmitted or stored. The
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`(hereinafter decoder) before the video and/or audio sequence is displayed.
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`However, a bitstream can only be decoded by a decoder if it complies to the
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`standard used by the decoder. To be able to decode the bitstream on a large
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`number of systems it is advantageous to encode the Video and/or audio sequences
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`to comply to a Well accepted decompression standard. The MPEG standards are
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`currently Well accepted standards for one Way communication. H.261, and H.263
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`are currently Well accepted standards for video telephony.
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`Once decoded the images can be displayed on an electronic system dedicated
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`to displaying video and audio, such as television or digital video disk (DVD)
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`player, or on electronic systems Where image display is just one feature of the
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`system, such as a computer. A decoder needs to be added to these systems to
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`SGS-THOMSON Microelectronics Inc.
`96-S-11
`Page 2
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`allow them to display compressed sequences, such as received images and
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`associated audio, or ones taken from a storage device. An encoder needs to be
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`added to allow the system to compress video and/or audio sequences,
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`transmitted or stored. Both need to be added for two way communication such as
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`A typical decoder, such as an MPEG decoder 10 shown in Figure 1a,
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`16, and a memory interface 18. The decoder can also contain other circuitry
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`example, when the decoder is designed to operate in a typical television the decoder
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`will also contain an on screen display (OSD) circuit.
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`Figure 1b shows a better decoder architecture, used in the STi352O and
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`STi3 520A MPEG Audio/MPEG-2 Video Integrated Decoder manufactured by SGS-
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`The
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`THOMSON Microelectronics. The decoder has a register interface 20 instead of
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`interface 20 is coupled to an external
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`rnicrocontroller 24. The use of a register interface 20 makes it possible to tailor the
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`decoder 10 to the specific hardware the decoder 10 interfaces with or change its
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`operation without having to replace the decoder by just reprogramming the register
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`It also allows the user to replace the microcontroller 24, to upgrade or
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`and reprogramming the register interface 20, without having to replace the decoder
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`10.
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`The memory interface 18 is coupled to a memory 22. A typical MPEG
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`decoder 10 requires 16 Mbits of memory to operate in the main profile at main
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`level mode (MP at ML). This typically means that the decoder requires a 2Mbyte .
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`memory. Memory 22 is dedicated to the MPEG decoder 10 and increases the price
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`of adding a decoder 10 to the electronic system.
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`In current technology the cost of
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`this additional dedicated memory 22 can be a significant percentage of the cost of
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`An encoder also requires a memory interface 18 and dedicated memory.
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`Adding the encoder to an electronic system again increases the price of the system
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`by both the price of the encoder and its dedicated memory.
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`in the semiconductor industry is to reduce the die area of an
`A goal
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`integrated circuit device for a given functionality. Some advantages of reducing the
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`die area is the increase in the number of the die that can be manufactured on same
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`results in both an increase in volume and reduction in price of the device.
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`Many of the functional circuits described above for Figure la and Figure lb
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`take up a lot of die space. However, each of them is needed to make the respective
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`Figure 1c shows a computer 25 containing a decoder 10, a main memory 168
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`and other typical components such as a modem 199, and graphics accelerator 188.
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`The decoder 10 and the rest of the components are coupled to the core logic chipset
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`190 through a bus 170. The bus is typically a PCI (peripheral component interface)
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`or ISA (industry standard architecture) bus, and each component contains an
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`!
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`~»v:.,,;.‘
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`Page 13 of 280
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`periodically between images until the decoder can get access to the memory to
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`process the next image. The movie may stop quite often between images and wait.
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`2 To reduce the minimum required bandwidth and still operate in real time, the
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`decoder 10 may need to drog/%?’a1:aea.5If the decoder 10 regularly does not decode
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`every frame then it may not need to stop between images. However, this produces
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`very poor continuity in the images. This is problematic with an image encoded to
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`the MPEG-1 or MPEG-2 standard;(, or any standards that uses temporal
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`In temporal (interpicture) compression some of the images are
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`decoded based on previous images and some based on previous and future images. _
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`Dropping an image on which the decoding of other images is based is unacceptable/
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`and will result in many poor or even completely unrecognizable images.
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`The computer can also contain both a decoder and encoder to allow for video
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`telephony, as described above.
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`In this case not operating in real time would mean
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`that the length of time between the occurrence of an event, such as speaking, at one
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`end of the conversation until
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`conversation is increased by the time both the encoder and then the decoder must
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`wait to get access to the bus and the main memory. Not being able to operate in
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`real time means that there would be gaps in the conversation until the equipment
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`can catch up. This increases the time needed to have a video conference, and
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`makes the conference uncomfortable for the participants.
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`One widely used solution to allow a component in a computer system to
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`operate in real time is to give the component its own dedicated memory. Thus, as
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`shown in Figure lc, the decoder 10 can be given its own dedicated memory 22,
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`with a dedicated bus 26 to connect the decoder 10 to its memory 22.
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`The
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`96-S-11
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`its controller and the pins to control
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`significantly increase the cost of adding a decoder 10 to the computer.
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`this memory
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`dedicated memory 22,
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`/ \
`[E
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`96-S-11
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`Summary of the Invention
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`The present application discloses an electronic system that contains a first
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`device and video and/or audio decompression and/or compression device capable
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`of operating in real
`time. Both the first device and the video and/or audio
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`decompression and/or compression device require a memory interface. The video
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`and/or audio decompression and/or compression device shares a memory interface
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`and the memory with the first device. In the preferred embodiment of the invention
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`the shared memory interface contains an arbiter. The arbiter and DMA engines of
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`the video and/or audio decompression and/or compression device and of the first _
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`device are configured to arbitrate between the two devices When one of them is
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`requesting access to the memory. This allows the use of one memory interface to
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`the access of both the video and/or audio decompression and/or
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`compression device and the first device to the memory.
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`control
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`When the video and/or audio decompression and/or compression device used
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`in an electronic system, such as a computer, already containing a device that has
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`a memory interface the video and/or audio decompression and/or compression
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`device can share that memory interface and the memory of the device and the
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`memory interface and memory of the video and/or audio decompression and/or
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`compression device can be eliminated. Eliminating this memory interface reduces
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`the die area without changing the critical dimensions of the device. Therefore
`increasing the volume and reducing the cost of the decoder or encoder. Eliminating
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`the memory greatly reduces
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`compression device to operate in real time.
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`fact that the video and/or audio decompression and/or compression device does not
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`decompression and/or compression device can share the memory of the device with
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`video and/or audio decompression and/or compression device is reduced because
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`first device and no extra packaging or pins are needed for the video and/or audio
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`decompression and/or compression device, and no pins are needed for the first
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`two devices.
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`Other advantages and objects of the invention will be apparent to those of
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`ordinary skill in the art having reference to the following specification together with
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`Brief Description of the Drawings
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`Figure la and lb are electrical diagrams, in block form, of prior art decoders.
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`in block form, of a computer system
`Figure 1c is an electrical diagram,
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`containing a decoder according to the prior art.
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`Figure 2 is an electrical diagram, in block form, of an electronic system
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`containing a device having a memory interface and an encoder and decoder.
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`containing a core logic chipset designed for the CPU to share a memory interface
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`in block form, of a computer system
`Figure 4 is an electrical diagram,
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`Detailed Description of the Preferred Embodiment
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`Figure 2 shows an electronic system 40 containing a first device 42 having
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`access to a memory 50 through a memory interface 48, and a decoder 44 and
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`encoder 46, having access to the same memory 50 through the same memory
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`interface 48. First device 42 can be a processor, a core logic chipset, a graphics
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`accelerator, or any other device that requires access to the memory 50, and either
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`contains or is coupled to a memory interface. Any parts common to Figures 1
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`through 4 are indicated using the same numbering system.
`In the preferred
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`embodiment of the invention, electronic system 40 contains a first device 42, a
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`decoder 44, an encoder 46, a memory interface 48, and a memory 50. Although, I
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`either the decoder 44 or encoder 46 can be used in the decoder/encoder 45 without
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`the other. For ease of reference, a video and/or audio decompression and/or
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`compression device 45 will hereinafter be referred to as decoder/encoder 45. The
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`decoder/encoder 45 may be a single device, or cell on an integrated circuit, or may
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`be two separate devices, or cells in an integrated circuit.
`In the preferred
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`embodiment of the invention, the first device 42, decoder/encoder 45, and memory
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`interface 48 are on one integrated circuit, however,
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`integrated circuits in any combination.
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`C II (C. u.'u+ I Q-
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`The decoder 44 includes a video decoding/k1-2—ei1=euit- and an audio decoding
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`circuit 14, both coupled to a register interface 20. The decoder 44 can be either a
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`video and audio decoder, just a video, or just an audio decoder. If the decoder 44
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`is just a video decoder it does not contain the audio decoding circuitry 14. The
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`audio decoding can be performed by a separate audio codec coupled to the first
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`device 42, or through software‘.
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`when the decoder/encoder 45 is in a system containing a processor and is coupled
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`The first device 42 also contains a DMA engine 60. The DMA engine 60
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`of the first device 42 is coupled to the arbiter 54 of the memory interface 48. The
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`memory interface 48 is coupled to a memory 50. The memory controller 56 is the
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`control logic that generates the address the memory interface 48 a.eeess— in
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`encoded to comply with, whether the decoder/encoder 45 is to operate inreal time,
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`to what extent frames are dropped, and which images are stored. Additionally, the
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`latency of the bus 70 that couples the decoder/encoder 45 to the memory 50 should
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`is to have the decoder/encoder 45 operate in real
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`dropping so many frames that it becomes noticeable to the human viewer of the
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`movie. To operate in real time the decoder/encoder 45 should decoder and/or
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`time without
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`encode images fast enough so that any delay in decoding and/or encoding cannot
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`be detected by a human viewer. This means that the decoder/encoder 45 has a
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`' 5/"””””’"”"”“
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`SGS-THOMSON Microelectronics Inc.
`96-S-11
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`Page 14
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`Page 22 of 280
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`required bandwidth that allows the decoder/encoder 45 to operate fast enough to
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`decode the entire image in the time between screen refreshes, which is typically
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`1/30 of a second, with the human viewer not being able to detect any delay in the
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`decoding and/ or encoding. To operate in real time the required bandwidth should
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`be lower than the bandwidth of the bus.
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`components on the bus, i.e. deny these components access to the memory for an
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`amount of time that would interfere with their operation, this required bandwidth
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`should be less the entire bandwidth of the bus. Therefore a fast bus 70 should be
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`used. A fast bus 70 is any bus whose bandwidth is equal to or greater that the
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`required bandwidth. There are busses, in current technology, including the ISA ‘
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`bus, whose bandwidth is significantly below the bandwidth required for this.
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`In the preferred embodiment of the invention the decoder/encoder 45 is
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`coupled to the memory 50 through a fast bus 70