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`Patent Number:
`
`Date of Patent:
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`5,812,789
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`Sep. 22, 1998
`
`[11]
`
`[45]
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`
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`
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`Galbi, D. et al., “An MPEG-1 Audio/Video Decoder With
`
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`
`
`
`
`Run-Length Compressed Antialiased Video Overlays,”
`
`
`
`
`1995 IEEE International Solid—State Circuits Conference,
`
`
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`
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`pp. 286-287, 381.
`
`
`
`Maturi, G., “Single Chip MPEG Audio Decoder,” IEEE
`
`
`
`
`
`
`
`
`Transactions on Consumer Electronics, vol. 38, No. 3, Aug.
`
`
`
`
`
`
`
`1992, pp. 348-356.
`
`
`
`Butler, B. and T. Mace, “The Great Leap Forward,” PC
`
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`
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`
`
`
`
`Magazine, Oct. 11, 1994, pp. 241-244, 246, 248, 250,
`
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`
`
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`
`
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`253-254, 256, 260-261, 264, 266-268, 273-275, 278.
`
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`
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`Doquilo, J., “Symmetric Multiprocessing Servers: Scaling
`
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`
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`the Performance Wall,” Infoworld, Mar. 27, 1995, pp.
`
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`
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`82-85, 88-92.
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`Video Electronics Standards Association, “VESA Unificd
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`Memory Architechture Hardware Specifications Proposal,”
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`Version: 1.0p, Oct. 31, 1995, pp. 1-38.
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`Video Electronics Standards Association, “VESA Unified
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`Memory Architecture VESABIOS Extensions VUMA-SBE
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`Proposal,” Version: 1.0p, Nov. 1, 1995, pp. 1-26.
`
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`
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`
`
`King, A., Inside Windows 95, Microsoft Press, Redmond,
`
`
`
`
`
`
`
`Washington, 1994, pp. 85-90.
`
`
`
`
`“MPEG Video Overview,” SGS-Thomson Microelectronics
`
`
`
`
`Technical Note, Apr. 1992, pp. 1-4.
`
`
`
`
`
`
`“On the Bus Arbitration for MPEG 2 Video Decoder” ; VLSI
`
`
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`
`
`
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`Tech, System and Application, 1995 Symposium.
`
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`“A Low Cost Graphics and Multimedia Workstation Chip
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`Set”; IEEE Micro, 1994.
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`Primary Examiher—Ellis B. Ramirez
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`Attorney, Agent, or Firm—David V. (Carlson; Theodore E.
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`Galanthay; Lisa K. Jorgenson
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`ABSTRACT
`
`[57]
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`An clcctronic system that contains a first dcvicc that requires
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`a memory interface and video and/or audio decompression
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`and/or compression device that shares a memory interface
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`and memory with the first device While still permitting the
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`video and/or audio decompression and/or compression
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`device to operate in real time is disclosed.
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`33 Claims, 5 Drawing Sheets
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`Bheda, II. and P. Srinivasan, “A lligh-Performance Cross-
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`Platform MPEG Decoder,” Digital Wdeo Compression on
`
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`
`Personal Computers.‘ Algorithms and Technologies. SPIE
`
`
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`
`
`Proceedings, Feb. 7-8, 1994, V0. 2187, pp. 241-248.
`
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`
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`Bursky, D., “Highly Integrated Controller Eases MPEG-2
`
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`Adoption,” Electronic Design, Aug. 21, 1995, vol. 43, No.
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`17, pp. 141-142.
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`14\
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`DECUDER
`
`VIDEO
`DECODING
`CIRCUIT
`
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`AUDIO
`
`DECODING
`CIRZIUII
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`INIEFFACE
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`FIRST DEVICE
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`60
`Q4
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`DMA ENGIIIE
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`\54
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`58, REFRESH LOGIC
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`MEMORY COMROLLER
`56/
`I/EMORY INTER:/«CE
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`United States Patent
`Diaz et al.
`
`
`
`[19]
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`
`[54]
`
`
`VIDEO AND/OR AUDIO DECOMPRESSION
`
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`
`AND/OR COMPRESSION DEVICE THAT
`
`
`
`
`SHARES A MEMORY INTERFACE
`
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`
`[75]
`
`
`Inventors: Raul Zcgcrs Diaz, Palo Alto; Jetfcrson
`
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`
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`Eugene Owen, Freemont, both of Calif.
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`[73]
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`Assignee: STMicr0electr0nics, Inc., Carrollton,
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`Tex.
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`
`
`[21]
`
`[32]
`
`[51]
`
`[52]
`
`[58]
`
`
`Appl. No.: 702,911
`
`
`
`Aug. 26, 1996
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`
`G06F 17/00
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`................. .. 395/200.77
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`Field of Search ....................... .. 395/200.77, 200.82,
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`395/507, 890, 729, 348/402, 407, 10
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`[56]
`
`
`References Cited
`
`
`U.S. PATENT DOCUMENTS
`
`
`
`9/1988
`Conforti
`.............................. . 395/729
`4,774,660
`1/1990
`
`
`
`
`
`4,894,565
`Marquardt ..
`395/729
`
`
`
`
`
`6/1991
`5,027,400
`..
`Baji et al.
`348/10
`
`
`
`
`
`12/1994
`Price et al.
`.
`.. 395/729
`5,371,893
`
`
`
`
`
`10/1995
`Scalise et al.
`.. 348/431
`5,459,519
`
`
`
`
`
`5/1996
`5,522,080
`Harney et al.
`.. 395/729
`
`
`
`
`
`9/1996
`Rcttcr ct al.
`.. 348/402
`5,557,533
`
`
`
`
`
`
`1/1997
`5,598,525
`Nally et al.
`.. 395/507
`
`
`
`
`
`4/1997
`.. 395/200.82
`Joh
`5,621,893
`4/1997
`
`
`
`
`
`5,623,672
`Poppat
`.. . .. . .
`.. . . .. 395/729
`
`
`
`
`
`FOREIGN PATENT DOCUMENTS
`
`
`9/1995 European Pat. Off.
`.
`
`
`
`
`OTHER PUBLICATIONS
`
`
`.
`.
`
`. .. . . .. . .. . .
`
`
`
`
`
`0 673 171 A2
`
`
`
`
`Samsung Exhibit 1001
`
`Page 1 of 13
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`
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`
`
`U.S. Patent
`
`
`
`
`Sep. 22, 1998
`
`
`Sheet 1 of 5
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`
`
`5,812,789
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`
`
`
`
`vIDEo DECODING
`
`CIRCUIT
`
`
`
`
`
`INTERFACE
`
`
`
`CONTROLLER
`
`MICRO— I I-2 I MEMORY
`I AUDIO DECODING I 1
`
`
`CIRCUIT
`-5
`
`I4
`
`E
`
`
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`
`
`
`
`FIG.
`7 0.
`
`
`(PRIOR ART)
`
`
`VIDEO DECODING
`CIRCUIT
`
`
`
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`
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`
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`M
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`7 b
`FIG.
`
`
`(PRIOR ART)
`
`Page2 of 13
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`
`I 12 I
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`
`I AUDIO DECODING I
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`CIRCUIT
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`I4
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`Page 2 of 13
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`U.S. Patent
`
`Sep. 22, 1998
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`Sheet 2 0f5
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`5,812,789
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`2
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`added to allow the system to compress video and/or audio
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`sequences, to be transmitted or stored. Both need to be added
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`for two way communication such as video telephony.
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`A typical decoder, such as an MPEG decoder 10 shown in
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`FIG. 1a, contains video decoding circuitry 12, audio decod-
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`ing circuitry 14, a microcontroller 16, and a memory inter-
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`face 18. The decoder can also contain other circuitry
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`depending on the electronic system the decoder is designed
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`to operate in. For example, when the decoder is designed to
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`operate in a typical television the decoder will also contain
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`an on screen display (OSD) circuit.
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`FIG. 1b shows a better decoder architecture, used in the
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`STi3520 and STi3520A MPEG Audio/MPEG-2 Video Inte-
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`grated Decoder manufactured by SGS-THOMSON Micro-
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`electronics. The decoder has a register interface 20 instead
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`of a microcontroller. The register interface 20 is coupled to
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`an external microcontroller 24. The use of a register inter-
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`face 20 makes it possible to tailor the decoder 10 to the
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`specific hardware the decoder 10 interfaces with or change
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`its operation without having to replace the decoder by just
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`reprogramming the register interface. It also allows the user
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`to replace the microcontroller 24, to upgrade or tailor the
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`microcontroller 24 to a specific use, by just replacing the
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`microcontroller and reprogramming the register interface
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`20, without having to replace the decoder 10.
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`The memory interface 18 is coupled to a memory 22. A
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`typical MPEG decoder 10 requires 16 Mbits of memory to
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`operate in the main profile at main level mode (MP at ML).
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`This typically means that the decoder requires a 2 Mbyte
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`memory. Memory 22 is dedicated to the MPEG decoder 10
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`and increases the price of adding a decoder 10 to the
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`electronic system. In current technology the cost of this
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`additional dedicated memory 22 can be a significant per-
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`centage of the cost of the decoder.
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`An encoder also requires a memory interface 18 and
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`dedicated memory. Adding the encoder to an electronic
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`system again increases the price of the system by both the
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`price of the encoder and its dedicated memory.
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`A goal in the semiconductor industry is to reduce the die
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`area of an integrated circuit device for a given functionality.
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`Some advantages of reducing the die area is the increase in
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`the number of the die that can be manufactured on same size
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`silicon wafer, and the reduction in price per die resulting
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`therefrom. This results in both an increase in volume and
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`reduction in price of the device.
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`Many of the functional circuits described above for FIG.
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`1a and FIG. 1b take up a lot of die space. However, each of
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`them is needed to make the respective decoder operate.
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`FIG. 1c shows a computer 25 containing a decoder 10, a
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`main memory 168 and other typical components such as a
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`modem 199, and graphics accelerator 188. The decoder 10
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`and the rest of the components are coupled to the core logic
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`chipset 190 through a bus 170. The bus is typically a PCI
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`(peripheral component interface) or ISA (industry standard
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`architecture) bus, and each component contains an appro-
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`priate interface for interfacing with the bus.
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`When any component needs access to the memory 168
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`either to read from or write to the main memory 168, it
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`generates a request which is placed on the bus 26. When the
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`request is a write the data to be written is also placed on the
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`bus 26. The request is processed in the core logic chipset 190
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`and the data is then either written to or read from the main
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`memory 168. When data is read from the main memory 168
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`the data is now placed on the bus and goes to the component
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`that requested the read.
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`There are typically many components in the computer
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`systems that may require access to the main memory 168,
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`1
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`VIDEO AND/OR AUDIO DECOMPRESSION
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`AND/OR COMPRESSION DEVICE THAT
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`SHARES A MEMORY INTERFACE
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`
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`CROSS-REFERENCE TO RELATED
`
`
`APPLICATIONS
`
`
`This application contains some text and drawings in
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`common with pending U.S. patent applications entitled:
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`“Video and/or Audio Decompression and/or Compression
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`
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`Device that Shares a Memory” by Jefferson E. Owen, Raul
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`Z. Diaz, and Osvaldo Colavin Ser. No. 08/702,910 filed on
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`Aug. 26, 1996, and has the same effective filing date and
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`ownership as the present application, and to that extent is
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`related to the present application, which is incorporated
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`herein by reference.
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`BACKGROUND
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`The present invention relates to the field of electronic
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`systems having a video and/or audio decompression and/or
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`compression device, and is more specifically directed to
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`sharing a memory interface between a video and/or audio
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`decompression and/or compression device and another
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`device contained in the electronic system.
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`The size of a digital representation of uncompressed video
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`images is dependent on the resolution, and color depth of the
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`image. Amovie composed of a sequence of such images, and
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`the audio signals that go along with them, quickly becomes
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`large enough so that uncompressed such a movie typically
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`cannot fit entirely onto conventional recording medium,
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`such as a CD. It is also typically now prohibitively expen-
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`sive to transmit such a movie uncompressed.
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`It is therefore advantageous to compress video and audio
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`sequences before they are transmitted or stored. A great deal
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`of effort is being expanded to develop systems to compress
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`these sequences. There are several coding standards cur-
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`rently used that are based on the discrete cosine transfer
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`algorithm including MPEG-1, MPEG-2, H.261, and H.263.
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`(MPEG stands for “Motion Picture Expert Group”, a com-
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`mittee of the International Organization for Standardization,
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`ISO.) The MPEG-1, MPEG-2, H.261, and H.263 standards
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`are decompression protocols that describe how an encoded
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`bitstream is to be decoded. The encoding can be done in any
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`manner, as long as the resulting bitstream complies with the
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`standard.
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`Video and/or audio compression devices (hereinafter
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`encoders) are used to encode the video and/or audio
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`sequence before it is transmitted or stored. The resulting
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`bitstream is decoded by a video and/or audio decompression
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`device (hereinafter decoder) before the video and/or audio
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`sequence is displayed. However, a bitstream can only be
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`decoded by a decoder if it complies to the standard used by
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`the decoder. To be able to decode the bitstream on a large
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`number of systems it is advantageous to encode the video
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`and/or audio sequences to comply to a well accepted decom-
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`pression standard. The MPEG standards are currently well
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`accepted standards for one way communication. H.261, and
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`H.263 are currently well accepted standards for video tele-
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`phony.
`Once decoded the images can be displayed on an elec-
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`tronic system dedicated to displaying video and audio, such
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`as television or digital video disk (DVD) player, or on
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`electronic systems where image display is just one feature of
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`the system, such as a computer. A decoder needs to be added
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`to these systems to allow them to display compressed
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`sequences, such as received images and associated audio, or
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`ones taken from a storage device. An encoder needs to be
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`Page 7 of 13
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`4
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`and/or compression device shares a memory interface and
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`the memory with the first device. In the preferred embodi-
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`ment of the invention the shared memory interface contains
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`an arbiter. The arbiter and DMA engines of the video and/or
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`audio decompression and/or compression device and of the
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`first device are configured to arbitrate between the two
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`devices when one of them is requesting access to the
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`memory. This allows the use of one memory interface to
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`control the access of both the video and/or audio decom-
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`pression and/or compression device and the first device to
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`the memory.
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`When the video and/or audio decompression and/or com-
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`pression device used in an electronic system, such as a
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`computer, already containing a device that has a memory
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`interface the video and/or audio decompression and/or com-
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`pression device can share that memory interface and the
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`memory of the device and the memory interface and
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`memory of the video and/or audio decompression and/or
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`compression device can be eliminated. Eliminating this
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`memory interface reduces the die area without changing the
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`critical dimensions of the device. Therefore increasing the
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`volume and reducing the cost of the decoder or encoder.
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`Eliminating the memory greatly reduces the cost of adding
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`the video and/or audio decompression and/or compression
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`device to the electronic system while not requiring the video
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`and/or audio decompression and/or compression device to
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`be connected to the system bus, allowing the video and/or
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`audio decompression and/or compression device to operate
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`in real time.
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`An advantage of the present invention is significant cost
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`reduction due to the fact that the video and/or audio decom-
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`pression and/or compression device does not need its own
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`dedicated memory but can share a memory with another
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`device and still operate in real time.
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`Another significant advantage of the present invention is
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`that the die space needed for the video and/or audio decom-
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`pression and/or compression device is smaller because the
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`memory interface on the video and/or audio decompression
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`and/or compression device is eliminated.
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`A further advantage of the present invention is that the
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`video and/or audio decompression and/or compression
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`device can share the memory of the device with which it is
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`sharing the memory interface more efficiently.
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`Another advantage of the present invention is that the cost
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`of producing a video and/or audio decompression and/or
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`compression device is reduced because the memory inter-
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`face on the video and/or audio decompression and/or com-
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`pression device is eliminated.
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`Another advantage of the present invention is that the
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`video and/or audio decompression and/or compression
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`device can be monolithically integrated into the first device
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`and no extra packaging or pins are needed for the video
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`and/or audio decompression and/or compression device, and
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`no pins are needed for the first device to connect to the video
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`and/or audio decompression and/or compression device,
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`saving pins on both devices and producing a better connec-
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`tion between the two devices.
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`Other advantages and objects of the invention will be
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`apparent to those of ordinary skill in the art having reference
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`to the following specification together with the drawings.
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`FIGS. la and 1b are electrical diagrams, in block form, of
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`prior art decoders.
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`FIG. 1c is an electrical diagram, in block form, of a
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`computer system containing a decoder according to the prior
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`art.
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`5,812,789
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`3
`and they are typically all coupled to the same bus 174, or
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`possibly several buses 170, 198 connected together by a PCI
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`bridge 192, if there are not enough connectors on one bus to
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`accommodate all of the peripherals. However, the addition
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`of each bus is very expensive. Each request is typically
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`processed according to a priority scheme. The priority
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`scheme is typically based on the priority given to the device
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`and the order in which the requests are received. Typically,
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`the priority scheme is set up so no device monopolizes the
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`bus, starving all of the other devices. Good practice suggests
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`that no device on the bus require more than approximately
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`50% of the bus’s bandwidth.
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`The minimum bandwidth required for the decoder 10 can
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`be calculated based on the characteristics and desired opera-
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`tion of the decoder. These characteristics include the stan-
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`dard to which the bitstream is encoded to comply with,
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`whether the decoder is to operate in real time, to what extent
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`frames are dropped, and how the images are stored.
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`Additionally, the latency of the bus that couples the decoder
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`to the memory should be considered.
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`If the decoder does not operate in real time the decoded
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`movie would stop periodically between images until the
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`decoder can get access to the memory to process the next
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`image. The movie may stop quite often between images and
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`wait.
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`To reduce the minimum required bandwidth and still
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`operate in real time,
`the decoder 10 may need to drop
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`frames. If the decoder 10 regularly does not decode every
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`frame then it may not need to stop between images.
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`However, this produces very poor continuity in the images.
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`This is problematic with an image encoded to the MPEG-1
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`or MPEG-2 standard, or any standards that uses temporal
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`compression. In temporal (interpicture) compression some
`of the images are decoded based on previous images and
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`some based on previous and future images. Dropping an
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`image on which the decoding of other images is based is
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`unacceptable and will result in many poor or even com-
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`pletely unrecognizable images.
`The computer can also contain both a decoder and
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`encoder to allow for video telephony, as described above. In
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`this case not operating in real time would mean that the
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`length of time between the occurrence of an event, such as
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`speaking, at one end of the conversation until the event is
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`displayed at the other end of the conversation is increased by
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`the time both the encoder and then the decoder must wait to
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`get access to the bus and the main memory. Not being able
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`to operate in real time means that there would be gaps in the
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`conversation until
`the equipment can catch up. This
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`increases the time needed to have a video conference, and
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`makes the conference uncomfortable for the participants.
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`One widely used solution to allow a component in a
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`computer system to operate in real
`time is to give the
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`component its own dedicated memory. Thus, as shown in
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`the decoder 10 can be given its own dedicated
`FIG. 1c,
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`memory 22, with a dedicated bus 26 to connect the decoder
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`10 to its memory 22. The dedicated memory 22, its con-
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`troller and the pins to control this memory significantly
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`increase the cost of adding a decoder 10 to the computer.
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`SUMMARY OF THE INVENTION
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`The present application discloses an electronic system
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`that contains a first device and video and/or audio decom-
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`pression and/or compression device capable of operating in
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`real time. Both the first device and the video and/or audio
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`decompression and/or compression device require a
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`memory interface. The video and/or audio decompression
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`Page 8 of 13
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`Page 8 of 13
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`5,812,789
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`5
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`FIG. 2 is an electrical diagram,
`in block form, of an
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`electronic system containing a device having a memory
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`interface and an encoder and decoder.
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`FIG. 3 is an electrical diagram,
`in block form, of a
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`computer system containing a core logic chipset designed
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`for the CPU to share a memory interface with an encoder
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`and decoder.
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`in block form, of a
`FIG. 4 is an electrical diagram,
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`computer system containing a graphics accelerator designed
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`to share a memory interface with an encoder and/or decoder.
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`DETAILED DESCRIPTION OF THE
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`PREFERRED EMBODIMENT
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`FIG. 2 shows an electronic system 40 containing a first
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`device 42 having access to a memory 50 through a memory
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`interface 48, and a decoder 44 and encoder 46, having access
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`to the same memory 50 through the same memory interface
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`48. First device 42 can be a processor, a core logic chipset,
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`a graphics accelerator, or any other device that requires
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`access to the memory 50, and either contains or is coupled
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`to a memory interface. Any parts common to FIGS. 1
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`through 4 are indicated using the same numbering system. In
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`the preferred embodiment of the invention, electronic sys-
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`tem 40 contains a first device 42, a decoder 44, an encoder
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`46, a memory interface 48, and a memory 50. Although,
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`either the decoder 44 or encoder 46 can be used in the
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`decoder/encoder 45 without the other. For ease of reference,
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`a video and/or audio decompression and/or compression
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`device 45 will hereinafter be referred to as decoder/encoder
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`45. The decoder/encoder 45 may be a single device, or cell
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`on an integrated circuit, or may be two separate devices, or
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`cells in an integrated circuit. In the preferred embodiment of
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`the invention, the first device 42, decoder/encoder 45, and
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`memory interface 48 are on one integrated circuit, however,
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`they can be on separate integrated circuits in any combina-
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`tion.
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`The decoder 44 includes a video decoding circuit 12 and
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`an audio decoding circuit 14, both coupled to a register
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`interface 20. The decoder 44 can be either a video and audio
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`decoder, just a video, or just an audio decoder. If the decoder
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`44 is just a video decoder it does not contain the audio
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`decoding circuitry 14. The audio decoding can be performed
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`by a separate audio codec coupled to the first device 42, or
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`through software.
`In the preferred embodiment of the
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`invention, when the decoder/encoder 45 is in a system
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`containing a processor and is coupled to the processor, the
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`audio decoding is performed in software. This frees up space
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`on the die without causing significant delay in the decoding.
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`If the audio decoding is performed in software, the processor
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`should preferably operate at a speed to allow the audio
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`decoding to be performed in real time without starving other
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`components of the system that may need to utilize the
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`processor. For example, currently software to perform AC-3
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`audio decoding takes up approximately 40% of the band-
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`width of a 133 MHZ Pentium. The encoder 46 includes a
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`video encoding circuit 62 and an audio encoding circuit 64,
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`both coupled to a register interface 20. The encoder 46 can
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`be either a video and audio encoder, just a video, or just an
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`audio encoder. If the encoder 46 is just a video encoder, it
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`does not contain the audio encoding circuitry 64. The audio
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`encoding can be performed by a separate audio codec
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`coupled to the first device 42, or through software. In the
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`preferred embodiment of the invention, when the decoder/
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`encoder 45 is in a system containing a processor and is
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`coupled to the processor, the audio encoding is performed in
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`software presenting the same advantages of freeing up space
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`Page 9 of 13
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`6
`on the die without causing significant delay in the encoding.
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`The register interfaces 20 of the decoder 44 and encoder 46
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`are coupled to a processor.
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`The decoder 44 and encoder 46 are coupled to the direct
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`memory access (DMA) engine 52. The decoder and encoder
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`can be coupled to the same DMA engine as shown in FIG.
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`2, or each can have its own DMA engine, or share a DMA
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`engine with another device. When the decoder/encoder 45
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`are two separate devices or cells, decoder 44 and encoder 46
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`can still be coupled to one DMA engine 52. When the
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`decoder/encoder is one device or is one cell on an integrated
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`circuit, the DMA engine 52 can be part of the decoder/
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`encoder 45, as shown in FIG. 2. The DMA engine 52 is
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`coupled to the arbiter 54 of the memory interface 48.
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`The first device 42 also contains a DMA engine 60. The
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`DMA engine 60 of the first device 42 is coupled to the arbiter
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`54 of the memory interface 48. The arbiter is also coupled
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`to the refresh logic 58 and the memory controller 56. The
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`memory interface 48 is coupled to a memory 50. The
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`memory controller 56 is the control logic that generates the
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`address the memory interface 48 accesses in the memory 50
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`and the timing of the burst cycles.
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`In current technology, memory 50 is typically a DRAM.
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`However, other types of memory can be used. The refresh
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`logic 58 is needed to refresh the DRAM. However, as is
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`known in the art, if a different memory is used, the refresh
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`logic 58 may not be needed and can be eliminated.
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`The decoder/encoder 45 is coupled to the memory 50
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`through devices, typically a bus 70, that have a bandwidth
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`greater than the bandwidth required for the decoder/encoder
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`45 to operate in real time. The minimum bandwidth required
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`for the decoder/encoder 45 can be calculated based on the
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`characteristics and desired operation of the decoder, includ-
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`ing the standard to which the bitstream is encoded to comply
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`with, whether the decoder/encoder 45 is to operate in real
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`time, to what extent frames are dropped, and which images
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`are stored. Additionally,
`the latency of the bus 70 that
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`couples the decoder/encoder 45 to the memory 50 should be
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`considered.
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`A goal is to have the decoder/encoder 45 operate in real
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`time without dropping so many frames that
`it becomes
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`noticeable to the human viewer of the movie. To operate in
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`real time the decoder/encoder 45 should decoder and/or
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`encode images fast enough so that any delay in deco