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`Paper No.
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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`_____________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`_____________________
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`
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`APPLE INC., HTC CORPORATION, AND HTC AMERICA INC.,
`Petitioners,
`
`v.
`
`PARTHENON UNIFIED MEMORY ARCHITECTURE LLC,
`Patent Owner
`
`_____________________
`
`
`
`Case IPR2016-00923
`Patent No. 5,812,789
`
`_____________________
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`
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`PETITIONER’S REPLY
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`Petitioner’s Reply
`IPR2016-00923 (Patent No. 5,812,789)
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`TABLE OF CONTENTS
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`I.
`
`II.
`
`Introduction ...................................................................................................... 1
`
`Lambrecht anticipates each and every limitation recited in
`claims 1, 3, 5, 11, and 13. ................................................................................ 2
`
`A.
`
`Lambrecht anticipates “a shared bus . . . having a
`sufficient bandwidth to enable the decoder to access the
`memory and operate in real time.” ........................................................ 3
`
`1.
`
`2.
`
`in Fig. 21 of Lambrecht
`The PCI bus
`communicates data between the memory and the
`multimedia devices when in the multimedia mode. ................... 3
`
`No additional logic is needed in the PCI bridge
`chipset in Fig. 21 for the multimedia devices
`communicate data
`to
`the main memory
`in
`multimedia mode.......................................................................12
`
`Lambrecht anticipates “a decoder that requires access to
`the memory sufficient to maintain real time operation.” ....................14
`
`Lambrecht anticipates “a shared bus . . . having sufficient
`bandwidth to enable the decoder to access the memory
`and operate in real time.” ....................................................................17
`
`Lambrecht anticipates “the bus having a sufficient
`bandwidth to enable the decoder to access the memory
`and operate
`in real
`time when
`the first device
`simultaneously accesses the bus.” .......................................................20
`
`B.
`
`C.
`
`D.
`
`III. The combination of Lambrecht and Artieri renders claim 4
`obvious. ..........................................................................................................22
`
`IV. The combination of Lambrecht and Moore renders claim 6
`obvious. ..........................................................................................................23
`
`V.
`
`Conclusion .....................................................................................................24
`
`VI. Certificate of Word Count .............................................................................25
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`i
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`Petitioner’s Reply
`IPR2016-00923 (Patent No. 5,812,789)
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`PETITIONER’S UPDATED EXHIBIT LIST
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`February 24, 2017
`
`Description
`Exhibit
`Ex. 1001 U.S. Patent No. 5,812,789 (“the ’789 patent”)
`Ex. 1002 File History for U.S. Patent No. 5,812,789
`Ex. 1003 Reserved
`Ex. 1004
`ISO/IEC 11172-2: 1993: Information technology—Coding of moving
`pictures and associated audio for digital storage media at up to about
`1,5 Mbit/s—Part 2: Video, (1st ed. August 1, 1993) (“MPEG
`Standard”)
`Ex. 1005 S. Rathnam et al., “An Architectural Overview of the Programmable
`Multimedia Processor, TM-1,” IEEE Proceedings of COMPCON ’96,
`pp. 319-326 (1996) (“Rathnam”)
`Ex. 1006 R.J. Gove, “The MVP: A Highly-Integrated Video Compression
`Chip,” Proceedings of the IEEE Data Compression Conference (DCC
`’94), pp. 215-224 (March 29-31, 1994)
`Ex. 1007 U.S. Patent No. 5,774,676 (“Stearns”)
`Ex. 1008 Reserved
`Ex. 1009 Reserved
`Ex. 1010 WorldCat Entry for Rathnam
`Ex. 1011 Patent Owner Claim Construction Brief in Case No. 2: 14-cv-690,
`April 7, 2015
`Ex. 1012 Patent Owner Claim Construction Brief in Case No. 2: 14-cv-902, June
`18, 2015
`Ex. 1013 Reserved
`Ex. 1014 Brad Hansen, The Dictionary of Multimedia, 1997
`Ex. 1015 U.S. Patent No. 8,681,164
`Ex. 1016 Excerpt of File History for U.S. Patent No. 8,681,164
`Ex. 1017 Reserved
`
`
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`ii
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`Petitioner’s Reply
`IPR2016-00923 (Patent No. 5,812,789)
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`Description
`
`Exhibit
`Ex. 1018 Reserved
`Ex. 1019 Shanley, et al., “PCI System Architecture,”’ Addison-Wesley
`Publishing Company, 1995 (3rd ed.) (“Shanley”)
`Ex. 1020 Stone, H., “Microcomputer Interfacing,” Addison-Wesley Publishing
`Company, 1982
`Ex. 1021 Reserved
`Ex. 1022 Reserved
`Ex. 1023 U.S. Patent No. 5,797,028 (“Gulick 028”)
`Ex. 1024
`“Accelerated Graphics Port Interface Specification,” Intel Corporation,
`July 31, 1996 (Revision 1.0) (“AGP”)
`Ex. 1025 VESA Unified Memory Architecture Hardware Specifications
`Proposal, Version 1.0p (“VUMA”)
`Ex. 1026 Reserved
`Ex. 1027 Reserved
`Ex. 1028 Reserved
`Ex. 1029 Curriculum Vitae of Dr. Harold Stone
`Ex. 1030 Expert Declaration of Dr. Harold Stone (“Stone Decl.”)
`Ex. 1031 Reserved
`Ex. 1032 U.S. Patent No. 5,682,484 (“Lambrecht”)
`Ex. 1033 Reserved
`Ex. 1034 Slavenburg, G., “The TriMedia VLIW-Based PCI Multimedia
`Processor,” Microprocessor Forum 1995, Oct. 10-11, 1995
`(“Slavenburg”)
`Ex. 1035 G. Moore, “Cramming more components onto integrated circuits,”
`Electronics, Vol. 38, No. 8, Apr. 19, 1965 (“Moore”)
`Ex. 1036 U.S. Patent No. 5,579,052 (“Artieri”)
`Ex. 1037 Reserved
`Ex. 1038 Reserved
`Ex. 1039 Reserved
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`Petitioner’s Reply
`IPR2016-00923 (Patent No. 5,812,789)
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`Description
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`Exhibit
`Ex. 1040 Reserved
`Ex. 1041 Declaration of Curt Holbreich in Support of Motion for Pro Hac Vice
`Admission
`Ex. 1042 Declaration of Yakov Zolotorev in Support of Motion for Pro Hac
`Vice Admission
`Ex. 1043 Deposition Transcript of Dr. Mitchell A. Thornton
`Ex. 1044 Second Expert Declaration of Harold S. Stone, Ph.D.
`Ex. 1045 U.S. Patent No. 5,461,679 (“Normile”)
`Ex. 1046 Errata sheet for Deposition of Dr. Stone included as Ex. 2004
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`iv
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`Introduction
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`I.
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`Petitioner’s Reply
`IPR2016-00923 (Patent No. 5,812,789)
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`The Petition and the record as a whole provides detailed reasons why a
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`person of skill in the art (“POSITA”) would have understood Lambrecht to either
`
`anticipate or render obvious (in combination) each and every limitation of the
`
`challenged claims of the ’789 patent. None of Patent Owner’s arguments overcome
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`the express teachings of Lambrecht.
`
`Patent Owner’s primary argument is that the PCI bus in Lambrecht’s Fig. 21
`
`is not capable of communicating data between the multimedia devices (including a
`
`decoder) and the main system memory. This argument, though, is predicated on
`
`misunderstandings regarding the express teachings of Lambrecht and the state of
`
`the art at the time of the ’789 patent.
`
`First, Patent Owner attempts to impose limitations on the teachings of Fig.
`
`21 by importing characteristics described in other, distinct embodiments into the
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`disclosures related to Fig. 21. But, as discussed below, Patent Owner
`
`misapprehends the teachings and disclosures of Lambrecht, while simultaneously
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`rendering the teachings with respect Fig 21 redundant and nonsensical.
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`Second, Patent Owner argues that the chipset that communicates with the
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`PCI bus in Lambrecht’s Fig. 21 would require additional, special circuitry to
`
`operate. But, as discussed below, such argument contradicts the teachings in
`
`Lambrecht. No such special circuitry is required.
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`1
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`IPR2016-00923 (Patent No. 5,812,789)
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`Third, Patent Owner incorrectly argues that the video decoder disclosed in
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`
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`
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`Lambrecht would not access the main memory because, at the time of Lambrecht,
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`all video decoders included dedicated memory. As discussed below, this is a
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`misunderstanding of the state of the art—POSITAs at the time knew that video
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`decoders could directly access the main memory instead of requiring dedicated
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`memory.
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`Finally, Patent Owner raises other arguments regarding the whether the
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`system in Lambrecht has sufficient bandwidth to maintain realtime operation and
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`whether multimedia devices can use the shared bus simultaneously. Both of these
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`arguments are incorrect as they fail to properly consider the teachings of
`
`Lambrecht and the knowledge of a POSITA.
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`In sum, Patent Owner’s arguments are unpersuasive. Lambrecht anticipates
`
`claims 1, 3, 5, 11, and 13 and renders obvious claim 4 (in combination with
`
`Artieri) and claim 6 (in combination with Moore). For the reasons shown in the
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`Petition and below, claims 1, 3-6, 11, and 13 of the ’789 patent are unpatentable.
`
`II. Lambrecht anticipates each and every limitation recited in claims 1, 3,
`5, 11, and 13.
`
`Patent Owner argues that Lambrecht does not anticipate each and every
`
`limitation of claims 1, 3, 5, 11, and 13. Patent Owner, however, focuses its
`
`arguments solely certain limitations of claim 1.
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`2
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`Petitioner’s Reply
`IPR2016-00923 (Patent No. 5,812,789)
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`A. Lambrecht anticipates “a shared bus . . . having a sufficient
`bandwidth to enable the decoder to access the memory and
`operate in real time.”
`
`
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`Patent Owner argues that Lambrecht does not anticipate “a shared bus . . .
`
`having a sufficient bandwidth to enable the decoder to access the memory and
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`operate in real time,” as recited in claim 1 of the ’789 patent, because Lambrecht
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`allegedly fails to teach a bus that allows a decoder to access the memory and
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`operate in real time. Response, Paper No. 22, at 6. Patent Owner’s argument fails
`
`because it ignores Lambrecht’s express teachings of Fig. 21, and improperly
`
`incorporates purported technical limitations from other embodiments taught in
`
`Lambrecht.
`
`1.
`
`The PCI bus in Fig. 21 of Lambrecht communicates data
`between the memory and the multimedia devices when in
`the multimedia mode.
`
`Lambrecht is directed to “[a] computer system optimized for real-time
`
`applications which provides increased performance over current computer
`
`architectures.” Ex. 1032, Abstract. Lambrecht’s computer system achieves this
`
`increased performance by including “a standard local system bus, such as the PCI
`
`bus” and also including “a dedicated real-time bus or multimedia bus.” Id. This
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`allows “multimedia devices such as video cards, audio cards, etc.” to transfer real-
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`time data through the bus. Id. As a result, the computer system “provides much
`
`greater performance for real-time applications than prior systems.” Id.
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`3
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`Petitioner’s Reply
`IPR2016-00923 (Patent No. 5,812,789)
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`The embodiment in Fig. 21 describes a system to achieve the express
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`
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`
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`purpose of Lambrecht:
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`
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`Id., Fig. 21 (annotated).
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`The computer system of Fig. 21, specifically referenced in the Petition,
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`discloses a computer system that “includes an expansion bus, preferably a PCI bus
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`120, and which includes mode logic which selects between different modes of the
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`PCI bus 120.” Id. at 26:48-51. The mode logic, contained within the PCI bridge
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`chipset, “is operable to place the PCI bus 120 in either a normal PCI mode or in a
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`real-time/multimedia mode optimized for multimedia transfers of periodic data.”
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`Id. at 26:53-56. The computer system in Fig. 21 also includes multimedia devices
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`142D-146D that:
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`communicate with each other and with the CPU 102 and main
`memory 110 via the PCI bus 120, as is well known in the art. The
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`IPR2016-00923 (Patent No. 5,812,789)
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`multimedia devices 142D-146D also communicate data between using
`the PCI bus signal lines 120 when the PCI bus 120 is in the
`multimedia mode.
`Id. at 27:57-62 (emphasis added). In this way, the Fig. 21 embodiment includes a
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`
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`PCI bus (i.e., a shared bus) that has sufficient bandwidth to enable the multimedia
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`devices (including a decoder) to access the memory and operate in real time.
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`Patent Owner, however, argues that the multimedia devices 142D-146D in
`
`Lambrecht’s Fig. 21 are not able to access the main memory when the PCI bus 120
`
`is in “multimedia mode.” Response at 6-8. Patent Owner’s reasoning is that,
`
`because Lambrecht states that Fig. 21 is “similar” to Fig. 1, the portions of
`
`Lambrecht that describe Fig. 1 automatically and unequivocally apply to Fig. 21.
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`Id. But “similar” does not mean identical, as Patent Owner essentially argues, and
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`its attempt to limit the disclosure of Fig. 21 by improperly importing limitations of
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`Fig. 1 and other embodiments into its disclosures fails.
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`In describing Fig. 1, Lambrecht states that “the multimedia devices 142-146
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`communicate with each other via the PCI bus 120 and also communicate with the
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`CPU and main memory 110 via the PCI bus 120” and that “[t]he multimedia
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`devices 142-146 also communicate data between each other using the real-time bus
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`or multimedia bus 130.” Ex. 1032 (Lambrecht) at 8:20-25. Patent Owner and its
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`expert, Dr. Thornton, thus conclude, based solely on the disclosure with reference
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`to Fig. 1, that the multimedia mode in Fig. 21 is the same as the multimedia bus
`5
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`Petitioner’s Reply
`IPR2016-00923 (Patent No. 5,812,789)
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`130 in Fig. 1, and therefore operates in exactly the same manner to only
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`
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`communicate data between multimedia devices. Response at 7-8 (citing Ex. 2003
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`(Thornton Decl.) ¶ 41). Patent Owner’s reliance on the description of Fig. 1,
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`however, is incorrect because it ignores the entire description of Fig. 21 as well as
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`Lambrecht’s other teachings. See Ex. 1044 (Stone decl.) ¶ 2.
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`As seen in the comparison below, Fig. 21 differs from Fig. 1 in significant
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`ways. Fig. 1 has two individualized buses (a real-time bus and a PCI expansion
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`bus), whereas Fig. 21 has (i) a single PCI bus 120 that provides real-time data
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`transfer and (ii) additional mode logic in the PCI bridge chipset 106.
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`Ex. 1032, Fig. 21
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`Ex. 1032, Fig. 1
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`
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`The mode logic “is operable to place the PCI bus 120 in either a normal PCI
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`mode or in a real-time/multimedia mode optimized for multimedia transfers of
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`periodic data.” Ex. 1032 at 26:53-56. This allows the multimedia devices to
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`IPR2016-00923 (Patent No. 5,812,789)
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`“communicate with each other and with the CPU 102 and main memory 110 via
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`the PCI bus 120, as is well known in the art.” Id. at 27:57-59 (emphasis added).
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`The mode logic also allows the multimedia devices to communicate data “using
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`the PCI bus signal lines 120 when the PCI bus 120 is in the multimedia mode.” Id.
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`at 27:59-62 (emphasis added). Thus, Lambrecht literally teaches that the PCI bus
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`provides for real-time multimedia data transfers and communicating between the
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`multimedia devices and the main memory via the PCI bus. See Ex. 1044 ¶ 4.
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`Accordingly, Patent Owner’s argument—that the limited functionality of the
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`separate real-time bus of Fig 1 somehow transfers its limited functionality to the
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`multimedia mode of the PCI in Fig. 21—is simply conjecture, while contradicting
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`the actual teachings with respect to Fig. 21.
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`Moreover, there is nothing in reference to Fig. 21 that restricts the
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`multimedia mode of the PCI bus 120 to data communication only between
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`multimedia devices. See Ex. 1044 ¶ 5. Instead, the computer system in Fig. 21
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`provides an optional multimedia bus 130 “to augment or supplement the PCI bus
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`120 when the PCI bus 120 is in multimedia mode.” Ex. 1032 at 27:30-31. This
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`optional multimedia bus 130 is included so that the multimedia devices can
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`“communicate data between each other using the real-time bus or multimedia bus
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`130. When the multimedia devices 142-146 communicate using the real-time bus
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`130, the devices are not required to obtain PCI bus mastership and they consume
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`7
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`Petitioner’s Reply
`IPR2016-00923 (Patent No. 5,812,789)
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`little or no PCI bus cycles.” Id. at 8:24-28 (referencing Fig. 1). Thus, including the
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`optional multimedia bus 130 into the Fig. 21 embodiment provides a second bus
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`dedicated to enabling the multimedia devices to “communicate data between each
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`other” so that “the devices are not required to obtain PCI bus mastership and they
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`consume little or no PCI bus cycles” on the PCI bus 120. See id. at 8:24-28; Ex.
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`1044 ¶ 5.
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`Patent Owner’s argument that the PCI bus 120 is restricted to only
`
`communicate data between multimedia devices when in the multimedia mode
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`would make the optional inclusion of the multimedia bus 130 redundant and
`
`unnecessary. See Ex. 1044 ¶ 6. Under Patent Owner’s theory, the multimedia mode
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`of the PCI bus 120 would allegedly provide data communication only between the
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`multimedia devices, which would be the identical function of the optional
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`multimedia bus 130 (which provides data communication only between the
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`multimedia devices). See id. This is contrary to the express purpose of Lambrecht.
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`See id. Such a configuration would provide data communication only between the
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`multimedia devices via multimedia bus 130 while also consuming cycles on PCI
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`bus 120 in order to perform the exact same function of communicating data only
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`between the multimedia devices. See id.
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`Additionally, contrary to Patent Owner’s argument that the multimedia bus
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`130 can only be used to communicate between multimedia devices, other
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`Petitioner’s Reply
`IPR2016-00923 (Patent No. 5,812,789)
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`embodiments of Lambrecht disclose the opposite. In particular, the embodiment in
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`Fig. 6, shown below, is similar to Fig. 1 except that the multimedia bus in Fig. 6 is
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`not only connected to the multimedia devices but is also connected to the PCI
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`bridge chipset that connects the CPU and memory. Ex. 1032 at 12:22-25.
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`Ex. 1032, Fig. 6
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`Ex. 1032, Fig. 1
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`
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`The additional connection of the multimedia bus to the chipset in Fig. 6 is “to
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`accommodate peripheral device accesses through the real-time bus 130A and
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`chipset logic 106A to main memory 110.” Id. at 12:29-31 (emphasis added). In
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`other words, in Fig. 6, “one or more of the multimedia devices 142-146 can use the
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`multimedia bus 130A to interface through the chipset logic 106A to the main
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`memory 110 as desired.” Ex. 1032 at 12:43-45 (emphasis added). Thus, despite
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`Patent Owner’s argument to the contrary, Lambrecht does in fact teach that when
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`the multimedia bus is connected to the PCI bridge chipset, it can be used to
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`Petitioner’s Reply
`IPR2016-00923 (Patent No. 5,812,789)
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`communicate data between the multimedia devices and the CPU and memory in
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`real-time. Ex. 1044 ¶ 8.
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`Patent Owner does not reference this aspect of the multimedia bus in Fig. 6
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`in its Response but instead focuses exclusively on the more limiting embodiment
`
`of Fig. 1. Moreover, in preparing his declaration, Patent Owner’s expert
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`acknowledged that he never considered the embodiment in Fig. 6 but “only used
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`Figure 1 and Figure 21” in forming his opinion. Ex. 1043 (Thornton Depo.) at p.79
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`ln.15-16.
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`Further, Patent Owner’s argument is contrary to the disclosed purpose of the
`
`invention as it fails to explain how the system in Fig. 21 would continue to
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`“provide[] much greater performance for real-time applications” (Ex. 1032,
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`Abstract) if the multimedia mode of the PCI bus is limited to only communicating
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`data between the multimedia devices. See Ex. 1044 ¶ 9. In this alleged
`
`configuration, both the PCI bus and the optional multimedia bus would be
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`dedicated to transfers between multimedia devices, which would result in the CPU
`
`and the memory not being able to interface with the multimedia devices. See id.
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`Any operations requiring interface between the multimedia devices would
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`therefore be paused until the PCI bus return to the normal mode. See id. This
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`alleged configuration also negates the entire point of the multimedia bus being
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`optionally included since the multimedia devices would be “required to obtain PCI
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`Petitioner’s Reply
`IPR2016-00923 (Patent No. 5,812,789)
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`bus mastership” and would consume all of the PCI bus cycles while in the
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`multimedia mode. Ex. 1032 at 8:25-28; see Ex. 1044 ¶ 9.
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`Accordingly, Patent Owner’s argument that the multimedia mode of the PCI
`
`bus 120 in Fig. 21 can only communicate data between the multimedia devices
`
`because the multimedia bus 130 of Fig. 1 can only communicate data between the
`
`multimedia devices is incorrect. See Ex. 1044 ¶ 10. Patent Owner’s argument fails
`
`to account for the optional inclusion of the multimedia bus 130 in Fig. 21 to
`
`perform the same alleged function and it fails to explain why the multimedia mode
`
`of the PCI bus 120 (which is connected to the PCI chipset) would operate the same
`
`as the multimedia bus of Fig. 1 (which is not connected to the PCI chipset) rather
`
`than operate the same as the multimedia bus of Fig. 6 (which is connected to the
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`PCI chipset). See id.
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`In sum, Lambrecht discloses that “multimedia devices 142-146
`
`communicate with each other via the PCI bus 120 and also communicate with the
`
`CPU and main memory 110 via the PCI bus 120” and that “[t]he multimedia
`
`devices 142-146 also communicate data between each other using the real-time bus
`
`or multimedia bus 130.” Ex. 1032 (Lambrecht) at 8:20-25. Thus contrary to Patent
`
`Owner’s argument, the bus of Lambrecht enables the decoder device (i.e., a
`
`multimedia device) to access the main memory and operate in real-time.
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`2.
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`Petitioner’s Reply
`IPR2016-00923 (Patent No. 5,812,789)
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`No additional logic is needed in the PCI bridge chipset in
`Fig. 21 for the multimedia devices communicate data to the
`main memory in multimedia mode.
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`
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`Patent Owner further argues that the multimedia devices are not able to
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`access the main memory when PCI bus 120 is in “multimedia mode” because only
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`the multimedia devices include a special multimedia mode interface logic 966
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`(shown in Fig. 22). Response at 10-13. Patent Owner errs in its position that the
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`addition of special multimedia mode interface logic 966 circuitry is required in
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`order for the main memory to use the multimedia mode.
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`Patent Owner argues that “one of ordinary skill in the art would recognize
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`that only the multimedia devices (142D, 144D, 146D) are equipped to utilize the
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`‘multimedia mode’ of the PCI Expansion Bus (120)” since only these devices “are
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`equipped with the interface logic (966) of the bus interface circuitry (962).” Id. at
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`13. While it certainly is the case that the multimedia devices in Fig. 21 include
`
`interface logic 966 in order to interface with the multimedia mode (see Ex. 1032 at
`
`27:38-40), Patent Owner overlooks the other teachings of Lambrecht.
`
`Lambrecht teaches that the “a host/PCI/cache bridge or chipset 106” already
`
`has the capability of communicating with the PCI bus when in multimedia mode.
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`As shown in Fig. 21, the chipset logic 106 is coupled to a CPU 102 and a main
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`memory 110. Id. at 26:65-67, 27:4-5. “The chipset logic 106 preferably includes a
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`memory controller for interfacing to the main memory 110.” Id. at 27:8-9. The
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`Petitioner’s Reply
`IPR2016-00923 (Patent No. 5,812,789)
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`chipset logic 106 also includes a “mode logic 960 [that] is operable to place the
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`PCI bus 120 in either a normal PCI mode or in a real-time/multimedia mode
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`optimized for multimedia transfers of periodic data.” Id. at 27:19-22. Since chipset
`
`106 interfaces the CPU and the main memory with the PCI bus, and has mode
`
`logic for placing the PCI bus into multimedia mode (and for returning the PCI bus
`
`to normal PCI mode), it is clear that Lambrecht teaches that the chipset 106 is
`
`capable of communicating with the PCI bus when the PCI bus is in multimedia
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`mode. Ex. 1030 at p.43-51; see Ex. 1044 ¶ 12.
`
`This is further evidenced from Lambrecht’s disclosure of Fig. 6. As
`
`discussed above, Fig. 6 includes chipset logic 106A that “is connected to both the
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`local expansion bus 120 as well as the real-time [multimedia] bus 130A.” Ex. 1032
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`at 12:23-25; see Ex. 1044 ¶ 13. The chipset 106A “can communicate directly to the
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`PCI bus 120, and can also communicate directly with the real-time or multimedia
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`bus 130.” Ex. 1032 at 12:37-40. This allows the multimedia devices (that include
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`both PCI bus and multimedia bus interface logic, see Fig. 2) to communicate with
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`the CPU and the memory via either the PCI bus or the multimedia bus. See id. at
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`12:40-45; see Ex. 1044 ¶ 13.
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`Thus, based on the entire disclosure of Lambrecht’s Fig. 21 and the
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`examples from Lambrecht’s other embodiments, Lambrecht teaches that the
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`multimedia mode of the PCI bus 120 in Fig. 21 communicates data between the
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`Petitioner’s Reply
`IPR2016-00923 (Patent No. 5,812,789)
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`multimedia devices, the CPU, and the memory in real-time while in the multimedia
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`mode. Ex. 1030 at p.43-51.
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`B.
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`Lambrecht anticipates “a decoder that requires access to the
`memory sufficient to maintain real time operation.”
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`Patent Owner argues that Lambrecht does not anticipate “a decoder” because
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`“Lambrecht does not disclose a bus that would allow the alleged decoder (144D) to
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`access the alleged main memory (110) in real time.” Response at 14. Patent Owner
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`reasons that Lambrecht’s “multimedia devices may have their own dedicated
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`multimedia memory (160)” and in one embodiment (Figs. 15 and 16) use this
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`dedicated memory “in real time through the multimedia/real-time bus.” Id. at 14-
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`15.
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`First, Patent Owner’s argument fails because it relies on a feature of a
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`different embodiment of Lambrecht and assumes that this feature applies to Fig. 21
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`of Lambrecht. As stated in the Petition and discussed above, Lambrecht’s
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`embodiment in Fig. 21 discloses a number of multimedia devices 142D-146D that
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`are each coupled to the PCI bus 120. Ex. 1032 at 27:32-33. These multimedia
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`devices “may comprise video accelerator or graphics accelerator cards, video
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`playback cards, MPEG decoder cards, sound cards, network interface cards, SCSI
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`adapters for interfacing to various input/output devices, such as CD-ROMS and
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`tape drives, or other devices as desired.” Id. at 27:51-56 (emphasis added). Thus,
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`14
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`Petitioner’s Reply
`IPR2016-00923 (Patent No. 5,812,789)
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`since Lambrecht specifically teaches an MPEG decoder as one of the multimedia
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`devices coupled to the PCI bus 120 in Fig. 21 and, as discussed above, also teaches
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`that the multimedia devices can access the CPU and the main memory when the
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`PCI bus is in the multimedia mode, Lambrecht does in fact anticipate “a decoder
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`that requires access to the memory.” Indeed, Patent Owner’s expert admits that
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`Lambrecht discloses requiring such cards to have their own memory is undesirable
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`at least because it adds additional cost to the system. Ex. 1043 at 54:15-20; see
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`also Ex. 1032 at 2:3-11. To argue that the multimedia devices must have their own
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`dedicated memory runs directly counter to the purpose of the Lambrecht invention.
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`Second, Patent Owner’s argument also fails because it relies on an incorrect
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`understanding of the state of the art. In particular, Patent Owner’s expert claims
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`that “traditional MPEG decoders require a 2 Mbyte dedicated memory that is
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`utilized during the decoding process.” Ex. 2003 ¶ 31. Patent Owner’s expert cites
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`no evidence or support for such statement. See Ex. 1044 ¶ 14. Based on this
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`unsupported statement, Patent Owner’s expert thus assumes that the video
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`decoders discussed in Lambrecht also require dedicated multimedia memory and
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`that such decoders could not use the main memory in Fig. 21. See Ex. 2003 ¶ 48;
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`Ex. 1043 at 88:23-89:1 (“And if [the multimedia device] were assumed to be a
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`video decoder, one skilled in the art in 1997, when this was issued, would presume
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`that there would be multimedia memory”); see also Response at 22-23.
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`15
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`Petitioner’s Reply
`IPR2016-00923 (Patent No. 5,812,789)
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`Patent Owner’s expert, however, is incorrect that video decoders known in
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`the art prior to the filing of the ’789 patent in 1996 or Lambrecht in 1995 required
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`dedicated multimedia memory. See Ex. 1044 ¶ 15. For example, U.S. Patent No.
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`5,797,028 to Gulick et al. (“Gulick”) (Ex. 1023) (in which Lambrecht is a co-
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`inventor) that was filed on September 11, 1995 (almost a year prior to the ’789
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`patent) and shared the same original assignee as Lambrecht, teaches a digital
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`system chip 112 that “is programmable to perform various functions, such as
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`MPEG decoding.” Ex. 1023 at 6:21-22. Gulick describes, in certain instances, that
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`the decoder chip 112 can include “multimedia memory (not shown) for storing
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`multimedia data, such as video data and audio data.” Id. at 6:37-39. Gulick,
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`however, also discloses that, in other instances, the decoder chip 112 “does not
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`include multimedia memory, but rather video data and audio so data are stored in
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`the system memory 110 according to a unified memory architecture.” Id. at 6:48-
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`51. Other systems that also predate the ’789 patent disclosed a video decoder that
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`used shared memory. See Ex. 1007 (disclosing a system that uses either system
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`memory or dedicated memory for at least some video decoding operations); Ex.
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`1045 (disclosing a system with shared memory that is used by multiple peripheral
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`devices including video decoders); See Ex. 1044 ¶ 16.
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`Thus, it is clear that a POSITA, before the filing of the ’789 patent, had full
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`knowledge that video decoders could use main system memory according to a
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`16
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`Petitioner’s Reply
`IPR2016-00923 (Patent No. 5,812,789)
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`unified memory architecture for video decoding operations. See id. ¶ 17. Patent
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`Owner’s expert’s naked assertion that video decoders at the time of the ’789 patent
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`required dedicated multimedia memory is incorrect. See id. Instead, it was known
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`in the art that video decoders could utilize either dedicated multimedia memory, as
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`shown in Lambrecht’s Figs. 15 and 16, or the main memory, as shown in
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`Lambrecht’s Figs. 6, 19, and 21, and the evidence of record shows that it was
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`known to POSITAs that decoders could use the main system memory. See id.
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`Consequently, Patent Owner’s argument that Lambrecht’s decoder required
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`multimedia memory is entirely predicated on an incorrect understanding of the
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`state of the art. Thus, contrary to Patent Owner’s argument, Lambrecht’s Fig. 21
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`does in fact anticipate “a decoder that requires access to the memory.”
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`C. Lambrecht anticipates “a shared bus . . . having sufficient
`bandwidth to enable the decoder to access the memory and
`operate in real time.”
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`Patent Owner argues that Lambrecht fails to anticipate “a shared bus” that
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`“enable[s] the decoder to access the memory and operate in real time” for two
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`reasons—(1) the multimedia mode of Fig. 21 allegedly only allowing data transfers
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`between multimedia devices and (2) Lambrecht’s failure to specifically state that
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`the PCI bus 120, the PCI bridge chipset 106, and the memory bus 108 are capable
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`of facilitating real-time data transfers. See Response at 16-21. Both of these
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`arguments are incorrect because they fail to consider the entire description with
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`17
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`Petitioner’s Reply
`IPR2016-00923 (Patent No. 5,812,789)
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`reference to Fig. 21 as well as the technical functionality of PCI bus referenced in
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`Fig. 21.
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`First, Patent Owner reiterates its argument previously used in its Response
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`(see p.6-13) that the multimedia mode of the PCI bus in Fig. 21 is only used for
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`data transfers between the multimedia devices. Response at 18-21. This time,
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`though, Patent Owner attempt to rely not only on disclosure related to Lambrecht’s
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`Fig. 1, but also relies on Figs. 7 and 20. This argument, however, fails for the same
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`reason as discussed above in section II.A.1. Fig. 21 teaches that the multimedia
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`devices can access the main memory via the PCI bus (the only bus in Fig. 21) in
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`either the normal mode or the multimedia mode. See section II.A.1, above.
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`Second, Patent Owner’s assertion—that Lambrecht’s system in Fig. 21
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`cannot facilitate real time data transfers because the PCI bus 120, the PCI bridge
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`chipset 106, and the memory bus 108 are not specifically described as being
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`capable of such—also fails in the face of the ’789 patent’s own disclosure.
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`According to the ’789 patent, the bus must have “a bandwidth greater than the
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`bandwidth required for the decoder/encoder 45 to operate in real time.” Ex. 1001 at
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`6:29-32. In the ’789 patent, the decoder/encoder 45 operates according to the
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`MPEG-1 or MPEG-2 standard. See id. at 7:45-54. In two examples provided by the
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`’789 patent, the bus “is capable of having a bandwidth of approximately 400
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`Mbytes/s. This bandw