United States Patent 15
`Rympalski et al.
`
`[11] Patent Number:
`
`[45] Date of Patent:
`
`4,639,720
`Jan, 27, 1987
`
`54] ELECTRONIC SKETCH PAD
`[75]
`Inventors: William P, Rympalski, Melbourne:
`James 8, Herstein, Satellite Beach;
`Roger L, Ritenour, Palm Bay, all of
`Fla.
`
`[73] Assignee:
`Harris Corporation, Melbourne, Fla.
`[21} Appl. No.: 224,067
`[22] Filed:
`Jan. 12, 1981
`[ST] WAG CMS oeccessesssssssecsssssusevasecesteeeeees G09G 3/00
`[S2] US. CM, occccccecesnsssssarscseeeseueveen 340/712; 340/707:
`340/365 C
`[58] Field of Search ........cccc0: 340/707, 712, 784, 706,
`340/365 C, 708, 365 S; 178/18-20
`References Cited
`U.S, PATENT DOCUMENTS
`
`[56]
`
`.
`
`csscesseccceseeceeeee 340/706
`4/1964 Romero...
`3,128,458
`
`we 340/707
`1/1976 Graven ....
`3,932,862
`
`oe 540/707
`4,177,354 12/1979 Matthews.
`
`4,224,615
`9/1980 Penz ......
`ve 340/712
`
`4,232,311 11/1980 Agneta ..
`sees 340/707
`
`3/1981 Besson ou.
`= 340/565 C
`4,257,117
`- 340/365 €
`9/198] EHichelbergeretal.
`4,290,052
`
`. . 340/712
`4,200,061
`9/1981 Serrano .c.eecccn
`
`4,373,784
`
`2/1983 Nonomuraet al. oes 340/784
`
`Primary Examiner—Marshalt M, Curtis
`Attorney, Agent, or Firm—Antonelli, Terry & Wands
`[57]
`ABSTRACT
`A graphics input/output device contains a graphics
`input pad having an array of transparent capacitive
`pixels the capacitance characteristics of which are
`changed in response to the passing of a conductive-
`tipped stylus over the surface of the pad. This change in
`capacitance is sensed by sense buffers disposed along
`the columns of the matrix, as the rows are scannedat a
`prescribed scanning rate.
`_
`The sensed data is read out of the sense buffer and
`loaded into a RAM. Anarray ofdisplay pixels formed
`of an LCD matrix is addressed by a scan sequence con-
`trol unit, and the energization of the display pixels is
`multiplexed with the read-out scanning of the sensed
`data, so as to present to the user a real time generated
`image of the graphics created by the stylus. As a result,
`it appearsto the user that the stylusis actually “writing”
`on the display pad.
`
`30 Claims, 13 Drawing Figures
`
`(133
`
`
`
`
`
`CAPACITOR PIXEL
`ARRAT
`
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`US. Patent
`
`Jan. 21, 1987,
`
`Sheet 1 of7
`
`4,639,720
`
`TO
`
`FIG. A.
`
`MODEM —-
`
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`U.S. Patent
`
`Jan. 27, 1987
`
`Sheet 2 of 7
`
`4,639,720
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`U.S. Patent
`
`Jan. 27,1987
`
`Sheet 3 of7
`
`4,639,720
`
`LCD DISPLAY
`MATRIX
`
`
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`U.S. Patent
`
`Sheet 4 of 7.
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`4,639,720
`
`Jan. 27, 1987
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`EXHIBIT2012
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`U.S. Patent
`
`Sheet 5 of 7
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`4,639,720
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`

`U.S. Patent
`
`Jan.27,1987
`
`Sheet of7
`
`4,639,720
`
`FIG. 9A,
`
`NEW
`OLD
`"NEW
`_
`
`MEMORY DATA|PIXEL DATA; W/E=|MEMORY DATA.
`
`LINE 160 LINE 48 LINE 46MODE LINE 44
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`
`CLK SWITCHED LATCH UNIT
`
`258
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`260
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`262
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`U.S. Patent
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`Jan.27,1987
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`Sheet 70f7
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`4,639,720
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`FIG. 10,
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`$2 CLK
`
`INTL.SYNC
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`1
`
`ELECTRONIC SKETCH PAD
`
`4,639,720
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`FIELD OF THE INVENTION
`The present, invention relates to a graphic transducer
`device that is capable of accepting and storing user
`written graphics as may be applied to the device bya
`hand-held stylus, The invention also relates to a device
`associated with the transducer for providing a display
`of the graphics being concurrently written on the sur-
`face of the transducer device.
`
`2
`point of the stylus. Because ofits reliance on the mem-
`ory property of the plasma display, selective control of
`the display graphics and addressing the display from
`external memory are not possible, so as to substantially
`limit tts adaptability to other data I/O interfaces suchas
`external communications and memory.
`in addition to the above-described proposals, there
`are various other coordinate display or hand-held or
`touch-responsive transducer arrangements, some for
`input data resolving alone, others for graphics input and
`display. However, these devices also suffer from a lack
`of versatility (they are capable of locating only one
`coordinate point at a time) and consume considerable
`power and involve complex hardware, thereby reduc-
`ing their cost effectiveness and practical utility for the
`graphics message writer. For an overview of such pro-
`posais, attention may be directed to the U.S. Pat. Nos.
`3,757,322 to Barkan; 4,030,091 to Ngo; 3,342,935 to
`Leifer et al.; 3,530,241 to Ellis; 3,699,439 to Turner;
`4,055,726 to Turner et al.; 3,958,234 to Hoo; and
`4,121,204 Welch et al.
`
`SUMMARYOF THE INVENTION
`In accordance with the present invention, there is
`provided a new and improved graphics input/output
`device which overcomesthe shortcomings of prior art
`proposals, through a scheme that offers simplicity, ver-
`satiiity and low pawer consumption,
`together with
`considerable ease of operation. To this end, the unit
`employs a graphics input pad or plate containing an
`array or matrix of transparent capacitive coupling-
`responsive conductors, the capacitance characteristics
`of which are changed in response to the passing of a.
`conductive-tipped stylus over the surface ofthe graph-
`ics input pad. As the stylus tip passes over the pad sur-
`face, it is capacitively coupled to one or more pairs
`(depending upon stylus tip contact area as may be im-
`parted by user hand pressure) of row and column.
`arranged conductor electrode regions, thereby chang-
`ing their normal capacitance. This change in ‘capaci-
`tance is sensed by sense buffers disposed along the col-
`umns, as the rows are scanned at a prescribed scanning
`rate.
`
`‘Fhe sensed data is read out of the sense buffer and
`icaded into a random access memory (RAM) under the
`control of a scan sequence contre! circail. An array of
`display pixels formed of a liquid crystal display (LCD)
`matrix, corresponding in number and position to the
`X-Y intersections ofthe clectrodesof the graphics input
`pad, is addressed by the scan sequence control unit and
`the energization ofthe display pixels is multiplexed with
`the read-out scanning of the sensed data, so as to present
`lo the user a real time generated image of the graphics
`created by the stylus, so that it appears to the user that
`the stylus is actually “writing” on the display pad. In
`addition to its writing capability, the electronic sketch
`pad of the present invention may operate in an erase
`mode, whereby the user may selectively 25 erasc previ-
`ously written graphics from the display, employing the
`same stylus used for writing. In this mode, combina-
`ional logic within the scan sequence control unit logi-
`cally combines the data stored in the display memory
`with that obtained from the sense buffer, so as to change
`the states of the bits corresponding to graphics stored in
`memory over which the now-erasing stylus passes.
`During the display cycle, this new data is delivered to
`
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`25
`
`BACKGROUND OF THE INVENTION
`Recent technological developments in information
`exchange systems have witnessed proposals to replace
`keyboards or scanners as the fundamental message
`entry device. Generally these proposals entail some
`form of coordinate position input
`transducer upon
`which the user enters graphics data by means of a sty-
`lus, such as a light pen, shorting conductive rod stylus,
`etc. An array of signal pick-up elements located within
`or coupled integrally to the transducer produce output
`signals representative of specified or selected coordi-
`nate locations over which the input coupling element
`(e.g. stylus) travels as the user writes the graphics on the
`transducer. These signals are then processed (e.g. en-
`coded, stored, etc.) and may be used to address a matrix-
`type display device throngh which the graphics gener-
`ated by the user may be displayed for viewing. In addi-
`tion to cathode-ray tube displays which typically re-
`spond to user-generated graphic input signals produced
`by a light. beam stylus,
`there have been proposed
`schemes whereby the display device is of a relatively
`compactsize and lies directly beneath the input trans-
`ducer, so that the stylus appears to create a graphics
`display image at its coordinate paints of contact with
`the device. For an exemplary ilustration of these types
`of devices, attention may be directed to U.S, Pat. Nos.
`4,177,354 to Matthews and 3,944,740 to Murase et al.
`The former patent describes a device whereby a light
`pen is used to cause local conduction of the input trans-
`ducer through a photosensitive layer separating a con--
`ductive and a resistive plane. The coordinates of the
`ight pen stylus are derived from the voltage level de-
`tected at the top conductive plane, and then processed
`for display via a display assembly such as a CRT unit,
`upon which the graphics entry transducer may be
`placed. This type of device has the disadvantage of
`being light sensitive, so that high ambient light or a.
`light-emitting display could degrade its performance,
`the light pen scans only a singfe matrix transducer point
`at @ time and the processing of the data for storage and
`display, as well as the display itself (CRY), requires a
`significant amountofhardware and high powerrequire-
`ments.
`The scheme proposed in U.S. Pat. No. 3,944,740 is an
`attempt at a reduced-size or compact configuration of a
`combined graphics input/output device and, for this
`purpose, it employs a transparent input pad mounted
`over the tap of a plasma panel display. The input pad is
`a matrix of conductive rows and columnsthat are ar-
`ranged so that a stylus having a conductive tip can short
`circuit a row electrode and a column electrodeat its
`point of contact, with current conducted through the
`row and column electrodes representing the stylus loca-
`tion. The plasma display has an inherent Memory capa-
`bility which is employed to provide 2 one-for-one stor-
`age and display function for each short circuit contact
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`3
`the LCD screen whereby the erasure action of the
`writer is presented as removed graphics.
`A further feature of the present invention provides
`written graphics to be stored for retrieval at a later time,
`with the writing/display surface being cleared for ac-
`cepting new graphics. In this embodimentof the inven-
`tion, multiple display memory units are employed. This
`feature also enables stored graphics to be selectively
`coupled for external communication via a suitable
`modem interface unit. Another feature of the present
`invention permits the electronic sketch pad, when cou-
`pled to a suitable computer with image processing capa-
`bility, to serve as a new form ofinteractive graphics
`computer terminal.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG.1 is a pictorial view of the physical configura-
`tion of an electronic sketch pad according to the present
`invention;
`FIG.2 is a general block diagram ofthe data storage
`and signal processing circuitry of the control circuitry
`portion of the electronic sketch pad;
`FIG, 3 is a top view of a portion of the X-Y grid
`structure of a capacitor pixel array mput pad;
`FIG.4 is a sectional view of the structure of a capaci-
`tor pixel array taken along line I—I of FIG. 3;
`FIG.5 is a sectional view of the structure of a capaci-
`tor pixel array taken along line IT—II of FIG. 3;
`»"BIG,6 illustrates the configuration of a writing stylus
`for use with the electronic sketch pad;
`FIG. 7 is an iliustration of the general configuration
`"of an LCD pad and its coupling electrode arrangement;
`“FIGS, 8A and 8B are a schematic logic diagram of a
`scanning control sequencer;
`FIG. 9 is a schematic logic diagram of a memory
`update conversion logic circuit;
`~ RIG. 9A is a truth table for explaining the operation
`'”
`* of the logic of FIG. 9;
`'
`FIG. 10 is a schematic block diagram of the capacitor
`“pixel array sean electronics; and
`* - BIG. 1£ is a schematic block diagram of the LCD
`scan electronics.
`DETAILED DESCRIPTION
`A pictorial view of the physical configuration of an
`electronic sketch pad according io the present inven-
`tion is shown in FIG.1. The sketch pad 1 is a multilay-
`ered device having a top or upper transparent capaci-
`tance input matrix pad 2, beneath which there is dis-
`posed an LCD matrix output or display pad 3. Beneath
`display pad 3 is an input/output and power pack unit 4
`containing scan control electronics and drive circuitry
`for the pads 2 and 3, which may be implemented in
`accordance with large scale integration (LSI) tech-
`niques.
`The upper transparent capacitance input matrix pad
`2, a detailed description of which will be presented
`below m conjunction with the description of FIG, 3,
`gay be formed of an Indium Tin Oxide thin film array
`of transparent conductive regions deposited on a glass
`plate and connected in a row and column configuration.
`The array of regions corresponds to a like array of
`pixels of display pad 3 atop which pad 2 is superim-
`posed. Both pads 2 and 3 may be connected to unit 4
`through strips of conductive elastomer.
`The generation of input graphic data may be effected
`by means of a hand-held writing stylus 5. Stylus 5, to be
`described in greater detail below in conjunction with
`
`4
`the description of FIG. 6, may be formed of a plastic
`tod, having the size and shape of an ordinary pencil.
`The writing tip of stylus 5 may be formed of silicon
`rubber that has been impregnated with metal (e.g. sil-
`ver) particles. As the tip of stylus 5 is passed over the
`writing surface 7 of pad 2, il capacitively couples X-Y
`pairs of transparent conductive regions to each other,
`thereby altering their normal capacitance. This change
`in capacitance is sensed by a sense buffer, and is coupled
`to the electronics processing pad 4, in response to the
`operation of the matrix scan electronics.
`Data stored in the buffers is continually loaded into a
`static random access display memory contained in the
`electronics pad 4, During this time, the pixels of display
`pad 3 are energized in real time, corresponding to the
`stored sensed changed capacitance data, as the stylus §
`is moved over the surface 7 of pad 2. As there is a physi-
`cal one-for-one correspondence between row-column
`capacitance coupling regions in input pad 2, and display
`pixels in display pad 3, and also an electrical correspon-
`dence to storage locations in the static RAM, the LCD
`pixels are energized by the display memory readout at
`the same input capacitance coupling locations over
`which stylus 5 is passed. As a result, there is effectively
`presented a real time graphical presentation of the track
`6 of stylus 5 directly beneath writing surface 7, so that
`stylus 5 appears to be writing the graphics at its point of
`contact with input pad 2.
`Also provided on upper pad 2 is a set of control
`switches 8 coupled to the scan control and display
`memory circuitry of pad 4. Through the operation of
`these switches, the user of the pad mayselectively con-
`trol the mode of operation of the pad. More specifically,
`an INITIALIZE switch through which the pad is
`cleared for the start of operation. The function of such
`aswitch will be described in detail below in conjunction
`with the detailed description of FIGS. $A and 8B. The
`switch set may also include a WRITE/ERASE (ER)
`switch that is used to selectively erase graphics previ-
`
`ously written on the pad. The selective erasure is ac-
`complished by depressing the WRITE/ERASE switch
`and passing stylus 5 over previousiy written graphics.
`In addition, the set of switches may include one or more
`switches for externaliy controlling the selective cou-
`pling of data to and from additional memory. Through
`the operation of these switches, graphics written on
`display pad 3 may be entered inta one section of mem-
`ory, so that new graphics may be wotten on the pad
`using additional memory space. Similarly, previousky
`stored graphics may be displayed withoutthe use ofthe
`stylus. A detailed description of the effect of such exter-
`na! control of these switches will be presented below in
`conjunction with the description of the details of the
`data storage and signal processing circuitry.
`A general block diagram of the data storage and
`signal processing circuitry of the electronic sketch pad,
`shownpictorially in FIG. 1,
`is presented in FIG. 2.
`Hach of the transparcnt capacitance input pad 2 and
`LCD output pad 3 is coupled to input/output scanning
`electronics unit 13, the details of which will be de-
`scribed below in conjunction. with the desertption of.
`FIGS. 10 and 11. 1/0 scanning eiectronics 13 contains
`a pair of separate scanning subunits, one for the capaci-
`tance input pad and one for the antput display pad. The
`subunit for the input pad scans the matrix of conductive
`regions of capacitance input pad 2 to read out changes
`in capacitance at row/column intersections that have
`occurred as a result of the passing of the writing stylus
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`5 over the surface of pad 2. Similarly, for the LCD
`output pad 3, the output pad subunit of 1/O scanning
`electronics unit 13 carries out refresh scanning of the
`display pixels im accordance with data that has becn
`stored in a display memory 11, Dispiay memory 11 has
`one or More memory sections, each containing a plural-
`ity of memory locations corresponding, bit-by-bit, to
`the pixels of LCD output pad 3 and the capacitance
`row/column intersections of the conductive regions of
`input pad 2. Each memory section may be considered ta
`Tepresent one page of the sketch pad, upon which
`graphics may be writien for future reference. Forthis
`purpose, display memory 11 includes a switch unit
`under the control of an exiernal page switch, which
`selects the memory section to be used for the operation
`of the system. For purposes of simplifying the present
`description, let it be assumed that display memory 11
`contains a pair of memory sections, each of which has a
`memory capacity corresponding to the display pixel
`array. Page control switch may be used to select one of
`these two memory sections for one position of the
`switch, and the other memory section for the other
`position of the switch. In this manner, graphics written
`into one memory section may be stored for later recall
`and display as will be understood from the more de-
`tailed description to follow.
`Data originally inpui to the system by writing on
`. capacitance input pad 2 is written into memory 11 and
`read out therefrom for display by LCD output pad 3
`under the control of 2 scan control sequencer 12,
`through I/O scanning electronics unit 13. Scan control
`sequencer 22, the details of which will be described
`bclow in conjunction with the description of FIGS. 8A
`and 8B,
`is coupled to the set of switches described
`briefly above and contains timing signal generator cir-
`cuitry and combinational control logic for controfling
`the overall operation of the sketch pad signal processing
`circuitry. The display memory 11 and scan control
`sequencer 12 may also be coupled to an external bus
`interface 14 for permitting data communications to an
`extended memory or modem. Having described, gener-
`ally, the various components of which the electronic
`sketch pad of the present invention is configured, the
`details of the configuration and operation of the respec-
`tive individual units of the system will be described
`next.
`
`6
`214, 21%, 21¢, and 21d, while square section 22 has edges
`22a, 226, 22c, and 22d. Theintersection of edges 21¢ and
`216 ofsquare section 21 is contiguous with tab 23 which
`extends to and is contiguous with the corner bounded
`by edges 22c and 22d of square section 22, Similarly,
`each raw or Y electrode may also be formed as a series
`of square scctions, 31 and 32 of which are showninter-
`connecied by a tab 33 at opposing horizontal or row
`comers of adjacent square row sections. Thus, at the
`intersection of edges 314 and 31c of square section 31,
`tab 33 contiguously extends to the intersection of edges
`32d and 32a of square section 32. As viewed in plan, the
`square sections are spaced apart from each other,so that
`edge 216 of column square section 21 is spaced apart
`from edge 32d of square section 31. Similarly, edge 212
`of section21is spaced apart from edge 31¢ of section 31,
`edge 22d of section 22 is spaced apart from edge 314 of
`sction 31, and edge 22¢ of section 22 is spaced apart
`from edge 32a of section 31. It is again to be noted that
`the illustration of the plan view of the conductive
`square scctions in FIG. 3 is only a portion of the number
`of square sections of the overall matrix of the pad. To
`closely match normal linewidths of everyday writing
`insiruments, the linear density of the pad may be on the
`order of 32 seclions per inch. Each individual square
`section may be 0.020 inches on an edge with 0.032
`inches ¢enter-to-center spacing, the width of the tab
`portion being on the order of 0.001 inches. For those
`square sections that make up the rows of the matris, the
`tabs extend from the corners of adjacent row square
`sections in the Y or row direction, as tab 33 extends
`between row square sections 31 and 32. For those
`square sections that make up the columnsofthe matrix,
`the tabs extend in the X or column direction, as tab 23
`extends between column square sections 24 and 22.
`FIG, 4 showsa side sectional view of a portion ofthe
`capacitance input pad taken along line I—I of FIG.3.
`The pad is configured of a multiple layer structure of
`dielectric and conductor and may be formed by conven-
`tional lithographic manufacturing techniques. Square
`section 31 which is one of the transparent conductive
`row electodes,
`is formed of Indium Tin Oxide sput-
`tered, or otherwise deposited, and selectively etched on
`a glass substrate 37 to a thickness t of about 3000 A as
`the row electrodes are deposited. A dielectric layer 35
`of Silicon Dioxide or other suitable material is sput-
`tered, or otherwise deposited, over the row electrode
`CAPACITANCE INPUT PAD
`pattern to a thickness t of about 3000Aatop each raw
`The capacitance input pad is a capacitor switch array -
`section. Next, the column electrode pattern is formed
`30
`formed essentially of an X-Y grid of transparent Indium
`atop dielectric layer 35 to a thickness about 3000 A,
`Tin Oxide conductors deposited on a glass substrate.
`square section 21 of which is shown in FIG. 4. The
`FIG, 3 shows a top view of a portion of the X-¥ grid
`horizontal separation between adjacent edges of row
`. structure, while FIGS. 4 and § show side views of a
`and column electrodes, e.g. edge 21c of section 21 and
`portion of the same, depicting its layered configuration.
`edge 3lc of section 31,is about 0.001 inch to provide an
`In order to simplify the drawing, only that portion of
`acceptably low parasitic capacitance. Finally, a top
`the grid structure shown in solid line form has been
`layer of Silicon Dioxide 36 or other suitable material is
`numerically identified and will be described presently.
`sputtered or otherwise deposited on the upper column
`Surrounding conductors have been shown in broken
`electrode pattern and the exposed surface of dielectric
`lines and it wil! be understood that the number of con-
`layer 35 to complete the multilayer capacitance struc-
`ture.
`ductive regions of the matrix will vary depending upon
`the size and shape of the pad. Referring to FIG. 3, each
`FIG.5 showsa side sectional view ofa portion ofthe
`column or X electrode may be formed as a series of
`capacitance input pad taken along line II—II of FIG.3.
`square sections, 21 and 22 of which are shownin solid
`Square sections 31 and 32 connected bytab 33 are acen
`line form, interconnected by a tab 23 at Opposing cor-
`as @ continuous metallic layer,
`the separate sections
`ners of adjacent square sections. Each square sectionis
`being delineated by brokenlines through the layer. Tab
`bounded by tab projections at its opposite vertical or
`23 of a column electrode layerlies directiy over tab 33
`column corners with the edges bemg denoted by the
`of the row electrode layer thercbeneath. When the
`letters a, b, ¢, and d. Thus, square section 21 has edges
`conductive tip of stylus § passes over the surface 7 of
`
`35
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`4
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`35
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`the silicon dixcide layer 36 of the capacitance input pad
`there is a change in the capacitive coupling between the
`row and column electrodesat that point, which is indi-
`cated by capacitances 382 and 384 across dieiectric
`layer 35, This change in capacitive coupling is detected
`by the scanning electronics, to be described fully below
`in conjunction with the description of FLG. 16, by send-
`ing a digital pulse into each row, each row electrode
`being pulsed in sequence. Sense buffers are coupled to
`the columnelectrodes to detect the degree of capacitive 10
`coupling between the row and column electrodes. The -
`frequency of scanning is considerably higher than the
`movement of the stylus 5 over the surface 7 of the ca-
`pacitance input pad, so that at each X-Y crossing region
`over which the stylus passes, there will be a change in
`capacitive coupling detected by the sense buffers.
`STYLUS
`
`13
`
`20
`
`Thestyius employed to create the change in capaci-
`tive conpling at the X-¥ crossovers of the input padis
`shown in FIG, 6. The stylus itself may be formed of a
`cylindrical acrylic rod 5¢, the size of an ordinary pencil,
`at opposite ends of which there are inserted electrically
`conductive tips 5A and 5B for capacitive coupling the
`X-Y pixels of the input pad. Bach oftips 5A and 5B may
`be made of resilient, metal-filled plastic having a low
`coefficient of friction. One suitable material is an RTV
`' petting compound impregnated with silver. The shapes
`’ of tips 5A and 5B may have different tapers to provide
`different basic line widths. In this regard, with a certain
`degree of “softness” in the stylus tips, the width of a
`written line may be caused to vary by varying the de-
`gree of writing pressure imparted to the stylus, so that
`the contact area of the tip covers a plurality of X-Y
`capacitive switch array pixels. Also, the flexibility of 35
`the stylus tip enables it to conform io the shape of the
`' pad surface for maximum capacitive coupling to the
`transparent square regions of the row and columnelec-
`trodes.
`
`25
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`30
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`DISPLAY PAD
`
`“The display pad is formed of a liquid crystal dot
`matrix having 2 pixel arrangement in one-for-one coin-
`cidence with the capacitor pixels of the capacitance
`input pad. Such an arrangement is shown generally in
`FIG. 7, wherein LCD pad 3 is depicted. The pad con-
`tains a matrix of pixels, one of which 17 is shown at the
`intersection of the X1 and Y1lines of inputleads 15 and
`16. Leads 15 contain a Y or row driverinputlines while
`leads 16 contain a number m of X or column driver
`lines. The leads and pixel array are of conventional
`configuration to provide a matrix of pixels the number
`and position of which co respond to and are aligned
`with the X-Y crossovers of the capacitance input pad
`described above. As the physical construction of such
`an LCD panel is conventional, a more detailed descrip-
`tion of the same will not be presented here. Instead, the
`description below will focus upon the manner in which
`the LCD panel is sequentially scanned to create the
`image graphics to follow the path of the writingstylus.
`
`SCAN CONTROL SEQUENCER
`As described previously in conjunction with the de-
`scription of the general block diagram of the system
`shown in FIG. 2, control of the operation of the scan-
`ning, input and output fuactions of the input pad 2, and
`display pad 3, are carried out by a scan control se-
`quencer 12. This unit contrals the scan of the capaci-
`
`45
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`50
`
`35
`
`65
`
`8
`tance input pad 2, extracts data from the input buffers,
`updates the data in display memory 11, and controls the
`multiplexing of the data in LCD pad 3.
`Referring now to FIGS. 8A and 8B, a schematic
`logic diagram of the scanning control sequenceris ilus-
`trated. For coupling data to and from the section of
`display mcmory 11 as selected by the page switch, 4
`bidirectional, multi-bit data bus 41 is provided. Data bus
`41 is coupled to a buffer register 43 into which data read
`out from memory is controllably latched, as wiil be
`explained below. Bidirectional data bus 41 may be an
`eight bit data bus, although the size of the data bus may
`be appropriately tailored depending upon system com-
`ponents used and § opcrational requirements, without
`departing from the scope of the present invention. For
`purposes of the present description,it will be assumed
`that data bus 41 is an eight bit bus. When selectively
`enabled, buffer register 43 latches the data bits that are
`read out from memory and couples these daia bits to a
`data update decision circuit 45. Data update decision
`circuit 45 is comprised of combinational logic which
`receives, in addition to the data read out from memory,
`data that is produced from the capacitor switch array
`from the sketch pad scan electronics and updaies the
`state of the data bits from those memory locations cur-
`rently being addressed, the updated data bits being re-
`turned to memory. Within data update decision circuit
`45, there are a plurality of memory update conversion
`logic circuits 50, a detailed configuration for a single
`one of which is shown in FIG. 9, to be described below.
`Each of these memory update conversion logic circuits
`50 responds to a WRITE/ESE/input control signai on
`line 46 and selectively updates the value of the data bits
`for an individual data word read out of memory and
`returned to memory.
`Data that is coupled from the capacitor switch array
`is coupled over data bus 48. Data bus 48 is coupled also
`to the LCD pad for driving the LCD elements for the
`purpose ofdisplaying contents of memory as the respec-
`tive memory locations corresponding to scanned pixel
`locations are read out. For this purpose, bidirectional
`data bus 41 is coupled to a set of tristate driver circuits
`47, the outputs of which are coupled to data bus 48.
`Simitarly, the outputs of the memory update conversion
`logic circuits 50 within data update decision circuit 45
`are coupled over a data bus 44 to a set oftristate drivers
`42. The states of the variousbits of an eight bit word on
`databus 44 representative of the current value of data
`from those locations in memory being addressed are
`written back into memory through tristate driver cir-
`cuits 42.
`For addressing the display memory H,either in the
`read or write mode, a set of address lines 51, the number
`of which relates to the numberof pixels, and therefore
`the size, of the memory, are coupled to an address
`driver circuit 52, a set of inputs 53 for which is derived
`from a multiplexer 54. Multiplexer 34 receives the out-
`put of a display address generator 55 or a scan address
`generator 56, depending upon which of control Enes 67
`and 68 is enabied. Line 68, representative of. the cou-
`pling of the contents of the scan address generator 56
`through the multiplexer to the memory,
`is enabled
`when a prescribed portion of the capacitor switch array
`is being read out for updating the contents of memory
`corresponding to that location in the sketch pad. Line
`67 is enabled to cause muitiplexer 54 to couple the con-
`tents of the display address generator 55 to memory
`during a display mode during which the contents of the
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`memory are read out and delivered to the LCD via data
`also coupled to the reset input of the flip-flop 72. Flip-
`bus 48. In effect, each of the display address generator
`flop 72 is employed during the sequential scanning of
`55 and the scan address generator 56 is a binary counter,
`the capacitor switch array to cause multiplexcr 54 to
`controllably reset by a signal on line 95 during initializa-
`couple the output of scan address generator 56 to ad-
`tion of the system and each of which respectively
`dress link 51. Flip-flop 72 is set by way of line 73 which
`counts pulses supplied to its clock input via inverters 76
`is coupled to the Q output of a flip-flop delay circuit
`116.
`and 75, respectively, from input lines 77 and 74, re