throbber
UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`
`
`
`
`
`VOLKSWAGEN GROUP OF AMERICA, INC.,
`Petitioner
`
`v.
`
`ADVANCED SILICON TECHNOLOGIES LLC,
`Patent Owner
`
`
`
`Case IPR2016-TBA
`Patent 6,546,439 B1
`
`
`
`
`DECLARATION OF DR. ROBERT W. HORST
`Pattin-based IPR
`
`
`
`
`
`
`
`
`
`
`
`Mail Stop “PATENT BOARD”
`Patent Trial and Appeal Board
`U.S. Patent & Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`0001
`
`Volkswagen 1002
`
`

`
`
`
`TABLE OF CONTENTS
`
`U.S. Patent No. 6,546,439 B1
`
`I.  Background ......................................................................................................... 1 
`
`II.  Qualifications and Expertise ............................................................................... 2 
`
`III.  Legal Understanding ........................................................................................... 5 
`
`A.  My Understanding of Claim Construction ...................................................... 5 
`
`B.  A Person of Ordinary Skill in the Art .............................................................. 5 
`
`C.  My Understanding of Anticipation .................................................................. 6 
`
`D.  My Understanding of Obviousness ................................................................. 6 
`
`IV.  Background of Memory Controllers for Scheduling Memory Requests ............ 9 
`
`A.  Memory controllers are well known. ............................................................... 9 
`
`V.  Technical Analysis of the ’439 Patent .............................................................. 10 
`
`A.  Technical Summary ....................................................................................... 10 
`
`B.  Summary of Prosecution History .................................................................. 12 
`
`VI.  Understanding of Certain Claim Terms ............................................................ 15 
`
`A.  Source Indication ........................................................................................... 15 
`
`B.  Tag ................................................................................................................. 16 
`
`VII. Pattin Ground 1: Claims 1-7, 10-13, 15, 17-23, 26-29 and 31 are obvious over
`
`Pattin and Lewchuk .................................................................................................. 16 
`
`A.  Overview of Pattin ......................................................................................... 16 
`
`
`
`- i -
`
`0002
`
`

`
`U.S. Patent No. 6,546,439 B1
`
`B.  Overview of Lewchuk ................................................................................... 19 
`
`C.  Rationale for combining Pattin and Lewchuk ............................................... 20 
`
`D.  Claim 1 is obvious over Pattin and Lewchuk ................................................ 22 
`
`E.  Claim 2 is obvious over Pattin and Lewchuk ................................................ 28 
`
`F.  Claim 3 is obvious over Pattin and Lewchuk ................................................ 29 
`
`G.  Claim 4 is obvious over Pattin and Lewchuk ................................................ 31 
`
`H.  Claim 5 is obvious over Pattin and Lewchuk ................................................ 33 
`
`I.  Claim 6 is obvious over Pattin and Lewchuk ................................................ 34 
`
`J.  Claim 7 is obvious over Pattin and Lewchuk ................................................ 36 
`
`K.  Claim 10 is obvious over Pattin and Lewchuk .............................................. 37 
`
`L.  Claim 11 is obvious over Pattin and Lewchuk .............................................. 38 
`
`M.  Claim 12 is obvious over Pattin and Lewchuk .............................................. 39 
`
`N.  Claim 13 is obvious over Pattin and Lewchuk .............................................. 40 
`
`O.  Claim 15 is obvious over Pattin and Lewchuk .............................................. 40 
`
`P.  Claim 17 is obvious over Pattin and Lewchuk .............................................. 41 
`
`Q.  Claim 18 is obvious over Pattin and Lewchuk .............................................. 42 
`
`R.  Claim 19 is obvious over Pattin and Lewchuk .............................................. 43 
`
`S.  Claim 20 is obvious over Pattin and Lewchuk .............................................. 43 
`
`T.  Claim 21 is obvious over Pattin and Lewchuk .............................................. 44 
`
`- ii -
`
`
`
`
`
`0003
`
`

`
`
`
`U.S. Patent No. 6,546,439 B1
`
`U.  Claim 22 is obvious over Pattin and Lewchuk .............................................. 44 
`
`V.  Claim 23 is obvious over Pattin and Lewchuk .............................................. 45 
`
`W.  Claim 26 is obvious over Pattin and Lewchuk .............................................. 45 
`
`X.  Claim 27 is obvious over Pattin and Lewchuk .............................................. 46 
`
`Y.  Claim 28 is obvious over Pattin and Lewchuk .............................................. 46 
`
`Z.  Claim 29 is obvious over Pattin and Lewchuk .............................................. 47 
`
`AA. Claim 31 is obvious over Pattin and Lewchuk .............................................. 47 
`
`VIII.  Pattin Ground 2: Claims 14 and 30 are obvious over Pattin, Lewchuk and
`
`Bauman .................................................................................................................... 48 
`
`A.  Overview of Bauman ..................................................................................... 48 
`
`B.  Rationale for combining Pattin, Lewchuk and Bauman ................................ 49 
`
`C.  Claim 14 is obvious over Pattin, Lewchuk and Bauman .............................. 52 
`
`D.  Claim 30 is obvious over Pattin, Lewchuk and Bauman .............................. 55 
`
`IX.  Pattin Ground 3: Claims 8, 16, 24 and 32 are obvious over Pattin, Lewchuk
`
`and Wulf ................................................................................................................... 55 
`
`A.  Overview of Wulf .......................................................................................... 55 
`
`B.  Rationale for combining Pattin and Wulf ...................................................... 57 
`
`C.  Claim 8 is obvious over Pattin, Lewchuk and Wulf ...................................... 60 
`
`D.  Claim 16 is obvious over Pattin, Lewchuk and Wulf .................................... 61 
`
`
`
`- iii -
`
`0004
`
`

`
`
`
`E.  Claim 24 is obvious over Pattin, Lewchuk and Wulf .................................... 63 
`
`F.  Claim 32 is obvious over Pattin, Lewchuk and Wulf .................................... 63 
`
`U.S. Patent No. 6,546,439 B1
`
`X.  Pattin Ground 4: Claims 9 and 25 are obvious over Pattin, Lewchuk and
`
`DiNicola ................................................................................................................... 64 
`
`A.  Overview of DiNicola.................................................................................... 64 
`
`B.  Rationale for combining Pattin, Lewchuk and DiNicola .............................. 66 
`
`C.  Claim 9 is obvious over Pattin, Lewchuk and DiNicola ............................... 69 
`
`D.  Claim 25 is obvious over Pattin, Lewchuk and DiNicola ............................. 71 
`
`XI.  Conclusion ......................................................................................................... 73 
`
`
`
`- iv -
`
`   
`
`
`
`0005
`
`

`
`U.S. Patent No. 6,546,439 B1
`
`I, Dr. Robert W. Horst, declare as follows:
`
`I. Background
`
`1.
`
`I have been retained as an expert witness by Sterne, Kessler,
`
`Goldstein & Fox, P.L.L.C. to provide testimony on behalf of Volkswagen Group of
`
`America, Inc. (“Volkswagen”), for the above-captioned inter partes review
`
`proceeding. I understand that this proceeding involves U.S. Patent No. 6,546,439
`
`B1 (“’439 patent”), entitled “Method and System for Improved Data Access” by
`
`Geoffrey S. Strongin and Qadeer A. Qureshi. I understand that the ’439 patent was
`
`filed on December 9, 1998, issued on April 8, 2003, and is currently assigned to
`
`Advanced Silicon Technologies, LLC (“AST”).
`
`2.
`
`I have reviewed and am familiar with the specification of the ’439
`
`patent. I understand that the ’439 patent has been provided as Exhibit 1001. I will
`
`cite to the specification using the following format: (’439 patent, 1:1-10.) This
`
`example citation points to the ’439 patent specification at column 1, lines 1-10.
`
`3.
`
`I have reviewed and am familiar with the file history of the ’439
`
`patent. I understand that the file history has been provided as Exhibit 1008.
`
`4.
`
`I have also reviewed and am familiar with the following prior art used
`
`in the Petition for inter partes review of the ’439 patent:
`
`5.
`
`U.S. Patent No. 5,745,913 to Pattin et al. (Ex. 1003, “Pattin”);
`
`U.S. Patent No. 6,058,461 to Lewchuk et al. (Ex. 1005, “Lewchuk”);
`
`
`
`- 1 -
`
`0006
`
`

`
`U.S. Patent No. 6,546,439 B1
`
`U.S. Patent No. 5,832,304 to Bauman et al. (Ex. 1004, “Bauman”).
`
`U.S. Patent No. 6,154,826 to Wulf et al. (Ex. 1006, “Wulf”); and
`
`U.S. Patent No. 5,394,524 to DiNicola et al. (Ex. 1007, “DiNicola”).
`
`6.
`
`The ’439 patent describes a memory controller that schedules accesses
`
`to a system memory based on source attributes or other parameters associated with
`
`the requested memory accesses. (’439 patent, Abstract.) I am familiar with the
`
`technology described in the ’439 patent as of its earliest possible priority date (i.e.,
`
`December 9, 1998).
`
`7.
`
`I have been asked to provide my technical review, analysis, insights
`
`and opinions regarding the ’439 patent and the above-noted references that form
`
`the basis for the grounds of unpatentability set forth in the Petition for inter partes
`
`review that this Declaration supports.
`
`8.
`
`I am being compensated at my regular hourly rate, with
`
`reimbursement for actual expenses. My compensation is not dependent on the
`
`outcome of this inter partes review and in no way affects the substance of my
`
`statements in this declaration.
`
`II. Qualifications and Expertise
`
`9.
`
`I am an independent consultant with more than 30 years’ expertise in
`
`the design and architecture of computer systems. I have been asked to offer
`
`technical opinions relating to U.S. Patent No. 6,546,439, and prior art references
`
`
`
`- 2 -
`
`0007
`
`

`
`U.S. Patent No. 6,546,439 B1
`
`relating to the related subject matter. My current curriculum vitae is submitted as
`
`Exhibit 1010 and some highlights follow.
`
`10. Currently, I am an independent consultant at HT Consulting where my
`
`work includes consulting on technology and intellectual property. I have testified
`
`as an expert witness and consultant in patent and intellectual property litigation as
`
`well as inter partes reviews and re-examination proceedings.
`
`11.
`
`I earned my M.S. (1978) in electrical engineering and Ph.D. (1991) in
`
`computer science from the University of Illinois at Urbana-Champaign after
`
`earning my B.S. (1975) in electrical engineering from Bradley University. During
`
`my master’s program, I designed, constructed and debugged a shared memory
`
`parallel microprocessor system. During my doctoral program, I designed and
`
`simulated a massively parallel, multi-threaded task flow computer.
`
`12. After receiving my bachelor’s degree and while pursuing my master’s
`
`degree, I worked for Hewlett-Packard Co. While at Hewlett-Packard, I designed
`
`the micro-sequencer and cache of the HP3000 Series 64 processor. From 1980 to
`
`1999, I worked at Tandem Computers, which was acquired by Compaq Computers
`
`in 1997. While at Tandem, I was a designer and architect of several generations of
`
`fault-tolerant computer systems and was the principal architect of the NonStop
`
`Cyclone superscalar processor. The system development work at Tandem also
`
`included development of the ServerNet System Area Network and application of
`
`
`
`- 3 -
`
`0008
`
`

`
`U.S. Patent No. 6,546,439 B1
`
`this network to fault tolerant systems, clusters of database servers, and a prototype
`
`pipelined graphics rendering engine.
`
`13. Since leaving Compaq in 1999, I have worked with several
`
`technology companies, including 3Ware, Network Appliance, Tibion, and AlterG
`
`in the areas of computer design and biomedical devices. From 2012 to 2015, I was
`
`Chief Technology Officer of Robotics at AlterG, Inc., where I worked on the
`
`design of anti-gravity treadmills and orthotic devices to assist those with impaired
`
`mobility.
`
`14.
`
`In 2001, I was elected an IEEE Fellow “for contributions to the
`
`architecture and design of fault tolerant systems and networks.” I have authored
`
`over 30 publications, have worked with patent attorneys on numerous patent
`
`applications, and I am a named inventor on 79 issued U.S. patents.
`
`15. My patents include those directed to multithreaded machines
`
`(5,404,550: Method and apparatus for executing tasks by following a linked list of
`
`memory packets), graphics (6,753,878: Parallel pipelined merge engines;
`
`6,516,032: First-order difference compression for interleaved image data in a high-
`
`speed image compositor), and memory systems (5,329,629: Apparatus and method
`
`for reading, writing, and refreshing memory with direct virtual or physical access).
`
`
`
`- 4 -
`
`0009
`
`

`
`16. My Curriculum Vitae, which is filed as a separate Exhibit (Ex. 1010),
`
`contains further details on my education, experience, publications, and other
`
`U.S. Patent No. 6,546,439 B1
`
`qualifications to render this opinion as expert.
`
`III. Legal Understanding
`
`A. My Understanding of Claim Construction
`
`17.
`
`I understand that, during an inter partes review, claims are to be given
`
`their broadest reasonable construction in light of the specification as would be read
`
`by a person of ordinary skill in the relevant art (“POSA”) at the time of the
`
`invention. I understand that claim terms are given their ordinary and customary
`
`meaning as would be understood by a POSA in the context of the entire disclosure.
`
`A claim term, however, will not receive its ordinary meaning if the patentee acted
`
`as his own lexicographer and clearly set forth a definition of the claim term in the
`
`specification. In that case, the claim term will receive the definition set forth in the
`
`patent.
`
`B. A Person of Ordinary Skill in the Art
`
`18.
`
`I understand that a person of ordinary skill in the art (“POSA”) is
`
`presumed to be aware of all pertinent art, thinks along conventional wisdom in the
`
`art, and is a person of ordinary creativity—not an automaton. With this
`
`understanding, in my opinion, a POSA at the time of the putative invention (i.e.,
`
`December 1998 timeframe) would be a person holding at least the equivalent of a
`
`
`
`- 5 -
`
`0010
`
`

`
`U.S. Patent No. 6,546,439 B1
`
`Bachelor of Science (“B.S.”) degree in Electrical or Computer Engineering and
`
`two to three years of industry experience in the field of memory system design.
`
`Experience could take the place of some formal training, as domain knowledge
`
`may be learned on the job. This description is approximate, and a higher level of
`
`education or skill might make up for less education and vice versa.
`
`19.
`
`I am well qualified to determine the level of ordinary skill in the art
`
`for at least the following reasons.
`
`20. First, I am personally very familiar with the memory system
`
`technology of the ’439 patent in the December 1998 timeframe due to my work at
`
`Compaq Computers, as noted above.
`
`21. Second, my master’s work acquainted me with memory system
`
`design, a topic in which I have maintained a professional interest since that time.
`
`C. My Understanding of Anticipation
`
`22.
`
`I understand that a claimed invention is anticipated only if each and
`
`every element as set forth in the claim is found, either expressly or inherently
`
`described, in a single prior art reference.
`
`23.
`
`I understand that an element is inherently described in the prior art
`
`when it is necessarily present, even though it is not explicitly mentioned.
`
`24.
`
`It is my understanding that anticipation is a question of fact.
`
`D. My Understanding of Obviousness
`
`
`
`- 6 -
`
`0011
`
`

`
`U.S. Patent No. 6,546,439 B1
`
`25.
`
`I understand that a patent claim is invalid if the claimed invention
`
`would have been obvious to a person of ordinary skill in the field at the time of the
`
`purported invention, which is often considered the time the application was filed.
`
`This means that even if all of the requirements of the claim cannot be found in a
`
`single prior art reference that would anticipate the claim, the claim can still be
`
`invalid.
`
`26. As part of this inquiry, I have been asked to consider the level of
`
`ordinary skill in the field that someone would have had at the time the claimed
`
`invention was made. In deciding the level of ordinary skill, I considered the
`
`following:
`
` the levels of education and experience of persons working in the field;
`
` the types of problems encountered in the field; and
`
` the sophistication of the technology.
`
`27. To obtain a patent, a claimed invention must have, as of the priority
`
`date, been nonobvious in view of the prior art in the field. I understand that an
`
`invention is obvious when the differences between the subject matter sought to be
`
`patented and the prior art are such that the subject matter as a whole would have
`
`been obvious at the time the invention was made to a person having ordinary skill
`
`in the art.
`
`
`
`- 7 -
`
`0012
`
`

`
`U.S. Patent No. 6,546,439 B1
`
`28.
`
`I understand that to prove that prior art or a combination of prior art
`
`renders a patent obvious, it is necessary to (1) identify the particular references
`
`that, singly or in combination, make the patent obvious; (2) specifically identify
`
`which elements of the patent claim appear in each of the asserted references; and
`
`(3) explain how the prior art references could have been combined in order to
`
`create the inventions claimed in the asserted claim.
`
`29.
`
`I understand that certain objective indicia can be important evidence
`
`regarding whether a patent is obvious or nonobvious. Such indicia include:
`
`commercial success of products covered by the patent claims; a long-felt need for
`
`the invention; failed attempts by others to make the invention; copying of the
`
`invention by others in the field; unexpected results achieved by the invention as
`
`compared to the closest prior art; praise of the invention by the infringer or others
`
`in the field; the taking of licenses under the patent by others; expressions of
`
`surprise by experts and those skilled in the art at the making of the invention; and
`
`the patentee proceeded contrary to the accepted wisdom of the prior art.
`
`30.
`
`I also understand that when considering the obviousness of a patent
`
`claim, one should consider whether a teaching, suggestion, or motivation to
`
`combine the references exists so as to avoid impermissibly applying hindsight
`
`when considering the prior art. I understand this test should not be rigidly applied,
`
`but that the test can be important to avoiding such hindsight.
`
`
`
`- 8 -
`
`0013
`
`

`
`U.S. Patent No. 6,546,439 B1
`
`IV. Background of Memory Controllers for Scheduling Memory Requests
`
`A. Memory controllers are well known.
`
`31. Shared memory was a design concept that was used in various
`
`generations of PC architecture, and this shared memory concept was in wide use
`
`by the mid-90’s. This architectural approach allowed for the use of single memory
`
`by a variety of devices. Thus, various devices such as a central processor unit, an
`
`I/O device, and the like may access the shared memory. U.S. Patent No. 5,854,905
`
`to John I. Garney (Ex. 1009, “Garney”) describes the architecture of a typical PC
`
`computer system at the time of September 1996 (the filing date of the patent
`
`application that led to U.S. Patent No. 5,854,905). In particular, FIG. 2 illustrates
`
`memory 22, and an architecture that allows memory access by CPU 12, video
`
`controller 42 and various I/O devices. This Garney reference also provides a
`
`description that includes:
`
`FIG. 2 shows the architecture of a typical personal computer system in
`
`accordance with accepted practice. A main system bus 2, such as a
`
`Peripheral Component Interconnect (PCI) bus, connects together all the
`
`main components of a computer system. A CPU 12 of the computer system
`
`is isolated from the system bus 2 by a "Northbridge" 100 which essentially
`
`mates the CPU for read and write access to memory 22 (usually RAM). The
`
`Northbridge 100 also mates the CPU 12 for read and write access to the
`
`
`
`- 9 -
`
`0014
`
`

`
`U.S. Patent No. 6,546,439 B1
`
`system bus 2 for interaction with I/O devices located elsewhere in the
`
`system. (Garney, 3:44-54.)
`
`32. As Garney notes (circa 1996), a POSA would have been familiar that
`
`as part of the shared memory architecture, a memory controller is used to control
`
`memory requests from the variety of devices that share the memory. This memory
`
`controller is usually located in the Northbridge element in typical PC computer
`
`architectures. The memory controller accepts the memory access requests from
`
`various devices and provides an arbitration function. The arbitration function
`
`determines which memory access request should have first access, i.e., the order by
`
`which the memory access requests would be handled. For example, the arbitration
`
`function may schedule the memory access requests in the order that they are
`
`received. Alternatively, the arbitration function may schedule a memory access
`
`request from an I/O device ahead of a request from a CPU. Although scheduling
`
`memory access requests to be executed in the order received is more
`
`straightforward, it was quickly recognized that it was not efficient to do so.
`
`V. Technical Analysis of the ’439 Patent
`
`A. Technical Summary
`
`33. The ʼ439 specification confirms that a shared memory architecture
`
`was well known for use in computer architecture. In the background portion of the
`
`ʼ439 specification, reference is made to well-known concepts such as the
`
`
`
`- 10 -
`
`0015
`
`

`
`U.S. Patent No. 6,546,439 B1
`
`Northbridge, a memory controller, the Peripheral Component Interconnect (PCI)
`
`bus, and the Accelerated Graphics Port Interface Specification (AGP interface
`
`standard). (ʼ439 Patent, 2:4-3:20.) Furthermore, the background section of the
`
`ʼ439 specification acknowledges that it was well known in the art that a “memory
`
`controller controls access to system memory.” (ʼ439 Patent, 3:14-15.) The same
`
`background section also describes the use of “page mode” memory. (ʼ439 Patent,
`
`4:7.) In addition, the background section acknowledges that “[c]urrent memory
`
`controllers already ‘look ahead’ to see if pending memory accesses are destined
`
`for currently open pages.” (ʼ439 Patent, 4:24-26 (emphasis added).) The
`
`background section also notes that it would be “an efficient strategy which may be
`
`employed by the memory controller is that it selects which ones of the memory
`
`accesses to be executed are intended for pages which are already open.” (ʼ439
`
`Patent, 4:34-37.)
`
`34. Based on this introduction, the ʼ439 specification proceeds to describe
`
`a variety of scenarios by which a memory controller would operate. In Fig. 3, the
`
`ʼ439 specification illustrates, with support from the accompanying text, an
`
`approach by which information from various devices is provided to the memory
`
`controller for use in schedule memory accesses. (ʼ439 Patent, 9:16-35.) Similarly,
`
`in Fig. 4, the ’439 specification illustrates, with support from the accompanying
`
`text, examples of information that may be contained within tags that may be used
`
`
`
`- 11 -
`
`0016
`
`

`
`U.S. Patent No. 6,546,439 B1
`
`for memory access scheduling. (’439 Patent, 9:36-58.) In Fig. 5, the ʼ439
`
`specification illustrates, with support from the accompanying text, an approach
`
`which uses dedicated queues that transmit information related to the identity of the
`
`source upon which the queued memory transactions originate. (’439 Patent, 9:59-
`
`10:13.) Finally, in Fig. 6, the ʼ439 specification illustrates, with support from the
`
`accompanying text, an approach which combines dedicated queues and tags to
`
`provide source attribute information. (ʼ439 Patent, 10:14-45.)
`
`B.
`
`Summary of Prosecution History
`
`35. A copy of the file history of the ʼ439 patent is included as Exhibit
`
`1008. The ʼ439 patent application was filed on December 9, 1998, with claims 1-
`
`32. The Patent Office issued a first rejection on October 2, 2001, rejecting all
`
`claims as lacking enablement, as being indefinite, and lacking patentability based
`
`on two prior art references. In particular, the Office Action rejected claims 1, 2, 6-
`
`13, 17, 18 and 23-29 as being anticipated by U.S. Patent No. 6,295,592
`
`(“Jeddeloh”). The Office Action also rejected dependent claims 3-5 and 19-21 as
`
`obvious over Jeddeloh. The Office Action rejected dependent claims 14-16 and 30-
`
`32 as obvious over Jeddeloh in view of a secondary reference – U.S. Patent No.
`
`6,112,265 to Harriman et al. (“Harriman”).
`
`36.
`
`In their December 21, 2001 response, Applicants amended claims 1,
`
`14, and 17 to incorporate the feature of “wherein the requested memory operation
`
`
`
`- 12 -
`
`0017
`
`

`
`U.S. Patent No. 6,546,439 B1
`
`buffer is further structured to identify an address and a memory operation type of
`
`the requested memory operation.” Applicants also argued that these original claims
`
`were enabled and the terms were not indefinite.
`
`37.
`
`In a subsequent Final Office Action, mailed January 16, 2002, the
`
`Examiner withdrew the enablement and indefiniteness rejections, but maintained
`
`the prior art rejections based on Jeddeloh and Harriman.
`
`38.
`
`In their April 22, 2002 response, Applicants filed a Request for
`
`Continued Examination, which cancelled claims 1-32 and added new claims 33-64.
`
`Applicants argued that new claims 33-64 are patentable over the art of record
`
`based on, for example, the feature “a requested memory operation buffer
`
`configured to receive memory requests from a plurality of sources, wherein said
`
`requested memory operation buffer is further configured to provide, for each
`
`memory request, a source indication of the one of said plurality of sources from
`
`which the memory request was received,” as recited in claim 33 (now claim 1).
`
`Applicants further argued that “none of the ‘address, type of transfer and count’
`
`mentioned at col. 4, line 20, of Jeddeloh provide for each memory request an
`
`indication of which one of a plurality of sources was the source of the memory
`
`request.”
`
`39.
`
`In the subsequent Office Action mailed May 21, 2002, the Examiner
`
`rejected all pending claims based on U.S. Patent No. 6,112,265 to Harriman et al.
`
`
`
`- 13 -
`
`0018
`
`

`
`U.S. Patent No. 6,546,439 B1
`
`(“Harriman”). In particular, the Examiner noted that a source indication must
`
`inherently be there for the system to return data to the initiator. The Examiner also
`
`noted that the use of “parameters [that] comprise an identity of a stream or thread
`
`that initiated the memory request … is a mere matter of design choice.”
`
`40.
`
`In their August 23, 2002 response, Applicants argued that the
`
`inherency argument was flawed in that Harriman’s approach “might return data to
`
`the initiator in any number of ways independent of providing or associating a
`
`source indication with memory requests.”
`
`41. A Notice of Allowance was mailed on September 25, 2002, and the
`
`ʼ439 patent issued on April 8, 2003, with claims 33-64 renumbered as 1-32
`
`respectively. The Examiner’s statement of the reasons for allowance merely stated
`
`the text of the independent claims was “not taught or suggested by the cited prior
`
`art of record.”
`
`42. Based on the prosecution history, the purported novelty of the ’439
`
`patent claims resides in the feature that was incorporated into the independent
`
`claims in the Reply filed with the Request for Continued Prosecution. However,
`
`this feature—“a requested memory operation buffer configured to receive memory
`
`requests from a plurality of sources, wherein said requested memory operation
`
`buffer is further configured to provide, for each memory request, a source
`
`indication of the one of said plurality of sources from which the memory request
`
`
`
`- 14 -
`
`0019
`
`

`
`was received” (original claim 33, now recited in independent claim 1) is not
`
`patentable. Rather, this feature is clearly disclosed in the prior art, as demonstrated
`
`U.S. Patent No. 6,546,439 B1
`
`below.
`
`
`
`VI. Understanding of Certain Claim Terms
`
`A.
`
`Source Indication
`
`43. Based upon my analysis, “source indication” should be construed as
`
`its plain and ordinary meaning: “information that can be used to determine the
`
`source of the memory request.” Although the as-filed specification did not define
`
`or recite a “source indication,” the claims, specification, and figures of the ’439
`
`patent support this construction. Claim 14, for example, indicates that in a
`
`requested memory buffer having a separate memory request queue for each source,
`
`the “said source indication corresponds to one of said memory request queues.”
`
`(’439 patent, 13:13-20.) Further, the ’439 specification discloses that “due to
`
`[queues 600-604’s] association[s] with the various buses 102, 115, 118, queues
`
`600-604 convey information about the sources of the queued memory
`
`transactions.” (Id., 10:20-23.) Thus, a POSA would have understood a “source
`
`indication” to mean “information that can be used to determine the source of the
`
`memory request.”
`
`
`
`- 15 -
`
`0020
`
`

`
`U.S. Patent No. 6,546,439 B1
`
`B.
`
`Tag
`
`44. Based upon my analysis, a “tag” should be construed as its plain and
`
`ordinary meaning: “a data structure that includes information associated with a
`
`memory access request.” The ’439 specification discloses: “Further shown is that
`
`requested memory operation buffer 336 may be further structured such that each
`
`memory operation within requested memory operation buffer 336 may also have
`
`associated with that memory operation a ‘tag’ 302 which may contain one or more
`
`units indicative of one or more parameters related to the transaction in question.”
`
`(Id., 9:25-31.) The usage of the word “tag” in the specification, as exemplified by
`
`the above cited passage, indicates that the term “tag” captures the notion of request
`
`information accompanying memory accesses. Thus, a POSA would have
`
`understood a “tag” to mean “a data structure that includes information associated
`
`with a memory access request.”
`
`VII. Pattin Ground 1: Claims 1-7, 10-13, 15, 17-23, 26-29 and 31 are obvious
`over Pattin and Lewchuk
`
`A. Overview of Pattin
`
`45. Like the ’439 patent, Pattin is directed to a memory controller that
`
`intelligently re-orders memory requests from a plurality of sources to optimize
`
`bandwidth to an external DRAM memory. (Pattin, 1:51-54.)
`
`
`
`- 16 -
`
`0021
`
`

`
`
`
`446. FIG. 6 (bottom)) depicts a diagram oof Pattin’s
`
`
`
`
`
`
`
`
`
`UU.S. Patentt No. 6,5466,439 B1
`
`
`
`memory syystem withh
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`commonn elementss previouslly describeed with resppect to a DDRAM conntroller 56
`
`
`
`
`
`
`
`
`
`
`
`shown iin FIG. 4. ((Id., 6:55-556, 7:53-555.)
`
`
`
`
`
`
`
`447. Here, request qqueue 26 reeceives memmory requuest from a
`
`
`
`
`
`
`
`
`
`
`
`
`
`plurality oof
`
`sources
`
`including
`
`
`
`CPU cores 42-48, SCCI 57, andd PCI 58, wwhen the mmemory reqquest
`
`
`
`
`
`
`
`
`
`missed
`
`
`in second--level cach
`
`
`
`e 60. (Id., 6:64-7:3.)
`
`Then, the
`
`
`
`request prrioritizer 222
`
`
`
`
`
`
`
`“examinnes the pennding requ
`
`
`
`
`ermine whe 26 to deteests in requuest queue
`
`
`
`ich request
`t
`
`14-16.)
`
`
`
`should bbe processed next byy request prrocessor 244.” (Id., 8:
`
`
`
`
`
`
`
`
`
`
`
`448. To mmaximize mmemory banndwidth, PPattin descrribes that tthe requestt
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`prioritizzer groups requests toogether by bank and
`
`
`
`
`
`
`
`
`
`row-hit requests bbefore otheer row-misss requests.
`
`
`
`
`
`
`
`
`
`
`
`
`
`row, and tthen re-ordder and proocess
`
`
`
`(Id., 8:25--32.) But PPattin
`
`
`
`
`recogni
`
`
`
`
`
`
`
`
`
`zed that thhis request--schedulingg scheme ccould causee “just onee or a few oof
`
`
`
`
`
`
`
`- 17 -
`
`0022
`
`

`
`U.S. Patent No. 6,546,439 B1
`
`the sources [to] hog the DRAM, since the highest priority is given to row-hits.”
`
`(Id., 11:56-58.)
`
`49. To prevent one source from always having highest priority, Pattin
`
`describes implementing a round-robin scheme such that “[e]ach source is allowed
`
`two accesses to a bank before any other sources are allowed to win priority.” (Id.,
`
`11:64-67.) Pattin continues to prior

This document is available on Docket Alarm but you must sign up to view it.


Or .

Accessing this document will incur an additional charge of $.

After purchase, you can access this document again without charge.

Accept $ Charge
throbber

Still Working On It

This document is taking longer than usual to download. This can happen if we need to contact the court directly to obtain the document and their servers are running slowly.

Give it another minute or two to complete, and then try the refresh button.

throbber

A few More Minutes ... Still Working

It can take up to 5 minutes for us to download a document if the court servers are running slowly.

Thank you for your continued patience.

This document could not be displayed.

We could not find this document within its docket. Please go back to the docket page and check the link. If that does not work, go back to the docket and refresh it to pull the newest information.

Your account does not support viewing this document.

You need a Paid Account to view this document. Click here to change your account type.

Your account does not support viewing this document.

Set your membership status to view this document.

With a Docket Alarm membership, you'll get a whole lot more, including:

  • Up-to-date information for this case.
  • Email alerts whenever there is an update.
  • Full text search for other cases.
  • Get email alerts whenever a new case matches your search.

Become a Member

One Moment Please

The filing “” is large (MB) and is being downloaded.

Please refresh this page in a few minutes to see if the filing has been downloaded. The filing will also be emailed to you when the download completes.

Your document is on its way!

If you do not receive the document in five minutes, contact support at support@docketalarm.com.

Sealed Document

We are unable to display this document, it may be under a court ordered seal.

If you have proper credentials to access the file, you may proceed directly to the court's system using your government issued username and password.


Access Government Site

We are redirecting you
to a mobile optimized page.





Document Unreadable or Corrupt

Refresh this Document
Go to the Docket

We are unable to display this document.

Refresh this Document
Go to the Docket