UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`VOLKSWAGEN GROUP OF AMERICA, INC.,
`Petitioner
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`v.
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`ADVANCED SILICON TECHNOLOGIES LLC,
`Patent Owner
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`Case IPR2016-TBA
`Patent 6,546,439 B1
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`DECLARATION OF DR. ROBERT W. HORST
`Nielsen-based IPR
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`Mail Stop “PATENT BOARD”
`Patent Trial and Appeal Board
`U.S. Patent & Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
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`Volkswagen 1002
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`0001
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`VOLKSWAGEN GROUP OF AMERICA, INC.,
`Petitioner
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`v.
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`ADVANCED SILICON TECHNOLOGIES LLC,
`Patent Owner
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`Case IPR2016-TBA
`Patent 6,546,439 B1
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`DECLARATION OF DR. ROBERT W. HORST
`Nielsen-based IPR
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`Mail Stop “PATENT BOARD”
`Patent Trial and Appeal Board
`U.S. Patent & Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
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`Volkswagen 1002
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`0001
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`U.S. Patent No. 6,546,439 B1
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`TABLE OF CONTENTS
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`I. Background ......................................................................................................... 5
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`II. Qualifications and Expertise ............................................................................... 6
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`III. Legal Understanding ........................................................................................... 9
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`A. My Understanding of Claim Construction ...................................................... 9
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`B. A Person of Ordinary Skill in the Art .............................................................. 9
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`C. My Understanding of Anticipation ................................................................10
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`D. My Understanding of Obviousness ...............................................................10
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`IV. Background of Memory Controllers for Scheduling Memory Requests ..........12
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`A. Memory controllers are well known. .............................................................12
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`V. Technical Analysis of the ’439 Patent ..............................................................14
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`E. Technical Summary .......................................................................................14
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`F. Summary of Prosecution History ..................................................................16
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`VI. Understanding of Certain Claim Terms ............................................................19
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`A. Source Indication ...........................................................................................19
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`B. Tag .................................................................................................................20
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`VII. Ground 1: Claims 1, 2, 11, 14, 15, 17, 18, 27, 30 and 31 are obvious over
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`Nielsen and Talbot ...................................................................................................20
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`1. Overview of Nielsen...................................................................................21
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`0002
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`U.S. Patent No. 6,546,439 B1
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`2. Overview of Talbot ....................................................................................23
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`3. Rationale for combining Nielsen and Talbot .............................................25
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`4. Claim 1 is obvious over Nielsen and Talbot ..............................................29
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`5. Claim 2 is obvious over Nielsen and Talbot ..............................................36
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`6. Claim 11 is obvious over Nielsen and Talbot ............................................38
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`7. Claim 14 is obvious over Nielsen and Talbot ............................................39
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`8. Claim 15 is obvious over Nielsen and Talbot ............................................41
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`9. Claim 17 is obvious over Nielsen and Talbot ............................................42
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`10. Claim 18 is obvious over Nielsen and Talbot.........................................43
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`11. Claim 27 is obvious over Nielsen and Talbot.........................................43
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`12. Claim 30 is obvious over Nielsen and Talbot.........................................44
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`13. Claim 31 is obvious over Nielsen and Talbot.........................................44
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`VIII. Ground 2: Claims 3-7, 10, 12, 13, 19-23, 26, 28 and 29 are obvious over
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`Nielsen, Talbot and Lewchuk ..................................................................................45
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`14. Overview of Lewchuk ............................................................................45
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`15. Rationale for combining Nielsen, Talbot and Lewchuk .........................46
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`16. Claim 3 is obvious over Nielsen, Talbot and Lewchuk ..........................49
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`17. Claim 4 is obvious over Nielsen, Talbot and Lewchuk ..........................52
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`18. Claim 5 is obvious over Nielsen, Talbot and Lewchuk ..........................54
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`0003
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`U.S. Patent No. 6,546,439 B1
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`19. Claim 6 is obvious over Nielsen, Talbot and Lewchuk ..........................55
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`20. Claim 7 is obvious over Nielsen, Talbot and Lewchuk ..........................57
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`21. Claim 10 is obvious over Nielsen, Talbot and Lewchuk........................59
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`22. Claim 12 is obvious over Nielsen, Talbot and Lewchuk........................60
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`23. Claim 13 is obvious over Nielsen, Talbot and Lewchuk........................62
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`24. Claim 19 is obvious over Nielsen, Talbot and Lewchuk........................63
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`25. Claim 20 is obvious over Nielsen, Talbot and Lewchuk........................63
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`26. Claim 21 is obvious over Nielsen, Talbot and Lewchuk........................64
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`27. Claim 22 is obvious over Nielsen, Talbot and Lewchuk........................64
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`28. Claim 23 is obvious over Nielsen, Talbot and Lewchuk........................64
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`29. Claim 26 is obvious over Nielsen, Talbot and Lewchuk........................65
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`30. Claim 28 is obvious over Nielsen, Talbot and Lewchuk........................65
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`31. Claim 29 is obvious over Nielsen, Talbot and Lewchuk........................66
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`IX. Ground 3: Claims 8, 16, 24 and 32 are obvious over Nielsen, Talbot, Lewchuk
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`and Wulf ...................................................................................................................66
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`32. Overview of Wulf ...................................................................................66
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`33. Rationale for combining Nielsen, Talbot, Lewchuk and Wulf ..............68
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`34. Claim 8 is obvious over Nielsen, Talbot, Lewchuk, and Wulf ..............72
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`35. Claim 16 is obvious over Nielsen, Talbot, Lewchuk, and Wulf ............74
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`0004
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`U.S. Patent No. 6,546,439 B1
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`36. Claim 24 is obvious over Nielsen, Talbot, Lewchuk, and Wulf ............77
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`37. Claim 32 is obvious over Nielsen, Talbot, Lewchuk, and Wulf ............77
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`X. Ground 4: Claims 9 and 25 are obvious over Nielsen, Talbot, Lewchuk and
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`DiNicola ...................................................................................................................78
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`38. Overview of DiNicola .............................................................................78
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`39. Rationale for combining Nielsen, Talbot, Lewchuk and DiNicola ........81
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`40. Claim 9 is obvious over Nielsen, Talbot, Lewchuk and DiNicola .........85
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`41. Claim 25 is obvious over Nielsen, Talbot, Lewchuk, and DiNicola ......87
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`XI. Conclusion .........................................................................................................88
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`0005
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`I, Dr. Robert W. Horst, declare as follows:
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`I. Background
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`1.
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`I have been retained as an expert witness by Sterne, Kessler,
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`Goldstein & Fox, P.L.L.C. to provide testimony on behalf of Volkswagen Group of
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`America, Inc. (“Volkswagen”), for the above-captioned inter partes review
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`proceeding. I understand that this proceeding involves U.S. Patent No. 6,546,439
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`B1 (“’439 patent”), entitled “Method and System for Improved Data Access” by
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`Geoffrey S. Strongin and Qadeer A. Qureshi. I understand that the ’439 patent was
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`filed on December 9, 1998, issued on April 8, 2003, and is currently assigned to
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`Advanced Silicon Technologies, LLC (“AST”).
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`2.
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`I have reviewed and am familiar with the specification of the ’439
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`patent. I understand that the ’439 patent has been provided as Exhibit 1001. I will
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`cite to the specification using the following format: (’439 patent, 1:1-10.) This
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`example citation points to the ’439 patent specification at column 1, lines 1-10.
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`3.
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`I have reviewed and am familiar with the file history of the ’439
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`patent. I understand that the file history has been provided as Exhibit 1008.
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`4.
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`I have also reviewed and am familiar with the following prior art used
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`in the Petition for inter partes review of the ’439 patent:
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`U.S. Patent No. 6,104,417 to Nielsen et al. (Ex. 1003, “Nielsen”);
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`U.S. Patent No. 6,976,135 to Talbot et al. (Ex. 1004, “Talbot”);
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`0006
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`U.S. Patent No. 6,058,461 to Lewchuk et al. (Ex. 1005, “Lewchuk”);
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`U.S. Patent No. 6,154,826 to Wulf et al. (Ex. 1006, “Wulf”); and
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`U.S. Patent No. 5,394,524 to DiNicola et al. (Ex. 1007, “DiNicola”).
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`5.
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`The ’439 patent describes a memory controller that schedules accesses
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`to a system memory based on source attributes or other parameters associated with
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`the requested memory accesses. (’439 patent, Abstract.) I am familiar with the
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`technology described in the ’439 patent as of its earliest possible priority date (i.e.,
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`December 9, 1998).
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`6.
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`I have been asked to provide my technical review, analysis, insights
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`and opinions regarding the ’439 patent and the above-noted references that form
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`the basis for the grounds of unpatentability set forth in the Petition for inter partes
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`review that this Declaration supports.
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`7.
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`I am being compensated at my regular hourly rate, with
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`reimbursement for actual expenses. My compensation is not dependent on the
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`outcome of this inter partes review and in no way affects the substance of my
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`statements in this declaration.
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`II. Qualifications and Expertise
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`8.
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`I am an independent consultant with more than 30 years’ expertise in
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`the design and architecture of computer systems. I have been asked to offer
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`technical opinions relating to U.S. Patent No. 6,546,439, and prior art references
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`0007
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`relating to the related subject matter. My current curriculum vitae is submitted as
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`Exhibit 1010, and some highlights follow.
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`9.
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`Currently, I am an independent consultant at HT Consulting where my
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`work includes consulting on technology and intellectual property. I have testified
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`as an expert witness and consultant in patent and intellectual property litigation as
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`well as inter partes reviews and re-examination proceedings.
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`10.
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`I earned my M.S. (1978) in electrical engineering and Ph.D. (1991) in
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`computer science from the University of Illinois at Urbana-Champaign after
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`earning my B.S. (1975) in electrical engineering from Bradley University. During
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`my master’s program, I designed, constructed and debugged a shared memory
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`parallel microprocessor system. During my doctoral program, I designed and
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`simulated a massively parallel, multi-threaded task flow computer.
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`11. After receiving my bachelor’s degree and while pursuing my master’s
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`degree, I worked for Hewlett-Packard Co. While at Hewlett-Packard, I designed
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`the micro-sequencer and cache of the HP3000 Series 64 processor. From 1980 to
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`1999, I worked at Tandem Computers which was acquired by Compaq Computers
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`in 1997. While at Tandem, I was a designer and architect of several generations of
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`fault-tolerant computer systems and was the principal architect of the NonStop
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`Cyclone superscalar processor. The system development work at Tandem also
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`included development of the ServerNet System Area Network and application of
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`this network to fault tolerant systems, clusters of database servers, and a prototype
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`pipelined graphics rendering engine.
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`12. Since leaving Compaq in 1999, I have worked with several
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`technology companies, including 3Ware, Network Appliance, Tibion and AlterG
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`in the areas of computer design and biomedical devices. From 2012 to 2015, I was
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`Chief Technology Officer of Robotics at AlterG, Inc. where I worked on the design
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`of anti-gravity treadmills and orthotic devices to assist those with impaired
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`mobility.
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`13.
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`In 2001, I was elected an IEEE Fellow “for contributions to the
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`architecture and design of fault tolerant systems and networks.” I have authored
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`over 30 publications, have worked with patent attorneys on numerous patent
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`applications, and I am a named inventor on 79 issued U.S. patents.
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`14. My patents include those directed to multithreaded machines
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`(5,404,550: Method and apparatus for executing tasks by following a linked list of
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`memory packets), graphics (6,753,878: Parallel pipelined merge engines;
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`6,516,032: First-order difference compression for interleaved image data in a high-
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`speed image compositor), and memory systems (5,329,629: Apparatus and method
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`for reading, writing, and refreshing memory with direct virtual or physical access).
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`15. My Curriculum Vitae, which is filed as a separate Exhibit, contains
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`further details on my education, experience, publications, and other qualifications
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`to render this opinion as expert.
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`III. Legal Understanding
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`A. My Understanding of Claim Construction
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`16.
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`I understand that, during an inter partes review, claims are to be given
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`their broadest reasonable construction in light of the specification as would be read
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`by a person of ordinary skill in the relevant art (“POSA”) at the time of the
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`invention. I understand that claim terms are given their ordinary and customary
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`meaning as would be understood by a POSA in the context of the entire disclosure.
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`A claim term, however, will not receive its ordinary meaning if the patentee acted
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`as his own lexicographer and clearly set forth a definition of the claim term in the
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`specification. In that case, the claim term will receive the definition set forth in the
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`patent.
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`B. A Person of Ordinary Skill in the Art
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`17.
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`I understand that a POSA is presumed to be aware of all pertinent art,
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`thinks along conventional wisdom in the art, and is a person of ordinary
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`creativity—not an automaton. With this understanding, in my opinion, a POSA at
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`the time of the putative invention (i.e., December 1998 timeframe) would be a
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`person holding at least the equivalent of a Bachelor of Science (“B.S.”) degree in
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`Electrical or Computer Engineering and two to three years of industry experience
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`in the field of memory system design. Experience could take the place of some
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`formal training, as domain knowledge may be learned on the job. This description
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`is approximate, and a higher level of education or skill might make up for less
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`education and vice versa.
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`18.
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`I am well qualified to determine the level of ordinary skill in the art
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`for at least the following reasons.
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`19. First, I am personally very familiar with the memory system
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`technology of the ’439 patent in the December 1998 timeframe due to my work at
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`Compaq Computers, as noted above.
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`20. Second, my master’s work acquainted me with memory system
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`design, a topic with which I have maintained a professional interest since that time.
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`C. My Understanding of Anticipation
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`21.
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`I understand that a claimed invention is anticipated only if each and
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`every element as set forth in the claim is found, either expressly or inherently
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`described, in a single prior art reference.
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`22.
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`I understand that an element is inherently described in the prior art
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`when it is necessarily present, even though it is not explicitly mentioned.
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`23.
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`It is my understanding that anticipation is a question of fact.
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`D. My Understanding of Obviousness
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`24.
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`I understand that a patent claim is invalid if the claimed invention
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`would have been obvious to a POSA at the time of the purported invention, which
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`is often considered the time the application was filed. This means that even if all
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`of the requirements of the claim cannot be found in a single prior art reference that
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`would anticipate the claim, the claim can still be invalid.
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`25. As part of this inquiry, I have been asked to consider the level of
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`ordinary skill in the field that someone would have had at the time the claimed
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`invention was made. In deciding the level of ordinary skill, I considered the
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`following:
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`• the levels of education and experience of persons working in the field;
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`• the types of problems encountered in the field; and
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`• the sophistication of the technology.
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`26. To obtain a patent, a claimed invention must have, as of the priority
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`date, been nonobvious in view of the prior art in the field. I understand that an
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`invention is obvious when the differences between the subject matter sought to be
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`patented and the prior art are such that the subject matter as a whole would have
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`been obvious at the time the invention was made to a POSA.
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`27.
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`I understand that to prove that prior art or a combination of prior art
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`renders a patent obvious, it is necessary to (1) identify the particular references
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`that, singly or in combination, make the patent obvious; (2) specifically identify
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`which elements of the patent claim appear in each of the asserted references; and
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`(3) explain how the prior art references could have been combined in order to
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`create the inventions claimed in the asserted claim.
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`28.
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`I understand that certain objective indicia can be important evidence
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`regarding whether a patent is obvious or nonobvious. Such indicia include:
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`commercial success of products covered by the patent claims; a long-felt need for
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`the invention; failed attempts by others to make the invention; copying of the
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`invention by others in the field; unexpected results achieved by the invention as
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`compared to the closest prior art; praise of the invention by the infringer or others
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`in the field; the taking of licenses under the patent by others; expressions of
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`surprise by experts and those skilled in the art at the making of the invention; and
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`the patentee proceeded contrary to the accepted wisdom of the prior art.
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`29.
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`I also understand that when considering the obviousness of a patent
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`claim, one should consider whether a teaching, suggestion, or motivation to
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`combine the references exists so as to avoid impermissibly applying hindsight
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`when considering the prior art. I understand this test should not be rigidly applied,
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`but that the test can be important to avoiding such hindsight.
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`IV. Background of Memory Controllers for Scheduling Memory Requests
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`A. Memory controllers are well known.
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`30. Shared memory was a design concept that was used in various
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`generations of PC architecture, and this shared memory concept was in wide use
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`by the mid-1990’s. This architectural approach allowed for the use of single
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`memory by a variety of devices. Thus, various devices such as a central processor
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`unit, an I/O device, and the like may access the shared memory. U.S. Patent No.
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`5,854,905 to John I. Garney (Ex. 1009, “Garney”) describes the architecture of a
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`typical PC computer system at the time of September 1996 (the filing date of the
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`patent application that led to U.S. Patent No. 5,854,905). In particular, FIG. 2
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`illustrates memory 22, and an architecture that allows memory access by CPU 12,
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`video controller 42 and various I/O devices. This Garney reference also provides a
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`description that includes:
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`FIG. 2 shows the architecture of a typical personal computer system in
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`accordance with accepted practice. A main system bus 2, such as a
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`Peripheral Component Interconnect (PCI) bus, connects together all the
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`main components of a computer system. A CPU 12 of the computer system
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`is isolated from the system bus 2 by a "Northbridge" 100 which essentially
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`mates the CPU for read and write access to memory 22 (usually RAM). The
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`Northbridge 100 also mates the CPU 12 for read and write access to the
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`system bus 2 for interaction with I/O devices located elsewhere in the
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`system. (Garney, 3:44-54.)
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`31. As Garney notes (circa 1996), a POSA would have been familiar that
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`as part of the shared memory architecture, a memory controller is used to control
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`memory requests from the variety of devices that share the memory. This memory
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`controller is usually located in the Northbridge element in typical PC computer
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`architectures. The memory controller accepts the memory access requests from
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`various devices, and provides an arbitration function. The arbitration function
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`determines which memory access request should have first access, i.e., the order by
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`which the memory access requests would be handled. For example, the arbitration
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`function may schedule the memory access requests in the order that they are
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`received. Alternatively, the arbitration function may schedule a memory access
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`request from an I/O device ahead of a request from a CPU. Although scheduling
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`memory access requests to be executed in the order received is more
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`straightforward, it was quickly recognized that it was not efficient to do so.
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`V. Technical Analysis of the ’439 Patent
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`E.
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`Technical Summary
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`32. The ’439 specification confirms that a shared memory architecture
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`was well known for use in computer architecture. In the background portion of the
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`’439 specification, reference is made to well-known concepts such as the
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`Northbridge, a memory controller, the Peripheral Component Interconnect (PCI)
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`bus, and the Accelerated Graphics Port Interface Specification (AGP interface
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`standard). (’439 Patent, 2:4-3:20.) Furthermore, the background section of the
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`’439 specification acknowledges that it was well known in the art that a “memory
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`controller controls access to system memory.” (Id., 3:14-15.) The same
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`background section also describes the use of “page mode” memory. (Id., 4:7.) In
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`addition, the background section acknowledges that “[c]urrent memory
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`controllers already ‘look ahead’ to see if pending memory accesses are destined
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`for currently open pages.” (Id., 4:24-26 (emphasis added).) The background
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`section also notes that it would be “an efficient strategy which may be employed
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`by the memory controller is that it selects which ones of the memory accesses to be
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`executed are intended for pages which are already open.” (Id., 4:34-37.)
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`33. Based on this introduction, the ’439 specification proceeds to describe
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`a variety of scenarios by which a memory controller would operate. In Fig. 3, the
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`’439 specification illustrates, with support from the accompanying text, an
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`approach by which information from various devices is provided to the memory
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`controller for use in schedule memory accesses. (Id., 9:16-35.) Similarly, in Fig. 4,
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`the ’439 specification illustrates, with support from the accompanying text,
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`examples of information that may be contained within tags that may be used for
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`memory access scheduling. (Id., 9:36-58.) In Fig. 5, the ’439 specification
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`illustrates, with support from the accompanying text, an approach which uses
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`dedicated queues that transmit information related to the identity of the source
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`0016
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`upon which the queued memory transactions originate. (Id., 9:59-10:13.) Finally,
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`in Fig. 6, the ’439 specification illustrates, with support from the accompanying
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`text, an approach which combines dedicated queues and tags to provide source
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`attribute information. (Id., 10:14-45.)
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`F.
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`Summary of Prosecution History
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`34. A copy of the file history of the ’439 patent is included as Exhibit
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`1008. The ’439 patent application was filed on December 9, 1998, with claims 1-
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`32. The Patent Office issued a first rejection on October 2, 2001, rejecting all
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`claims as lacking enablement, as being indefinite, and lacking patentability based
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`on two prior art references. In particular, the Office Action rejected claims 1, 2, 6-
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`13, 17, 18 and 23-29 as being anticipated by U.S. Patent No. 6,295,592
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`(“Jeddeloh”). The Office Action also rejected dependent claims 3-5 and 19-21 as
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`obvious over Jeddeloh. The Office Action rejected dependent claims 14-16 and 30-
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`32 as obvious over Jeddeloh in view of a secondary reference – U.S. Patent No.
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`6,112,265 to Harriman et al. (“Harriman”).
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`35.
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`In their December 21, 2001 response, Applicants amended claims 1,
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`14 and 17 to incorporate the feature of “wherein the requested memory operation
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`buffer is further structured to identify an address and a memory operation type of
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`the requested memory operation.” Applicants also argued that these original claims
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`were enabled and the terms were not indefinite.
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`0017
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`36.
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`In a subsequent Final Office Action, mailed January 16, 2002, the
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`Examiner withdrew the enablement and indefiniteness rejections, but maintained
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`the prior art rejections based on Jeddeloh and Harriman.
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`37.
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`In their April 22, 2002 response, Applicants filed a Request for
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`Continued Examination, which cancelled claims 1-32 and added new claims 33-64.
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`Applicants argued that new claims 33-64 are patentable over the art of record
`
`based on, for example, the feature “a requested memory operation buffer
`
`configured to receive memory requests from a plurality of sources, wherein said
`
`requested memory operation buffer is further configured to provide, for each
`
`memory request, a source indication of the one of said plurality of sources from
`
`which the memory request was received,” as recited in claim 33 (now claim 1).
`
`Applicants further argued that “none of the ‘address, type of transfer and count’
`
`mentioned at col. 4, line 20, of Jeddeloh provide for each memory request an
`
`indication of which one of a plurality of sources was the source of the memory
`
`request.”
`
`38.
`
`In the subsequent Office Action mailed May 21, 2002, the Examiner
`
`rejected all pending claims based on U.S. Patent No. 6,112,265 to Harriman et al.
`
`(“Harriman”). In particular, the Examiner noted that a source indication must
`
`inherently be there for the system to return data to the initiator.” The Examiner
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`- 17 -
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`0018
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`
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`also noted that the use of “parameters [that] comprise an identity of a stream or
`
`thread that initiated the memory request … is a mere matter of design choice.”
`
`39.
`
`In their August 23, 2002 response, Applicants argued that the
`
`inherency argument was flawed in that Harriman’s approach “might return data to
`
`the initiator in any number of ways independent of providing or associating a
`
`source indication with memory requests.”
`
`40. A Notice of Allowance was mailed on September 25, 2002, and the
`
`’439 patent issued on April 8, 2003, with claims 33-64 renumbered as 1-32
`
`respectively. The Examiner’s statement of the reasons for allowance merely stated
`
`the text of the independent claims was “not taught or suggested by the cited prior
`
`art of record.”
`
`41. Based on the prosecution history, the purported novelty of the ’439
`
`patent claims resides in the feature that was incorporated into the independent
`
`claims in the Reply filed with the Request for Continued Prosecution. However,
`
`this feature—“a requested memory operation buffer configured to receive memory
`
`requests from a plurality of sources, wherein said requested memory operation
`
`buffer is further configured to provide, for each memory request, a source
`
`indication of the one of said plurality of sources from which the memory request
`
`was received” (original claim 33, now recited in independent claim 1) is not
`
`
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`- 18 -
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`0019
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`
`
`
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`patentable. Rather, this feature is clearly disclosed in the prior art, as demonstrated
`
`below.
`
`
`
`VI. Understanding of Certain Claim Terms
`
`A.
`
`Source Indication
`
`42. Based upon my analysis, “source indication” should be construed as
`
`its plain and ordinary meaning: “information that can be used to determine the
`
`source of the memory request.” Although the as-filed specification did not define
`
`or recite a “source indication,” the claims, specification, and figures of the ’439
`
`patent support this construction. Claim 14, for example, indicates that in a
`
`requested memory buffer having a separate memory request queue for each source,
`
`the “said source indication corresponds to one of said memory request queues.”
`
`(’439 patent, 13:13-20.) Further, the ’439 specification discloses that “due to
`
`[queues 600-604’s] association[s] with the various buses 102, 115, 118, queues
`
`600-604 convey information about the sources of the queue memory transactions.”
`
`(Id., 10:20-23.) Thus, a POSA would have understood a “source indication” to
`
`mean “information that can be used to determine the source of the memory
`
`request.”
`
`
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`- 19 -
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`0020
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`
`
`
`
`B.
`
`Tag
`
`43. Based upon my analysis, a “tag” should be construed as its plain and
`
`ordinary meaning: “a data structure that includes information associated with a
`
`memory access request.” The ’439 specification discloses: “Further shown is that
`
`requested memory operation buffer 336 may be further structured such that each
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`memory operation within requested memory operation buffer 336 may also have
`
`associated with that memory operation a ‘tag’ 302 which may contain one or more
`
`units indicative of one or more parameters related to the transaction in question.”
`
`(Id., 9:25-31.) The usage of the word “tag” in the specification, as exemplified by
`
`the above cited passage, indicates that the term “tag” captures the notion of request
`
`information accompanying memory accesses. Thus, a POSA would have
`
`understood a “tag” to mean “a data structure that includes information associated
`
`with a memory access request.”
`
`VII. Ground 1: Claims 1, 2, 11, 14, 15, 17, 18, 27, 30 and 31 are obvious over
`Nielsen and Talbot
`
`44. The ’439 patent is directed to “increas[ing] the ability of memory
`
`controllers to intelligently schedule accesses [or requests] to system memory”
`
`using information provided for the memory requests. (Id., 4:54-56, 10:46-50.) But
`
`the combination of Nielsen and Talbot teaches or suggests all the features of the
`
`challenged claims. And as set forth below, a POSA would have been motivated to
`
`
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`- 20 -
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`0021
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`
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`
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`combine these references. Thus, the challenged claims are unpatentable in view of
`
`Nielsen and Talbot.
`
`Overview of Nielsen
`1.
`45. Like the ’439 patent, Nielsen is directed to a memory controller that
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`intelligently provides multiple memory clients access to a unified system memory.
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`(Nielsen, 2:28-30.)
`
`46. FIG. 2A (right) depicts a system view of Nielsen’s unified memory
`
`computer architecture. (Id., 3:66-
`
`4:6.) Here, Nielsen’s memory
`
`controller receives and processes
`
`memory clients’ (e.g., CPU 206’s,
`
`image processor 214’s, etc.) “read
`
`and write requests to unified system
`
`memory 202.” (Id., 5:26-28.)
`
`47. FIG. 4 (partially reproduced below; annotations in red added by
`
`Volkswagen) depicts an example memory controller within Nielsen’s unified
`
`memory computer architecture. (Id., 8:9-11.)
`
`
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`- 21 -
`
`0022
`
`
`
`
`
`“requested
`memory
`operation
`buffer”
`
`“memory
`controller”
`
`
`48. To service memory requests from a plurality of sources, e.g., clients,
`
`Nielsen’s memory controller (above) implements an arbiter and associated
`
`arbitration logic within the annotated “request scheduling region.” (Id.) According
`
`to Nielsen, an “arbiter [and associated arbitration logic] determines which memory
`
`client request to pass to the decode stage of the request pipe” for further
`
`processing. (Id., 11:20-21.)
`
`49.
`
`In Nielsen’s unified memory computer architecture, memory
`
`“[c]lients place their requests in a queue. The arbitration logic [within an arbiter]
`
`looks at all of the requests at the top of the client queues and decides which request
`
`to start through the pipe” and process. (Id., 5:37-39.) Particularly, FIG. 4 depicts
`
`that client requests are received at respective client queues within the annotated
`
`“request buffering region.” (Id., 10:59-64 (“All of the memory clients have queues,
`
`except for refresh. . . . The five memory client queues are simple two-port
`
`
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`- 22 -
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`0023
`
`
`
`
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`structures with the memory clients on the write side and the arbitration logic on the
`
`read side.”).)
`
`50. Arbitration is performed for each arbitration slot—that is—a “series
`
`of requests from the same memory client.” (Id., 11:24-25.) And “[i]f the current
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`arbitration slot is terminated, the arbiter uses the results from an arbitration
`
`algorithm to decide which request to pass to the decode stage.” (Id., 11:48-51.)
`
`According to Nielsen, the arbitration algorithm intelligently schedules client’s
`
`memory requests to ensure that each client gets at least a certain proportion
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