lJNITRD STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`
`October 02, 2015
`
`THIS IS TO CERTIFY THAT ANNEXED HERETO IS A TRUE COPY FROM
`THE RI<-:CORDS OF THIS OFFICE OF:
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`U.S. PATENT: 6,33.9,428
`ISSlJI!~ I>ATF:: January 15, 2002
`
`By Authority of the
`Under Secretary of Commerc•e for Intellectual Property
`and Director of the United States Patent and Trademarl<. Office
`
`/Yl
`
`M. TARVER
`Certifying Officer
`
`0001
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`Volkswagen 1001
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`

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`ctz) United States Patent
`Fowler et al.
`
`1111111111111111111111 11111111111110 IIIIIIIIIIIIIIIIIIIIIIIIIIIHIIIIIIIII
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`(10) Patent No.:
`(45) Date of Patent:
`
`US006339428Bl
`US 6,339,428 Bl
`Jan.15, 2002
`
`(54) METHOD AND APPARATUS FOR
`COMI'IU~SSED 'HXI'URE CACHING IN 1\
`VIDEO GRAPHICS SYSTEM
`
`(75)
`
`Inventors: Mark C. J.<'owler, Hopkinton; l'aul
`Vcllu, Dnstnn; Michael '1: Wright,
`Marlborough, a !I of MA (US)
`
`(73) Assignee: ATI Intel'Dationul Sri, Barbados (KN)
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21) Appl. No.: 09/356,398
`
`(22)
`
`riled:
`Jul. 16, 1999
`Int. Cl? .......................... .......•.............. G06T 17100
`(51)
`(52) U.S. Cl ......................................... 345/5112; 345/583
`(58)
`l<1eld of Search ............. .................... 3'15/418, '119,
`345/423, 424, 428, 581, 582, 583
`
`(56)
`
`References Cited
`
`U.S. PA:l"ENT DOCUMEI'I"TS
`
`6,20-1,856 Dl • 3!2001 Wood et aL ................ 345/429
`6,222,555 Ill • 4/2001 ChristofTcTSon et a!. .... 345/430
`6,232,981 n 1 • 5/ 2!lllt Gossett ....................... 345/430
`
`6,256,038 Bl • 7/2001 Krishn3mmtby ............ 345/41 9
`6,268,861 Bl • 7/2001 Sanz-Pastor el al. ........ 345/426
`6,292,194 Rt • 912001 Powell, III .................. 345/430
`6,2!15,070 B I • 9!200t Wood ......................... 345/430
`* cited by examiner
`
`f'rimary F;xaminer····· Cliff N. Yo
`(74) Attomey, Agent, or Firm-Vedder, Price, Kaufman &
`Kammhol:t
`
`(57)
`
`ABSTUACT
`
`1\ method and apparatus for reducing memory bandwidth
`usage in video graphics tcxru riog operations that utilizes
`caching of compressed textures is presented. Texture infor·
`mation (or texturing operations i.s ~:>tored in a memory
`structure in a compressed formal. When texture information
`is needed for a texturing operation, a local cache i.s first
`examined to determine if the texture information required
`for the texturing operation is present within the cache. If it
`is not, the texture information is retrieved fro m the memory
`in a compressed format and stored in the cache in the
`compre.';;:;ed format. "l11e cumpre:;.~ed texture inlimnation is
`then retrieved from the cache each time it is required for a
`te xturing operation and deoompressed prior to use in such
`texturing operations.
`
`30 Claims, 3 Drawing Sheets
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`Texture
`Address
`Module
`30
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`!Q
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`Additional
`Color Values
`72
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`Uncomprcssed
`T exturc Data
`62
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`Filtering 13lock
`60
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`l'rnme Buffer
`90
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`Copy provided by USPTO from the PIRS Image Database on 09/30/2015
`0002
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`U.S. Patent
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`.Jan. 15,2002
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`Sheet 1 of 3
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`US 6,339,428 Bl
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`Memory
`20
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`- Compressed
`Texture Information
`22
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`r - - - -L - - - ,
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`Cache
`40
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`Texture
`Address
`Module
`30
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`Decompression
`Block
`50
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`lQ
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`Uncompressed
`Texture Data
`62
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`Filtering Block
`60
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`Frame Buffer
`90
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`Texel
`Decompression
`Blocks
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`Additional
`Color Values
`72
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`Texture
`Color
`64
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`Blending Block 70
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`Blended
`Color
`Pixel
`74
`Color Values .----....1-----~
`Source/Destination
`82
`Blending Block
`80
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`Figure 1.
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`Copy provided by USPTO from the PIRS Image Database on 09/30/2015
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`U.S. Patent
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`Jan.1S,2002
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`Sheet 2 of 3
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`US 6,339,428 Bl
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`100
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`Cache
`40
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`Memory
`20
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`Texture
`Address
`Module
`30
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`Cache
`40
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`Decompression
`Block
`50
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`Decompression
`Block
`160
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`Filtering Block
`60
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`64
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`Frame Buffer
`90
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`Texe
`Decompression
`Blocks
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`Additional
`Color Values
`72
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`Blending Block 70
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`Filtering Block
`180
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`174
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`Blended Color
`Values 184
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`Source/Destination
`Blending Block
`80
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`Pixel
`Color Values
`82
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`Figure 2.
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`Copy provided by USPTO from the PIRS Image Database on 09/3012015
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`US 6,339,428 B1
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`1
`MRTHOD AND APPARATUS FOR
`COMI•RESSED TEXTURR CACHING IN A
`VIDEO GRAPHICS SYSTEM
`
`FIELD OF THI2 INVENTION
`
`The invention relates generally to video graphic.~ process(cid:173)
`ing and more particularly to a method and appararus for
`compressed texrure caching in a video graphics system.
`
`2
`possible without additional memory bandwidth of the exter(cid:173)
`nal textlH"C memory being utilized. However, this solution
`s till suffers from the additional cost associated with a large
`cache struct urc.
`Therefore, a need exists for a method and apparatus that
`reduces memory bandwicith usage for texturing operations
`while limiting the size of any cache structures used to store
`texture data.
`
`BACKGROUND OF 11-IE INVENTION
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`10
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`BRIEF DESCRIPTION OF THB DRAWINGS
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`20
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`·- ····-,
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`FIG. ~ illustrates a block diagram of a video graphics
`texture mapping circuit in accordance with the present
`invention;
`FIG. 2 illustrates a block diagram of an alternate video
`graphics texture mapping circuit in accordance with the
`present invention;
`FIG. 3 illustrates a block dia_qram of a tcxll•ring pmcessor
`in accordance with the present invention; and
`FIG. 4 illustrates a flow diagram of a method for texturing
`di~"Play primitives in au:ordance with the present invention.
`
`DETAJLED DFSCRJIYHON OF A PREFERRED
`ilMBODIMENT OF TilE INVENTION
`
`Generally, the present invention provides a method and
`apparatus for reducing memory bandwidth usage in video
`graphit-s texturing operations. This is accomplished by stor(cid:173)
`ing texturing infunnation i n a memory structure in a corn(cid:173)
`pressed format. When texture information is needed for a
`texturing operation, a local cache is first examined to deter(cid:173)
`mine if the texrure information required for the texturing
`operation is present within the cache. If it is not, the texture
`information is retrieved from the memory in a compressed
`iormat and stored in the cache in the compressed format. The
`compressed texture i nformation is then retrieved from the
`cache each time it is required for a texturing operation and
`decompressed prior to usc in such texturing operations.
`Because the texture information is stored in the cache in
`a compressed formal, more texture information cao be stored
`in a cache of limited si<'.C, thus reducing the size require(cid:173)
`ments for the cache in a video graphics system. TI1is is
`accomplished while ensuring that memory bandwidth is
`minimi:.:cd by ~ loring the texturing information in the
`memory strucn.re as compressed texture information. Tbe
`compressed texture information requires les.~ memory band(cid:173)
`width to retrieve because less data must be retrieved from
`the memory for each texturing operation. Because the tex(cid:173)
`ture ioformalion is preferably compressed in a manner such
`that each individual texe l can be decompressed
`independently, multiple decompression operations for a
`single texturing operation can be performed in parallel. ·n1is
`ensures that the pcrformam.:e of the system is not compro(cid:173)
`mised by decompression operations performed on the tcx(cid:173)
`rure information prior to use.
`Texrurc maps stored in video graphics system for textur(cid:173)
`ing operations are typically referenced in UV space. As
`texturing operations apply textures to video graphics
`primitives, which arc preferably triangle primitives that arc
`commonly used in viico graphics systems, the appropriate
`position within the texture map that correspond<; to a par(cid:173)
`ticular pixel within the graphics primitive must be deter(cid:173)
`mined. This determination is based on a mapping between
`the pixel position in XY space, wbich is the reference space
`within wbich the primitive is rendered, to UV space, which
`is the reference frame for texture maps. When a texture is to
`be applied to a received graphia; primitive, the graphic~
`
`30
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`35
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`40
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`Computers are used iu many applications. As computing
`systems continue to evolve, the graphical display require(cid:173)
`ments of the systems become more demanding. "Ibis is
`especially true in applications where detailed three- 15
`dimensional graphical d isplays must be updated quickly.
`One example of such an application is a computer game
`where movement and modification o f background images
`may place great demands on the processing power of the
`computing system.
`In order to display some ~crecn images, detailed textures
`are stored in memory. These textures are digitized images
`drawn onto three-dimensional shapes to add visual detail.
`One example is a brick pattern that would be mapped onto
`a wall structure, and if the walls extending into the distance, 25
`the texture \vill be mapped in such a way as to show
`perspective.
`'Ibe use of detailed texrures can cons11mc a large amount
`of available memory bandwidth in a video graphics systems
`as the texrurcs may need to repeatedly be read from memory
`for use in texturing operations. As texture mapping opera(cid:173)
`tions consurnc more and more of the available memory
`bandwidth in video graphics processing circuits, overall
`performance of these video graphics circuits may be corn-
`promised. This is due to the fnct that other circuit blocks alsc•
`require acc<:Ss to tbe memory that stores the textures. If the
`texturing operations monopolize use of the memory, these
`other circuit block.~ may be unablo.; to prnperly perfonn their
`functions in a timely manner and, as a result, may degrade
`the performance of the video grdphic.'> system as a whole.
`One prior art solution that reduces memory bandwidth
`as.~ociated with reading texture data s tores portions of the
`textures in a cache included in the video graphics circuit.
`Recently used texture data that is still in the cache does not 45
`bave to be retrieved from memory each time it is reused.
`However, in order to be effective, the cache must he of a
`relatively large size. Large cacbcs consllllle a large amount
`of die area in integrated circuit solutions, and therefOre add
`to the cost of video graphics systems that utilize such large 50
`cacbc.~.
`Another prior art solution utilizes compression techniques
`to compress the texture data in the memory structure. When
`texture data is required from memory, it is deeomprcs.scd
`prior to use. However, in these systems data that is reused 55
`repeatedlY must be fetched and decompressed from memory
`each time it is used. Although memory band\vidth is reduced
`by the reduction in the amount of data that must be repeat(cid:173)
`edly retrieved from memory, the bandwidth required to
`retrieve the compressed data and decompress it is still 60
`substantial.
`Another hybrid prior art solution employs both compres(cid:173)
`sion and caching in a technique that stores compressed
`texture data in memory and dcc:omprcsses the texture data as
`it is retrieved for usc in texturing operalions. Aller the 65
`texture data ·is decompressed, it is stored in an on-chip cache
`such that repeated use of the same tcxn•re data Would be
`
`~'--------------------C~o-p_y_p_r_o_v~ld~e~d•b~y~u"s"P"THO~Ir~om~t~he-=P~IR~S~I~m-a_g_e~D~a~ta~b~a~s=e~o=n~0~9~~uoU.t2~0H1~5--------------------------------­
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`40
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`4
`two-third• contribution of th(; blue color ami be encodoo
`with the value "01". The other purple may be a two-thirds
`contribution of the red color and a one-third contribution of
`the blue color and be encoded with the value "10". In
`another embodiment, the available encodiug values may be
`used to encode the red color, the blue color, a purple color
`that is a half red and half blue, while the fourth encoding
`value may be used to encode a transparent tcxel.
`Although each two-bit encoding is dependent on the two
`reference. color values (with the exception of a transparent or
`other constant encoding), the two-bit eocodings arc not
`dependent on other two-bit encodings within the tcxel block.
`As such, each texel can be compressed or decompressed
`indepcudcut of other tcxcls within the block, Such texd
`independence allows for decompression of multiple texcls
`simultaneoiL~ly, which is beneficial when multiple texel
`values are combined to determine the final pixel color.
`In order to minimize the memory bandwidth required to
`fetch the compressed texture inforrnation 22 from the
`memory 20 for usage, the cache 40 is included in the video
`graphics texture mapping circwt 10. The texture informa tion
`stored in the cache 40 remains in the cornpr=d formal,
`thus enabling the cache 40 to ell'cctively store more texture
`information tban it could if the texture information was
`decompressed prior to storage in the cache 40. The system
`ilht&trated in FIG. 1 takes advantage of the capability of
`being able to decompress texture information on demand
`sucb that when particular texels are required for a texturing
`operation they can be fetched from the cache and decom(cid:173)
`press prior to usc. This reduces the required cache s i:.::e
`needed to maintain high performance levels in texturing
`operations.
`Because the cache 40 is of limited size, it preferably only
`stores a portion of the compressed texture information tbat
`is present in the memory 20. As such, a texture address
`module 30 is used to determine whether or not the texture
`data for a particular texturing operation is currently stored in
`the cache 40. Wheu the texture data is not stored in the cache
`40, th~ texture address module 30 copies the compressed
`texture information 22 from the memory 20 into the cache
`40. Once the required texture data for the texturing operation
`is pre.~ent in the c~che 40, the textur~ address module 30
`provide.~ control information, which c~n include addres.5 and
`control signa Is, to the cache 40 such that the cache 40
`provides the rcquiroo texture data 42 at its outputs.
`The decompres~ion block 50 receives the texture data 42
`from the c~che 40 ~nd decompresses the texture data 42 to
`produce uncompres.<;ed texture data 62. ·1be uncompres.~ed
`50 texture data 62 can then be used in the texturing operation.
`In many cases, the uncomprcs.-;ed texture data 62 includes a
`plurality of texels, and the filtering block 60 filters the
`uncompresscd texture data 62 to produce a resultant texture
`color 64. For example, if bilinear filtering is utili7.ed in the
`ss texture mapping circuit, the uncompressed texture data 62
`may include four diHcrent texel color values, where the
`filtering block 60 fillers these texel color values to produce
`the resultant texture color 64. It should be apparent to one of
`ordinary skill in the art that various filtering operations may
`60 be performed by the liltcring block 60 and that the number
`of texture colors included in tbe uncompressoo texture data
`62 can vary.
`Preferably, the decompression block 50 includes a plu(cid:173)
`rality of texel decomprc.-;.~ion blocks 52-58 such that a
`GS number of different decompression operations can be per(cid:173)
`formed in parallel. Assuming that the texture has been
`compre~sed in a manner sucb that compression and dccom-
`
`3
`primitive will includ(; texture coordinate data corresponding
`to the applicable texture. Preferably, tb(; texture coordinate
`data arc the UV coordinates corresponding to the pixels at
`the vertices of the video graphics primitive. For example, a
`triangle primitive will include the UV coordinate values s
`corresponding to the pixels at its vertices.
`Based on the known UV mappings at the vertex locations
`of the video graphics primitiv(;, the appropriate UV coordi(cid:173)
`nates (or any pixel \vithin the graphics primitive can be
`determined using interpolation. This then allows each pixel 10
`\vithin the video graphics primitive to be mapped into the
`texmre space at the appropriate UV coordinates.
`The point in the texture space detintd by the UV coor(cid:173)
`dinates dckrmined by the interpolation is then typically wscd
`to perform a weigbtt:d average ol' the color of the texcls, or l5
`individual texturt: componcuts, surrouudiug the particular
`point in UV space. The weighted average of the surrounding
`texd colors is then wsed to determiue the color l'or the
`particular pixel in the video graphics prin1itive. Various
`numbers of' texels may be included in the determination of 20
`the color for the particular pixel, and the weighted average
`performed using these texels may be system dependent. In
`one embodiment, bilinear filtering is used to determine the
`pixel color value by determining the weigbted average of the
`closest four tcxels to the point in UV space. However, other 25
`forms of filtering may use a much large number of tcxels. It
`should be apparent to one of ordinary skill in the art that
`various methods may be used to determine the color for a
`pixel based on stored texture infonnation that is mapped to
`the primitive that includes the pixel.
`FJG. 1 illustrates a block diagram of a video graphics
`tcxtuw mapping circuit 10 that may be used to contribute to
`the determination of the final color value for various pixels
`in a display frame. The video graphics texture mapping
`circuit 10 includes a memory 20, a cache 40, a texture
`address module 30, and a decompression block 50. 'lbe
`available bandwidth for accessing the memory 20 is often a
`performance-limiting factor in video graphic circuiL-;. As
`such, one of the objectives of tbe present inventiou is to help
`to minimize the memory bandwidth requiroo to perform
`texturing operations within the video graphics system. In
`order to facilitate this, the texture in formation stored in the
`memory 20 is stored in a compressed forrnat. The memory
`20 may be local system memory, or memory acces.~ible over
`au accelerated graphics for (AGP) bus. The compression
`algorithm utilized for compres.~ing the texture information
`prior to storage in the memory 20 is preferably one that
`compresses cacb of the tcxels within a texture independently
`of other tcxels in the texture.
`One such compression technique that can be util.i.'ted to
`individually compress texcls within the texture is the
`DlRECTX compres.<;ed texture format that has been devel(cid:173)
`oped by MICRosorrr. The DIREcrx compres.sed texture
`format divides texture maps into 4-by-1 ((;XCI blocks. For
`each texel block, two 16-bit color values are used as
`reference colors (or the texel block. Each of the texels within
`the 4-by-4 block is then represented by a two-bit encoding,
`where the two-bit encoding either selecL~ one o( the two 16
`bit colors, a combination of the two colors, or, in some
`ernbodimeuts, a transparent color for the texel.
`For example, if the first reference color value is a blue
`color, and the second reference color value is a r~d color, the
`four potential colors may be the r(;d color (encoded with the
`value "00"), tbc blue color (encoded with the value "11"),
`and two different shades of purple. 1bc first shade of purple
`may have a one-third contribution of the red color and· a
`
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`pression of the various tcxel color values is independent of
`other texel color values, the texel decompression blocks
`52-58 can decompress a plurality of texcl colors in parallel.
`T herefore, if t he fi ltering operation performed by the filter
`block 60 requires four tcxel colors, the decomp res.~ion block
`50 may includes four texel decompression blocks such that
`the four tcxel colors arc decompressed simult aneously and
`provided to the filter ing block 60 in par allel. In othe r
`embodiments, the texcl decompression blocks may be fast
`enough that they can perform two tcxel color decompres-
`sions within the time period required to perform a fillering
`operation. In such an embodiment, ii four texel colors arc
`required for a filtering operation, cwo texel decom pression
`blocks may sullice as each can perform two decompression
`operations w ithin the limited time allotted by each filtering 15
`operation.
`Once the texture color value 64 has been generated by the
`filtering block 60, it may be blended with additional color
`values 72 in the blending block 70. T he additional color
`values 72 may inclttdc interpolat<:d color values or constant 20
`color val\lcs that are blended w ith the texttlrc color lo
`produce the blended color 74. In ot her embodiments, the
`additional color value!". 72 may include other texture colors
`correspondi ng to other textures which also map to the
`particular pixel for which the color value is being deter- 25
`mined . Suc h an example is described in wore detail with
`re5pect to FIG. 2.
`Preferably, the blended color 74 is provided to a scurce/
`desti nation blending block 80 that is operably coupled to the
`frame buffer 90. ] be frame buffer 90 s tores pixel colors for 30
`a plurality of pixels, and preferably sto res a pixel color for
`each pixel of the display frame. T he source/destination
`blending block 80 blends the blended color 74 with a stored
`color 82 for a co rresponding pixel t hat is 5tored in a
`corresponding pixel location in the frame buffer. T he blend- 3s
`ing performed by the source/destination blending block 80
`produces a resultant pixel color that is then stored in the
`corresponding pixel location of the frame buffer. In other
`words, if the blended color 74 is to be appl ied to a pa rticular
`pixel, the source/destination blending block 80 will retrieve 40
`the current pixel color value 82 for that particular pixel from
`the frame buffer 90 and perlorm a blending operation
`between the blended color 74 and the fetched pixel color
`value 82. The resultant color value is then stored back into
`the frame buffer 90 at the appropriate location, overwriting 45
`the pr<:viously stored value.
`It should be noted that the functions performed by the
`blending block 70 and the source/destination blending block
`80 may be combined within a single blending unit. In
`additioo, the majority of the compon<:nts illustrated in FIG. so
`1 ace preferably included on a single integrated circuit that
`performs three-dimensional video graphics processing as
`w ell as two-dimen•ional proce.s<ing <uch a~ two(cid:173)
`dimensional scaling operations. Ia many cases the memory
`20 and the frame huftcr 90 may be located external to this 55
`in tegrated circ.:uit due to lbc large amount of die area
`required to implement such memor y structures. However, it
`s hou ld be apparent to one of ordinary skill in the art that, as
`processi ng technology continues to evolve, the in clusion of
`such memory structures in t he integrated circuit may 60
`become more economically feasible.
`FIG. 2 illust.rates an alternate embodiment of t.he inven(cid:173)
`tion in which a plurality of caches and a plurality of
`decompression block.c; are employed to enable multiple
`texrurcs to be decompressed and utmzcd simultaneously i n 65
`the system. The video graph ics t<:xture mapping circuit 100
`of I;IIG. 2 includes the memory 20, lbe textu re address
`
`6
`module 30, a plurality of caches 40 ancl l20, and a plurality
`of decompression blocks 50 and 160. Although only two
`caches arc illustrated in the clrawi ug, additional caches may
`he included to facilit ate handling of even more texture
`information in the system. T he video graphics texture map(cid:173)
`ping circuit 100 may be employed to allow for multiple
`textures to be mapped to a !>;ngle pixel such that the eventual
`color determined for the pixel is based on more than one
`texn1re. Note that the multiple caches included in this system
`may be unnecessary if a single cache that has enough read
`and write ports and sufficient s torage to contain multiple
`textures is used.
`As was the case w ith FIG. 1, the memory 20 stores
`compressed texture information that corresponds to at least
`one texture, and more preferably to a number of textures. A~
`stated earlier, the memory 20 m ay be local system memory
`or may be memory accessible over an accelerated graphics
`for (AUP) bus. 111e plurality of caches 40 and 120 arc
`operably coupled to the memory 20 and !".tore a portion of the
`compressed texmre information that is included in the
`memory 20. Preferably, e~ch of the cache5 40 ancl 120 stores
`different t\~Xturc data, but if one texture is used for m ultiple
`operations simultaneously, the texture may be stored in more
`than one of the plurality of caches.
`'!1tc texture address module determines w l1ether or not the
`textu re data corresponding to the present texturing operation
`is stored in one or more of the plurality of caches 40 and 120
`such that i t is available for usc in the texturing operation .
`Note that a number of different texturing operations may be
`occurring simultancou5l y in U1is system, and, in such cases,
`the texture address module 30 must determine whether all of
`the appropriate texturing information is included in the
`plttrality of caches 40 and 120. Note that the text ure address
`modu le 30 must also ensure that the texture data is stored in
`the caches 40 and 120 in a manner that allows it to be
`properly used in the current textur ing operation or opera(cid:173)
`tions. In othc r word s, if a particular pixel color is to be
`determined based on two different textures and both texture!".
`are stored in the cache 40, it tnay not be possible to combine
`the information from both textures in a single operation. In
`such an instance, the texture address modu le may be
`required to ensure that om: o f the two textures is stored in the
`cache 40 and the other is stored in the cache 120.
`When the texture address module determines that the
`texn•re dat a needed for the texn1ring operation or operations
`is not present or properly accessible ia the plural it yof caches
`40 and 120, the texture addres.~ module 30 copies the texture
`data in compressed format from the memory 20 to one or
`more of the plurality of caches 40 and 120. T he texture
`address module 30 then provides control information to the
`plurality of caches 40 and 120 such that the textu re data for
`the texturing operation is provided at the output~ of one or
`morP. o f thf'. phor~l ity M <c1r.he< 40 ~nd 1211
`A plura lity of decompression blocks 50 and 160 are
`coupled to the plurality of caches 40 and 120. 1be plurality
`of deco mpression blocks 50 ancl 1.60 decompress the texn1 rc
`data provided at. the outputs of the plurality of caches 40 and
`120 to produce uncompressed text ure data for the texn•ring
`operation. As is the case with the decompression block 50
`the decompression block 160 may include a plurality of
`texel decompression blocks 162-168 that permit multiple
`texcl6 to b\~ decompres.~ed individually and in parallel. Note
`that although each decompression block 50 and 160 is
`shown to i nclude four texel decompression blocks, the
`number of tcxcl decompression blocks ca n vary based on
`many factors. T he uncomprcssed texture data resulting from
`th<: decompression operations can then be used in the
`
`Copy provided by USPTO from the PIRS Image Databa se on 09130/2015
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`US 6,339,428 B1
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`texhJring operation within the circuit 100. It should be
`obvious to one of ordinary ~;kill in the art that if tllc
`decompression blocks arc able to operate at a higher rate of
`speed than the other texture mapping blocks, fewer de<.'Orn·
`pression blocks may be required as tbey can perform mul(cid:173)
`tiple texcl decompressions during the available time
`between texturing operations.
`Preferably, filtering blocks 60 and 180 are included in the
`system to filter the uncompres!iCd texture data provided by
`the clecompression block SO and 160. For example, if the
`filtering to be performed is a bilinear filtering operation,
`each of the filtering blocks 60 and 180 will receive four texel
`<.:olon; and lUter theliC colors to produce a resultant texture
`color 64 and 174, respectively.
`The blending block 180 combines each of the texture
`colors 64 and 174 with additional color values to produce a
`blended color 184. In the system illustrated iu FIG. 2, if one
`texture is decompressecl and filtered using the decompres(cid:173)
`sion block SO and the filtering block 60, and another texture
`is decompressed and filtered using decompression block 160
`and liltcring block 180, the resullant texture wlon; 64 and
`174 may be blended in the blending block 11!0 to produce a
`blended color value 184 that is a combination of the two
`textures. In other embodiment~. additiona I co tor values 1 82
`may be provided that arc based on constant color values or
`other interpolated color values [or blending with the texture
`colors 64 and 174. Thus, the blended color values 184 may
`be a single color value resulting from the blending of color
`values from multiple textures, or may be a number of color
`values resulting from the plurality of textures. Depending on
`the number of caches, dec;.:ompression blocks, and filtering
`blocks included in this system, the number of combinations
`or blending operations that may be performed by the blend(cid:173)
`ing block 180 can vary significantly.
`As was the ca~e with the circuit illustrated in FIG. 1, the
`source/destination blending block 80 receives the blended
`color values 184 and combines them with pixel color v~lues
`82 that arc fetched from the frame buffer 90. 'l11e resultant
`color values of the combination operations performed by the
`source/destination blending block 80 are then stored back
`into the frame buffer 90. The colors stored in the frame
`buffer 90 can then be fetched by display circuitry for
`rendering of the frame to a display.
`Preferably, the majority of the components illustrated in
`HG. 2, aside from the memory stmcturcs, arc included in a
`single integrated circuit that perfom1s three-12-dimensional
`video graphic,~ proces.<,ing. Such an integrated cir<..uit is also
`preferably capable of performing two-dimensional video
`graphics processing operations such as two-dimensional
`scaling operations.
`FIG. 3 illustrates a texturing processor 300 that may be
`used to perform the method illustrated in FIG. 4. The
`texturing processor 300 includes a processing module 302
`and memory 304. The processing module 302 may include
`a single processing entity or a plurality of processing enti(cid:173)
`ticli. Such a processing entity may be a microprocessor,
`m.icrocontroller, digital signal processor, state machine,
`logic cir<.-uitry, and/or any device that processe.s information
`based on operational ancVor programming instmctions. The 6o
`memory 304 may be a single memory device or a plurality
`of memory devices. Such a memory device may be a read
`only memory device, random acces..,; memory device, floppy
`disk, hard drive memory, and/or any device that stores
`digital infomtation. Note !bat when the processing module
`302 has one or more of its functions performed by a state
`machine and/or logic circuitry, the memory containing the
`
`8
`corresponding operational instructions is embeddecl within
`the state machine and/or logic circuitry.
`The memory 304 stores programming and/or operational
`instructions that, when executed by the processing module
`5 302, al low the processing module 302 to perform the method
`illustrated in FIG. 4. Note that the processor 300 may
`implement some of the functions of FIG. 4through software
`stored in the memory 304, whereas other portions of the
`method may be implemented using bardware, or circuitry
`10 included within the processor 300. TbUJi, a mix of hardware
`and software may be used to perform the method il\usrrated
`in FIG. 4. It should also be noted that although r.he method
`of FIG. 4 may be performed through a mix of hardware and
`sonware, this is merely one embodiment of a system that can
`IS perform the method.
`FIG. 4 illustrates a method for texturing display primi(cid:173)
`tives in a video graphics system. The method begins at step
`310 where a graphics primitive is received. The graphics
`primitive includes texture coordinate data <.:orrcsponding to
`20 a first texture. Preferably, the texture coordinate data indi(cid:173)
`cates a particular and texture coordinates corresponding to
`thc·vcrticcs of the graphics primitive. The texture coordinate
`data provide~; a means to map points or