UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`DECLARATION OF DR. WOODWARD YANG
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`Mail Stop “PATENT BOARD”
`Patent Trial and Appeal Board
`U.S. Patent & Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
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`VOLKSWAGEN GROUP OF AMERICA, INC.,
`Petitioner
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`v.
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`ADVANCED SILICON TECHNOLOGIES, LLC,
`Patent Owner
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`
`
`Case IPR2016-TBA
`Patent 6,339,428
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`Volkswagen 1003
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`0001
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`

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`TABLE OF CONTENTS
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`I. 
`Qualifications ............................................................................................. 2 
`My Understanding of Claim Construction .............................................. 8 
`II. 
`My Understanding of Obviousness .......................................................... 9 
`III. 
`Level of Ordinary Skill in the Art .......................................................... 11 
`IV. 
`Overview of the ’428 Patent .................................................................... 11 
`V. 
`Video Graphics Systems Discussed in the Background of the ’428
`VI. 
`Patent 14 
`VII. 
`Background of the Technologies Disclosed in the ’428 Patent ............ 15 
`A. 
`History of 3D Graphics Processing ........................................................... 15 
`B. 
`History of Compressed Texture Caching .................................................. 17 
`A. 
`Griffin ........................................................................................................ 21 
`B. 
`Tarolli ......................................................................................................... 22 
`C. 
`A Person of Ordinary Skill in the Relevant Art Would Have Been
`Motivated to Combine Griffin and Tarolli and Would Have Had a Reasonable
`Expectation of Success in Doing So ..................................................................... 23 
`X. 
`Grounds of Rejection. .............................................................................. 25 
`A. 
`Ground 1: Claims 1-4, 8, 9, 18-22, and 25-29 are obvious over Griffin. .. 25 
`1.  Claim 1 ....................................................................................................... 25 
`2.  Claim 2 ....................................................................................................... 39 
`3.  Claim 3 ....................................................................................................... 41 
`4.  Claim 4 ....................................................................................................... 42 
`5.  Claim 8 ....................................................................................................... 46 
`6.  Claim 9 ....................................................................................................... 48 
`7.  Claim 18 ..................................................................................................... 49 
`8.  Claim 19 ..................................................................................................... 57 
`9.  Claim 20 ..................................................................................................... 57 
`10.  Claim 21 ..................................................................................................... 59 
`11.  Claim 22 ..................................................................................................... 60 
`12.  Claim 25 ..................................................................................................... 61 
`13.  Claim 26 ..................................................................................................... 65 
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`0002
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`14.  Claim 27 ..................................................................................................... 65 
`15.  Claim 28 ..................................................................................................... 66 
`16.  Claim 29 ..................................................................................................... 66 
`B. 
`Ground 2: Claims 5, 6, 10-14, 16, 17, 23, 24, and 30 are obvious over
`Griffin in view of Tarolli. ..................................................................................... 66 
`1.  Claim 5 ....................................................................................................... 67 
`2.  Claim 6 ....................................................................................................... 69 
`3.  Claim 10 ..................................................................................................... 69 
`4.  Claim 11 ..................................................................................................... 78 
`5.  Claim 12 ..................................................................................................... 79 
`6.  Claim 13 ..................................................................................................... 80 
`7.  Claim 14 ..................................................................................................... 80 
`8.  Claim 16 ..................................................................................................... 82 
`9.  Claim 17 ..................................................................................................... 84 
`10.  Claim 23 ..................................................................................................... 84 
`11.  Claim 24 ..................................................................................................... 85 
`12.  Claim 30 ..................................................................................................... 85 
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`0003
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`U.S. Patent No. 6,339,428
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`I, Dr. Woodward Yang, declare as follows:
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`1.
`
`I have been retained on behalf of Volkswagen Group of America, Inc.
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`(“Volkswagen”) for the above-captioned Inter Partes Review proceeding. I under-
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`stand that this proceeding involves U.S. Patent No. 6,339,428 (“the ’428 patent”)
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`titled “Method and Apparatus for Compressed Texture Caching in a Video
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`Graphics System” by Mark Fowler, Paul Vella, and Michael Wright, and that the
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`’428 patent is currently assigned to Advanced Silicon Technologies LLC (“AST”).
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`2.
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`I have reviewed and am familiar with the specification of the ’428 pa-
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`tent filed on July 16, 1999. I understand that the ’428 patent has been provided as
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`VW 1001. I will cite to the specification using the following format: (’428 patent,
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`1:1-10). This example citation points to the ’428 patent specification at column 1,
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`lines 1-10.
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`3.
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`I have reviewed and am familiar with the file history of the ’428 pa-
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`tent. I understand that the file history has been provided as VW 1002.
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`4.
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`I have also reviewed and am familiar with the following prior art used
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`in the Petition for Inter Partes Review of the ’428 patent:
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`U.S. Patent No. 5,880,737 to Griffin et al., titled “Method and
`System for Accessing Texture Data in Environments with High
`Latency in a Graphics Rendering System” (“Griffin”). Griffin is-
`sued as a patent on March 9, 1999, more than four months prior to
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`
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`- 1 -
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`0004
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`

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`U.S. Patent No. 6,339,428
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`the filing date of the ’428 patent. I understand that Griffin has been
`provided as VW 1004.
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`U.S. Patent No. 5,822,452 to Tarolli et al., titled “System and
`Method for Narrow Channel Compression” (“Tarolli”). Tarolli is-
`sued as a patent on October 13, 1998, more than nine months prior
`to the filing date of the ’428 patent. I understand that Tarolli has
`been provided as VW 1005.
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`5.
`
`The ’428 patent describes methods and apparatuses that implement
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`“compressed texture caching” (’428 patent, 1:6-8) as a means for “reducing
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`memory bandwidth usage in video graphics texturing operations” (id., Abstract). I
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`am familiar with the technology described in the ’428 patent as of its July 16, 1999
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`filing date.
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`6.
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`I have been asked to provide my technical review, analysis, insights,
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`and opinions regarding the ’428 patent and the above-noted references that form
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`the basis for the grounds of rejection set forth in the Petition for Inter Partes Re-
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`view of the ’428 patent.
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`I.
`
`Qualifications
`7.
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`I have over 25 years of experience working with computer graphics—
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`specifically with memory systems and hardware for high performance image pro-
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`cessing applications. As detailed below, I have worked on many projects that are
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`highly relevant to the subject matter of the ’428 patent.
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`U.S. Patent No. 6,339,428
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`8.
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`I am presently the Gordon McKay Professor of Electrical Engineering
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`and Computer Science in the Paulson School of Engineering and Applied Science
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`at Harvard University. I have been teaching and pursuing various research endeav-
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`ors at Harvard University since 1990. I have taught classes related generally to the
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`design and analysis of microelectronic circuits and Very Large Scale Integration
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`(“VLSI”) systems: the process of creating integrated circuits by combining thou-
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`sands of transistors into a single chip. The microprocessors and graphics proces-
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`sors found in personal computers and smartphones are examples of VLSI devices.
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`9.
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`I have also taught graduate and undergraduate level courses in com-
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`puter architecture, computing hardware, digital logic design, mixed signal circuit
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`design, circuit theory, and engineering design. My research pursuits have been di-
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`rected to the development of advanced computing and memory systems for high
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`performance image processing and computer vision applications, data encryption,
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`error correcting codes, and integrated sensor and computing systems.
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`10.
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`In 2008, I was appointed as the Harvard Business School (“HBS”)
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`University Fellow and have taught courses at HBS as a Visiting Professor. In this
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`capacity, I have conducted research and taught business school courses on the
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`commercialization of new technologies, technological innovation, and industry ar-
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`chitecture.
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`0006
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`U.S. Patent No. 6,339,428
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`11. During my over 25 years of experience in the field of electrical engi-
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`neering and computer science, I have published many peer-reviewed papers in the
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`field and have been extensively involved in the development and commercializa-
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`tion of several important high performance computing and mobile device technol-
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`ogies. These technologies, which are now common in computing systems and mo-
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`bile devices, include high performance image processors, CMOS image sensors,
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`and pseudo-SRAM.
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`12. Over the course of my career, I have been a named inventor on at least
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`nine patents.
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`13.
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`I graduated with a Bachelor of Science degree in Electrical Engineer-
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`ing and Computer Science from the University of California, Berkeley in 1984.
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`During my undergraduate studies, I also pursued research in the university’s Elec-
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`tronic Research Laboratory, where I researched the measurement and analysis of
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`hot electron degradation in MOS (“metal oxide semiconductor”) transistors.
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`14.
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`I received a Master's of Science degree in Electrical Engineering and
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`Computer Science from the Massachusetts Institute of Technology in 1987. While
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`pursuing my Masters degree, I served as a research assistant in the Microsystems
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`Technology Laboratory, where I assisted in developing and characterizing low
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`pressure ammonia and oxygen annealing processes that improve the reliability of
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`scaled MOS transistors.
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`U.S. Patent No. 6,339,428
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`15.
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`I received my Ph.D. in Electrical Engineering and Computer Science
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`from the Massachusetts Institute of Technology in 1990. My doctoral thesis con-
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`cerned “The Architecture and Design of CCD Processors for Computer Vision.”
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`While pursuing my doctorate, I served as research assistant in the university’s Arti-
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`ficial Intelligence Laboratory, where I contributed to the development, design, and
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`implementation of analog VLSI hardware in computer vision systems. At the time,
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`since the computing demands for advanced real-time image processing of video
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`were beyond the capabilities of many supercomputers, this work attempted to use
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`more efficient and elegant analog computing techniques to reduce the computa-
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`tional demands on the digital computer.
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`16. From approximately 1990-2000, I taught and pursued advanced re-
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`search at Harvard in the general areas of high performance VLSI computing sys-
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`tems for processing and analyzing images and high performance computer archi-
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`tecture. With exponential growth of digital computing capabilities, my research
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`approach switched from analog to digital computing systems. An early important
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`milestone was a PC based real-time computer face recognition system in 1992 us-
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`ing only an Intel 80386 microprocessor and a high performance special purpose
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`image coprocessor that matched the computing performance of a supercomputer at
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`a fraction of the cost. Subsequent integration of similar coprocessor cores can be
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`found in the hardware video coder/decoders implemented in many advanced
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`U.S. Patent No. 6,339,428
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`graphic chips. Many of these techniques have direct relevance to the video
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`graphics texture mapping circuitry described in the ’428 patent.
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`17.
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`In addition, my research as part of an NSF funded project for High
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`Performance Computing Challenges involved the VLSI implementation of single
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`chip with a massively parallel array of 64 processors with 16Mb DRAM for com-
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`puter vision, machine learning, and graphics applications in 1997.
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`18.
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`I have also served as a consultant throughout my career. From 1991 to
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`1993, I advised on the research and development of advanced complementary-
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`metal-oxide-semiconductor (“CMOS”)/charge-coupled device (“CCD”) technolo-
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`gy and circuitry at the Istituto per la Ricerca Scientifica e Tecnologica (IRST), in
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`Trento, Italy. From 1993 to 1998, I served as a consultant for Hamamatsu Photon-
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`ics, K.K. in Hamamatsu City, Japan, where I helped develop smart image sensors
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`and CMOS/CCD analog charge-domain circuitry.
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`19. From 1995 to 2000, I worked as a consultant and Senior Fellow at
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`Hyundai Electronics Industries, in Ichon, Korea. At Hyundai, I developed and
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`commercialized high performance CMOS image sensor technology for embedded
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`image sensing and processing applications and researched advanced Dynamic
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`Random Access Memory (“DRAM”) design and merged memory logic (MML)
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`technology for advanced computer systems. From 1998 to 2001, I served as a
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`0009
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`U.S. Patent No. 6,339,428
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`member of the Science and Technology Board for Polaroid Corporation, where I
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`evaluated Polaroid’s research and technology developments.
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`20.
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`In 2000, I founded a company called Silicon7, Inc. Silicon7 was lo-
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`cated in Seongnam-si, Kyoungki-do, Korea, and developed application-specific
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`memory products for mobile communications and computing platforms. For ex-
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`ample, we developed 4-Mbit and 8-Mbit pseudo SRAMs which featured a 70-
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`nanosecond access time and ultra-low power consumption that were targeted for
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`mobile applications such as handsets and personal digital assistants. These ad-
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`vanced memory components and systems were optimized for the distinct require-
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`ments of mobile communication devices.
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`21. Over the course of my career, I have received various honors and fel-
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`lowships. While in school, I received the University of California Alumni Scholar-
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`ship (1980-1984), the National Science Foundation Fellowship (1984), the Hertz
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`Foundation Fellowship (1984-1990). I was admitted into the Phi Beta Kappa, Eta
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`Kappa Nu, and Tau Beta Pi honor societies in 1984. As a junior faculty member at
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`Harvard, I received both the National Science Foundation Young Investigator
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`Award and the Army Research Office Young Investigator Award in 1992. I have
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`also served as Institute of Electrical and Electronics Engineers (“IEEE”) Distin-
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`guished Lecturer in the areas of CMOS Image Sensors and High Performance
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`VLSI Systems.
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`U.S. Patent No. 6,339,428
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`22.
`
`I have also spoken and presented on a variety of topics throughout my
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`career. In January 2006, I was the Keynote Speaker at the Consumer Electronics
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`Show, where I gave a speech entitled “Disruptive Innovation.” In 1998, I spoke as
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`a distinguished lecturer at the Computing and Telecommunication Conference in
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`Chicago, Illinois, and at the U.S. Science and Technology Symposium in Korea
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`where I presented “The Dawn of Billion Transistor Chips.” I was also named a
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`Distinguished Lecturer in 1999 by the IEEE Solid-State Circuits Society and, in
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`this role, gave a lecture entitled “Merged Memory Logic” at Hanyang University in
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`Korea.
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`23. My Curriculum Vitae is attached as Appendix A, which contains fur-
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`ther details on my education, experience, publications, and other qualifications to
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`render an expert option. My work on this case is being billed at a rate of $700.00
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`per hour, with reimbursement for actual expenses. My compensation is not contin-
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`gent upon the outcome of this Inter Partes Review.
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`II. My Understanding of Claim Construction
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`24.
`
`I understand that, during an Inter Partes Review, claims are to be giv-
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`en their broadest reasonable construction in light of the specification as would be
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`read by a person having ordinary skill in the relevant art at the time the application
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`was filed (“PHOSITA”). I understand that claim terms are given their ordinary and
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`customary meaning as would be understood by a person of ordinary skill in the rel-
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`U.S. Patent No. 6,339,428
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`evant art in the context of the entire disclosure. However, a claim term will not re-
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`ceive its ordinary meaning if the patentee acted as his own lexicographer and clear-
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`ly set forth a definition of the claim term in the specification. In that case, the claim
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`term will receive the definition set forth in the patent.
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`III. My Understanding of Obviousness
`25.
`I understand that a patent claim is invalid if the claimed invention
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`would have been obvious to a person of ordinary skill in the field at the time the
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`application was filed. I understand that this means that even if all of the require-
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`ments of the claim cannot be found in a single prior art reference that would antici-
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`pate the claim, the claim can still be invalid.
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`26. As part of this inquiry, I have been asked to consider the level of ordi-
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`nary skill in the field that someone would have had at the time the claimed inven-
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`tion was made. In deciding the level of ordinary skill, I considered the following:
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` the levels of education and experience of persons working in the field;
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` the types of problems encountered in the field; and
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` the sophistication of the technology.
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`27. To obtain a patent, a claimed invention must have, as of the priority
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`date, been nonobvious in view of the prior art in the field. I understand that an in-
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`vention is obvious when the differences between the subject matter sought to be
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`patented and the prior art are such that the subject matter as a whole would have
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`U.S. Patent No. 6,339,428
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`been obvious at the time the invention was made to a person having ordinary skill
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`in the art.
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`28.
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`I understand that to prove that prior art or a combination of prior art
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`renders a patent obvious, it is necessary to (1) identify the particular references
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`that, singly or in combination, make the patent obvious; (2) specifically identify
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`which elements of the patent claim appear in each of the asserted references; and
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`(3) explain how the prior art references could have been combined in order to cre-
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`ate the inventions claimed in the asserted claim.
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`29.
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`I also understand that prior art references can be combined under sev-
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`eral different circumstances. For example, it is my understanding that one such cir-
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`cumstance is when a proposed combination of prior art references results in a sys-
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`tem that represents a predictable variation, which is achieved using prior art ele-
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`ments according to their established functions.
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`30.
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`I understand that certain objective indicia can be important evidence
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`regarding whether a patent is obvious or nonobvious. Such indicia include: com-
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`mercial success of products covered by the patent claims; a long-felt need for the
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`invention; failed attempts by others to make the invention; copying of the inven-
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`tion by others in the field; unexpected results achieved by the invention as com-
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`pared to the closest prior art; praise of the invention by the infringer or others in
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`the field; the taking of licenses under the patent by others; expressions of surprise
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`0013
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`U.S. Patent No. 6,339,428
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`by experts and those skilled in the art at the making of the invention; and the pa-
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`tentee proceeded contrary to the accepted wisdom of the prior art. At this point, I
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`am not aware of any secondary indicia of non-obviousness. I reserve the right to
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`supplement or amend my opinions to the extent any secondary indicia are brought
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`to my attention.
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`IV. Level of Ordinary Skill in the Art
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`31. Based on the disclosure of the ’428 patent, one of ordinary skill in the
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`art would have a B.S. degree in Electrical Engineering, Computer Science, or an
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`equivalent field as well as at least 2-3 years of academic or industry experience in
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`computer graphics, image processing hardware, or comparable industry experi-
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`ence.
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`V. Overview of the ’428 Patent
`32. The ’428 patent describes methods and apparatuses that implement
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`“compressed texture caching” (’428 patent, 1:6-8) as a means for “reducing
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`memory bandwidth usage in video graphics texturing operations” (id., Abstract).
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`FIG. 1 of the ’428 patent (reproduced below) illustrates an example video graphics
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`texture mapping circuit that reduces memory bandwidth usage by storing texture
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`information in a cache in a compressed format.
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`- 11 -
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`0014
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`UU.S. Patent
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`No. 6,3399,428
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`3
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`3. As shhown in FFIG. 1, viddeo graphiics texturee mapping circuit 100 in-
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`ng texture 0 for storincludes mmemory 20
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`informatioon “in a c
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`ompressedd format.”
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`(Id.,
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`
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`3:42-444.) The ’428 patent
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`describes
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`
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`that “[i]nn order too minimizee the memmory
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`bandwiddth requirred to fetcch the commpressed
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`memoryy 20 for ussage, the ccache 40 iss included
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`texture innformationn 22 fromm the
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`in the videeo graphiccs texture mmap-
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`
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`ping cirrcuit 10.” ((Id., 4:19-222.) Once aa texturingg operationn is initiateed, the requuired
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`0015
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`U.S. Patent No. 6,339,428
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`texture information is retrieved from memory 20 and stored in cache 40, also in a
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`compressed format. (Id., 4:34-36.) The ’428 patent explains that cache 40 “prefer-
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`ably only stores a portion of the compressed texture information that is present in
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`the memory 20,” and thus “texture address module 30 is used to determine whether
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`or not the texture data for a particular texturing operation is currently stored in the
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`cache 40.” (Id., 4:34-39.)
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`34. When the texture data is not stored in cache 40, “texture address mod-
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`ule 30 copies the compressed texture information 22 from the memory 20 into the
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`cache 40.” (Id., 4:39-42.) Once the required texture data for the texturing operation
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`is present in cache 40, texture address module 30 provides control information to
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`cache 40 such that cache 40 outputs the required texture data 42 to decompression
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`block 50. (Id., 4:42-46.) Subsequently, decompression block 50 decompresses the
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`texture data 42 to produce uncompressed texture data 62 that can then be used in
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`the texturing operation. (Id., 4:47-50.) The ’428 patent explains that the texturing
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`operation can include a filtering operation (filtering block 60) and two blending
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`operations (blending block 70 and source/destination block 80) before a final pixel
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`color value is produced and stored in frame buffer 90. (Id., 4:51-5:46.)
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`35. The ’428 patent does not purport to invent the idea of texture caching
`
`or even new video graphics texturing operations. Instead, as evidenced in the
`
`Background of the ’428 patent (discussed below), the ’428 patent merely purports
`
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`0016
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`U.S. Patent No. 6,339,428
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`to add “compressed texture caching” to known video graphics texture mapping cir-
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`cuitry. According to the ’428 patent, “compressed texture caching” provides vari-
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`ous benefits including “reducing memory bandwidth usage” (id., 2:26-28) and
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`“limiting the size of [] cache structures used to store texture data” (id., 2:7-8).
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`However, these same benefits motivated the use of compressed texture caching in
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`computer graphics systems well before the filing date of the ’428 patent.
`
`VI. Video Graphics Systems Discussed in the Background of the ’428 Patent
`36.
`In the Background of the ’428 patent, the inventors admit that three
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`distinct types of “prior art solution[s]” existed for “reduc[ing] memory bandwidth
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`associated with reading texture data” from memory. (’428 patent, 1:41-43.) The
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`first such prior art video graphics system included an off-chip memory and a large
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`on-chip cache, and did not use data compression. (See id., 1:41-50.) The second
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`prior art video graphics system identified by the inventors of the ’428 patent in-
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`cluded an off-chip memory that stored compressed image data, but did not include
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`an on-chip cache. (See id., 1:51-61.) The third prior art video graphics system iden-
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`tified by the inventors of the ’428 patent was a “hybrid prior art solution” that in-
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`cluded an off-chip memory that stored compressed image data as well as a large
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`on-chip cache that stored uncompressed image data. (See id., 1:62-2:4.)
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`37. Thus, a person of ordinary skill in the relevant art would have under-
`
`stood from reading the Background of the ’428 patent that the inventors of the ’428
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`U.S. Patent No. 6,339,428
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`patent believed that storing image data in an on-chip cache in a compressed format
`
`was the novel concept of the patent. But, as I explain in the follow sections, the
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`concept of storing image data in an on-chip cache in a compressed format existed
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`well before the filing date of the ’428 patent.
`
`VII. Background of the Technologies Disclosed in the ’428 Patent
`A. History of 3D Graphics Processing
`38. One of the primary objectives of 3D graphics processing is to provide
`
`photorealistic renderings of virtual images and animations. (See generally, Com-
`
`puter Graphics: Principles and Practice, VW 1017.)
`
`39. The basic principles and techniques for rendering high quality 3D
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`graphics were known well before the filing date of the ’428 patent, and were de-
`
`rived from the fundamental principles of physics. Specifically, the basic principles
`
`for rendering 3D graphics developed from an understanding of how light interacts
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`with materials as it is reflects off of various surfaces. One well-known software
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`package that performed high quality 3D rendering (and that existed prior to the
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`’428 patent) was RenderMan, which was used to create the animations seen in the
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`movie Toy Story. (See e.g., A Brief Introduction to RenderMan, VW 1014.)
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`40. However, conventional 3D graphics processing systems had a number
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`of limitations. For example, these systems involved computational simulations that
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`were extremely complex, required significant processing power, and involved large
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`amounts of data. (See generally, Computer Graphics: Principles and Practice, VW
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`U.S. Patent No. 6,339,428
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`1017.)
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`41. Throughout the 1990’s, significant effort was expended on develop-
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`ing: (i) specialized hardware to efficiently perform these computations, and (ii)
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`techniques for processing captured image data in order to produce video that still
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`appeared photorealistic.
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`42. One 3D graphics rendering technique that resulted from these efforts
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`was “texture mapping.” Texture mapping is 3D graphics rendering technique—
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`which was well-known years before the filing date of the ’428 patent—that in-
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`volves computing a projection of a 3D object onto a 2D image. (See id., Chapters 5
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`and 6.) Specifically, the position of the edges of the 3D object are first determined,
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`and then the texture of the 3D object is filled into the 2D image such that it can be
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`displayed. (See id., Chapter 16.) But, like other 3D graphics processing techniques
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`at the time, texture mapping involved the manipulation of large amounts of data.
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`Additionally, the bandwidth for supplying the required texture data was generally
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`limited by factors such as the speed at which the 3D graphics rendering can be car-
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`ried out.
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`43. A number of techniques for increasing the efficiency of video
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`graphics texture mapping circuits were soon developed. One such technique was
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`the implementation of texture compression. (See, e.g., Rendering from Compressed
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`U.S. Patent No. 6,339,428
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`Textures, VW 1015; see also Two Bit/Pixel Full Color Encoding, VW 1016.) Tex-
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`ture compression is a technique that could be used to reduce the amount of data
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`manipulation required for texture mapping. (Id.) Rather than directly using large
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`amounts of high resolution uncompressed texture data, only texture data at the ap-
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`propriate resolution (commonly referred to as a MIP (multum in parvo) map) was
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`used. (See, e.g., Pyramidal Parametrics, VW 1013.) This technique allowed texture
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`data to be compressed and approximated without a significant loss of photorealism.
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`(Id.)
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`B. History of Compressed Texture Caching
`44. The aforementioned texture compression technique was known well
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`before the filing data of the ’428 patent. In fact, several video graphics systems ex-
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`isted prior to July 16, 1999, the filing date of the ’428 patent, which stored image
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`data in an on-chip cache in a compressed format. For example:
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`45. Griffin: Disclosing multiple “improved methods and system for ac-
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`cessing texture data,” and in one such system, “[t]he memory control block fetches
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`the requested texture data, and if it is compressed, stores it in the compressed
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`cache 416 (990).” (Griffin, 30:4-7; emphasis added; see also claim 6.)
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`46. Tarolli: Disclosing that “[t]he invention compresses a texture im-
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`age, stores the compressed texture image, and quickly and efficiently decom-
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`presses the texture image when determining a value of a pixel.” (Tarolli, Abstract;
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`U.S. Patent No. 6,339,428
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`see also 6:62-66 (“the compression process reduces the texture memory 212 size
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`requirements.”); emphasis added.)
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`47. U.S. Patent No. 5,956,431 to Iourcha et al.: Disclosing that “[w]ithin
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`the image encoder system 220, the image is broken down into individual blocks
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`and processed before being forwarded to, e.g., the storage device 140, as com-
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`pressed or encoded image data.” (Iourcha, 5:51-54; emphasis added.) I under-
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`stand that Iourcha is provided as VW 1006.
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`48. U.S. Patent No. 6,111,585 to Choi: Disclosing that “when the texture
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`image is compressed using JPEG method, 8×8 pixels are compressed to one block
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`package to be stored in the refill line region 320 of the texture cache of FIG. 2.”
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`(Choi, 4:46-54; emphasis added.) I understand that Choi is provided as VW 1007.
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`49. U.S. Patent No. 6,259,460 to Gossett et al.: Disclosing that “[t]he
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`textures originate from the SDRAM 50, and are loaded along the 256-bit bus 137
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`into the format unit 136, which expands or compresses the formats depending
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`upon in what format the texture was stored. Then, a portion of that texture image
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`is loaded into the texture cache 134.” (Gossett, 11:23-27; emphasis added.) I un-
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`derstand that Gossett is provided as VW 1008.
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`50. U.S. Patent No. 6,236,405 to Schilling et al.: Disclosing “a hardware
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`architecture for the processing of compressed textures is presented, which inte-
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`grates texture mapping units together with a small texture cache on a chip. By
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`U.S. Patent No. 6,339,428
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`means of this texture compression, the off-chip bandwidth for updating the on-
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`chip cache is reduced, so that standard off-the-shelf DRAM devices can be used.”
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`(Schilling, 4:57-62; emphasis added.) I understand that Schilling is provided as
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`VW 1009.
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`51. UK Patent Application No. GB2343599 to Pearce: Disclosing that
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`“[t]he compressed texture is retrieved from memory by the memory controller 24
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`and held in a texture cache 30 … The output from the texture cache 30 is applied
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`to a decompression unit 32, which decompresses or decodes the texture values to
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`provide decompressed texels.” (Pearce, 13:29-14:8;