IPR2016-00894
`U.S. Patent No. 8,933,945 B2
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`________________
`
`VOLKSWAGEN GROUP OF AMERICA, INC.,
`Petitioner,
`
`v.
`
`ADVANCED SILICON TECHNOLOGIES LLC
`Patent Owner
`________________
`
`Case IPR2016-00894
`U.S. Patent No. 8,933,945 B2
`________________
`
`PATENT OWNER’S PRELIMINARY RESPONSE
`PURSUANT TO 37 C.F.R. § 42.107(a)
`
`

`
`I.
`II.
`
`III.
`
`IV.
`
`IPR2016-00894
`U.S. Patent No. 8,933,945 B2
`
`TABLE OF CONTENTS
`
`PAGE
`Introduction & Summary of Arguments..........................................................1
`The ’945 Patent................................................................................................2
`A.
`The ’945 Patent Discloses Improved Graphics Pipelines .....................2
`B.
`The Challenged Claims of the ’945 Patent ...........................................7
`The Primary Asserted References ...................................................................9
`A.
`Narayanaswami .....................................................................................9
`B.
`Gove ....................................................................................................12
`The Correct Claim Construction of Material Disputed Terms......................15
`A.
`The Controlling Claim Construction Standard ...................................15
`B.
`The Material Claim Construction Issue Facing The Board ................17
`1.
`“memory controller” .................................................................17
`a.
`The Correct Construction Of “memory controller”..........17
`b. Volkswagen’s Petition Depends On An Incorrect And
`Unsupported Construction Of “memory controller”.........18
`i. Volkswagen neither alleges nor proves that its
`construction is the ordinary meaning of the claimed
`“memory controller”...............................................19
`
`ii. Volkswagen neither alleges nor proves that its
`construction is some purported special definition of
`the claimed “memory controller” ...........................20
`
`2.
`
`“scan converter”........................................................................22
`a.
`“scan converter” Should Be Construed To Have Its
`Ordinary Meaning .............................................................24
`b. Volkswagen Failed To Argue Or Prove Any Clear And
`Unambiguous Special Definition Or Disavowal...............27
`The Remaining Claim Construction Dispute Is Not Material
`And Should Not Be Decided By The Board .......................................29
`
`C.
`
`ii
`
`

`
`V.
`
`Volkswagen’s Petition Fails With Respect To All Challenged Claims........30
`A.
`All Challenged Claims: Gove Cannot Cure Narayanaswami’s
`Admitted Deficiencies Regarding The “Memory Controller”
`And “Same Chip” Limitations ............................................................30
`1.
`Under the correct construction, Gove indisputably does
`not disclose the missing claimed “memory controller”............31
`Volkswagen failed to identify evidence sufficient to meet
`its burden of proving that it would have been obvious to
`combine Gove with Narayanaswami to provide the
`missing “memory controller” and “same chip”........................34
`a. Volkswagen identifies no explanation for how a person of
`ordinary skill would have combined Narayanaswami and
`Gove ..................................................................................37
`b. Volkswagen fails to establish a reasonable likelihood of
`proving why a person of ordinary skill would have
`combined Narayanaswami and Gove................................39
`All Challenged Claims: A Pipeline “operative to process data in
`a dedicated tile”...................................................................................42
`VI. Volkswagen’s Petition Also Fails With Respect To Various
`Limitations Specific To Certain Challenged Dependent Claims ..................48
`A.
`Dependent Claims 2 And 3: “a two dimensional partitioning of
`memory”..............................................................................................48
`1.
`Narayanaswami teaches away from “two dimensional
`partitioning of memory” ...........................................................49
`Combining “two dimensional partitioning of memory”
`with Narayanaswami would result in an inoperable
`system........................................................................................51
`Dependent Claim 5: “scan converter … operative to determine
`the portion of the pixel data to be processed by the back end
`circuitry”..............................................................................................52
`VII. Conclusion .....................................................................................................55
`
`2.
`
`2.
`
`IPR2016-00894
`U.S. Patent No. 8,933,945 B2
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`iii
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`B.
`
`B.
`
`

`
`IPR2016-00894
`U.S. Patent No. 8,933,945 B2
`
`TABLE OF AUTHORITIES
`
`Page(s)
`
`Cases
`ACTV, Inc. v. Walt Disney Co.,
`346 F.3d 1082 (Fed. Cir. 2003) ..........................................................................19
`
`Ariosa Diagnostics v. Verinata Health, Inc., et al.,
`IPR2013-00276, Paper 43 (PTAB Oct. 23, 2014)..............................................36
`
`Aventis Pharma S.A. v. Hospira, Inc.,
`675 F.3d 1324 (Fed. Cir. 2012) ....................................................................17, 24
`
`In re Beasley,
`117 Fed. Appx. 739 (Fed. Cir. 2004)..................................................................39
`
`Becton, Dickinson and Co. v. One StockDuq Holdings, LLC,
`IPR2013-00235, Paper 30 (PTAB Sept. 25, 2014)......................................passim
`
`Callcopy v. Verint Americas, et al.,
`IPR2013-00486, Paper 11 (PTAB Feb. 5, 2014)................................................35
`
`In re Chaganti,
`554 Fed. Appx. 917 (Fed. Cir. 2014)..................................................................36
`
`Ericcson, Inc. v. Intellectual Ventures I LLC,
`IPR2014-00921, Paper 8 (PTAB Dec. 16, 2014) .........................................16, 24
`
`Galderma Labs., L.P. v. Tolmar, Inc.,
`737 F.3d 731 (Fed. Cir. 2013) ............................................................................40
`
`In re Gordon,
`733 F.2d 900 (Fed. Cir. 1984) ......................................................................51, 52
`
`In re Gurley,
`27 F.3d 551 (Fed. Cir. 1994) ........................................................................51, 52
`
`Hill-Rom Services, Inc. v. Stryker Corporation,
`755 F.3d 1367 (Fed. Cir. 2014) ..............................................................16, 17, 24
`
`iv
`
`

`
`IPR2016-00894
`U.S. Patent No. 8,933,945 B2
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`Hockerson-Halberstadt, Inc. v. Converse Inc.,
`183 F.3d 1369 (Fed. Cir. 1999) ..........................................................................19
`
`Intellectual Ventures Mgmt, LLC, v. Xilinx, Inc.,
`IPR2012-00019, Paper 33 (PTAB February 10, 2014) ......................................16
`
`In re Karn,
`441 F.3d 997 (Fed. Cir. 2006) ............................................................................36
`
`KSR Int’l Co. v. Teleflex Inc.,
`550 U.S. 398 (2007)......................................................................................35, 36
`
`McGinley v. Franklin Sports Inc.,
`262 F.3d 1339 (Fed. Cir. 2001) ....................................................................51, 52
`
`Phillips v. AWH Corp.,
`415 F.3d 1303 (Fed. Cir. 2005) (en banc) ..........................................................16
`
`In re Ratti,
`270 F.2d 810 (CCPA 1959)..........................................................................51, 52
`
`Symantec Corp. v. RPost Communications Ltd.,
`IPR2014-00355, Paper 12 (PTAB Jul. 15, 2014)...............................................35
`
`Thorner v. Sony Computer Entm’t Am. LLC,
`669 F.3d 1362 (Fed. Cir. 2012) ..........................................................................28
`
`Universal Remote Control, Inc. v. Universal Electronics, Inc.,
`IPR2013-00127, Paper 32 (PTAB June 30, 2014) .............................................16
`
`Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc.,
`200 F.3d 795 (Fed. Cir. 1999) ............................................................................17
`
`Wellman, Inc. v. Eastman Chem. Co.,
`642 F.3d 1355 (Fed. Cir. 2011) ..........................................................................17
`
`Wowza Media Sys., LLC v. Adobe Systems Inc.,
`IPR2013-00054, No. 12 (PTAB Apr. 8, 2013)...................................................16
`
`Other Authorities
`
`37 C.F.R. § 42.107 .....................................................................................................1
`
`v
`
`

`
`77 Fed. Reg. 48,756, 48,766 (Aug. 14, 2012) .........................................................16
`
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`U.S. Patent No. 8,933,945 B2
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`

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`IPR2016-00894
`U.S. Patent No. 8,933,945 B2
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`TABLE OF EXHIBITS
`
`Exhibit
`2001
`
`Description
`Declaration of John C. Hart, Ph.D. In Support Of Patent Owner
`Advanced Silicon Technologies LLC’s Preliminary Response
`
`vii
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`

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`Case IPR2016-00894
`U.S. Patent No. 8,933,945 B2
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`I.
`
`Introduction & Summary of Arguments
`
`Patent Owner Advanced Silicon Technologies LLC (“AST”) submits this
`
`response under 37 C.F.R. § 42.107 to the Petition filed by Volkswagen Group Of
`
`America, Inc. (“Volkswagen” or “Petitioner”). For at least the following reasons,
`
`Volkswagen’s Petition fails to establish the required likelihood that it will prove
`
`that the challenged claims of AST’s U.S. Patent No. 8,933,945 (the “’945 Patent”)
`
`are unpatentable.
`
`All Challenged Claims:
`
`Under the correct claim constructions identified by AST, Volkswagen’s
`
`Petition fails to establish the required likelihood of success with respect to each of
`
`the following limitations:
`
` “memory controller”;
`
` “on a same chip”; and
`
` “one of the at least two graphics pipelines operative to process data in a
`
`dedicated tile.”
`
`Because each of these limitations is found in each of the challenged claims,
`
`each of Volkswagen’s failures with respect to these limitations provides a separate
`
`and independent reason for denying the Petition in its entirety.
`
`1
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`

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`U.S. Patent No. 8,933,945 B2
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`Dependent Claims:
`
`Under the proper claim construction, Volkswagen’s Petition also fails with
`
`respect to numerous limitations that are specific to certain challenged claims,
`
`including the following:
`
` “a two dimensional partitioning of memory” (dependent claims 2 and 3);
`
`and
`
` “scan converter … operative to determine the portion of the pixel data to
`
`be processed by the back end circuitry” (dependent claim 5).
`
`Each of these missing limitations provides an additional independent reason
`
`for denying the Petition with respect to the corresponding dependent claims.
`
`II.
`
`The ’945 Patent
`
`A.
`
`The ’945 Patent Discloses Improved Graphics Pipelines
`
`The ‘945 Patent is entitled “Dividing Work Among Multiple Graphics
`
`Pipelines Using a Super-Tiling Technique” and describes a “graphics processing
`
`circuit” consisting of multiple graphics pipelines on the same chip.
`
`When multiple graphics pipelines operate in parallel, an important goal for
`
`efficient graphics processing is “load balancing,” which means all of the graphics
`
`2
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`

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`U.S. Patent No. 8,933,945 B2
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`pipelines remain busy and none lay idle, such that the graphics processing unit can
`
`produce an image as quickly as possible. (See Hart Decl.1 at ¶ 16.)
`
`The ‘945 Patent illustrates such parallel graphics pipelines in Figure 2,
`
`which has been reproduced below, and annotated using a red rectangle to identify
`
`one of the plurality graphics pipelines:
`
`1 AST is providing the Declaration of John C. Hart, Ph.D. In Support Of Patent
`
`Owner Advanced Silicon Technologies LLC’s Preliminary Response as Exhibit
`
`2001.
`
`3
`
`

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`As depicted above, a graphics pipeline may contain front-end circuitry. Such
`
`front-end circuitry “generates the pixel data 36 by performing, for example,
`
`clipping, lighting, spatial transformations, matrix operations and rasterizing
`
`operations on the primitive data.” (’945 Patent2 at 4:39-42.) For example, the
`
`front end circuitry would convert the vertices of a triangle from their 3-D XYZ
`
`positions on the sphere to their corresponding 2-D XY positions on the display
`
`screen, as shown below. The “rasterizing operations” include computing vertex
`
`values useful for the next scan converter stage. (See Hart Decl. at ¶ 18.)
`
`Z
`
`XYZ
`
`XYZ
`
`XYZ
`
`Y
`
`X
`
`XY
`
`XY
`
`X
`
`Y
`
`XY
`
`The graphics pipeline may also include a scan converter. “The scan
`
`converter 37 of the first graphics pipeline 101 receives the pixel data 36 and
`
`sequentially provides the position (e.g. x, y) coordinates 60 in screen space of the
`
`pixels to be processed by the back end circuitry 39[.]” (’945 Patent at 4:45-48.)
`
`For example, as shown below, a scan converter accepts a triangle described by
`
`2 Volkswagen previously provided the ’945 Patent as Exhibit 1001.
`
`4
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`

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`three vertices and produces a collection of pixels designed to fill the triangle. (See
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`Hart Decl. at ¶ 19.)
`
`XY
`
`XY
`
`Y
`
`XY
`
`X
`The graphics pipeline may also include back-end circuitry. “Back end
`
`circuitry 39 may include, for example, pixel shaders, blending circuits, z-buffers or
`
`any other circuitry for performing pixel appearance attribute operations (e.g. color,
`
`texture blending, z-buffering) on those pixels located, for example, in tiles…”
`
`(’945 Patent at 4:66-5:3.) As illustrated below, the back end circuitry determines
`
`the colors of the pixels produced by the scan converter. (See Hart Decl. at ¶ 20.)
`
`In order to provide better load balancing of the available graphics pipelines,
`
`5
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`U.S. Patent No. 8,933,945 B2
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`the ‘945 Patent divides the screen up into tiles (below left), such that each tile can
`
`be assigned to one graphics pipeline for graphics processing. For example, as
`
`illustrated in below right, tiles shaded in red are assigned to one graphics pipeline
`
`while tiles shaded in blue are assigned to the other. (See Hart Decl. at ¶ 21.)
`
`As illustrated below, the graphics pipelines are in communication with a
`
`memory controller, which is operative to transfer pixel data between each of the
`
`pipelines and a shared memory. For example, as depicted below, memory
`
`controller 46 accepts pixels 43 and 44 generated by back end circuitry A 39 and B
`
`42 and writes pixels from both sources into the same graphics memory. This
`
`memory controller 46 may also manage the transfer of pixel data 49 and 50 from
`
`the shared graphics memory to the display 51 and back to the pipelines. (Hart
`
`Decl. at ¶ 23.)
`
`6
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`U.S. Patent No. 8,933,945 B2
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`B.
`
`The Challenged Claims of the ’945 Patent
`
`Volkswagen challenges independent claim 1, its dependent claims 2-11, and
`
`independent claim 21. As illustrated by exemplary claim 1 reproduced in full
`
`below, each challenged claim describes a graphics processing circuit having at
`
`least two graphics pipelines, at least one of which can “process data in a dedicated
`
`tile.” The claims additionally require a “memory controller” that is operative “to
`
`transfer pixel data between” the first pipeline, the second pipeline, and a memory
`
`shared by the two. The claims further require that the pipelines and the memory
`
`controller be on the “same chip.”
`
`1.
`
`A graphics processing circuit, comprising:
`
`7
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`least two graphics pipelines on the same chip
`at
`operative to process data in a corresponding set of tiles of a
`repeating tile pattern corresponding to screen locations, a
`respective one of
`the at
`least
`two graphics pipelines
`operative to process data in a dedicated tile; and
`a memory controller on the chip in communication
`with the at least two graphics pipelines, operative to transfer
`pixel data between each of a first pipeline and a second
`pipeline and a memory shared among the at least two graphics
`pipelines;
`wherein the repeating tile pattern includes a horizontally
`and vertically repeating pattern of square regions.
`
`(’945 Patent at claim 1 (emphasis added); see also claims 2-1, 21.)
`
`Also relevant to this Preliminary Response are the additional limitations of
`
`dependent claims 2 and 5. Challenged claim 2 depends from claim 1 and adds the
`
`requirement of a partitioning of memory:
`
`The graphics processing circuit of claim 1, wherein
`2.
`the square regions comprise a two dimensional partitioning of
`memory.
`
`(’945 Patent at claim 2.)
`
`Claim 5 depends from claim 4 (which depends from claim 1) and adds the
`
`requirement of each pipeline including a “scan converter” that can determine
`
`which portion of pixel data will be processed by a pipeline’s back end circuitry:
`
`8
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`

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`U.S. Patent No. 8,933,945 B2
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`The graphics pipeline processing circuit of claim 4,
`5.
`wherein each of the at least two graphics pipelines further
`includes a scan converter, coupled to the back end circuitry,
`operative to determine the portion of the pixel data to be
`processed by the back end circuitry.
`
`(’945 Patent at claim 5; see also claim 4.)
`
`III. The Primary Asserted References
`
`Volkswagen’s Petition asserts the following Grounds:
`
`Ground
`
`References
`
`Basis
`
`Challenged Claims
`
`I
`
`II
`
`III
`
`Narayanaswami and Gove
`
`§ 103(a)
`
`1, 9, 10, and 21
`
`§ 103(a)
`
`2-4 and 6-7
`
`Narayanaswami, Gove, and
`Foley
`Narayanaswami, Gove,
`Foley, and Kelleher
`Each of these Grounds relies on the combination of two primary references:
`
`§ 103(a)
`
`5, 8, and 11
`
`Narayanaswami and Gove.
`
`Narayanaswami
`A.
`Narayanaswami3 is directed to a graphics processing circuit and in
`
`particular, a method and apparatus for managing a graphical workload across
`
`multiple processors. Narayanaswami is designed to provide a “computer graphics
`
`systems” capable of rendering multiple objects into a frame buffer with the
`
`3 Volkswagen previously provided the Narayanaswami reference as Exhibit 1008.
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`9
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`U.S. Patent No. 8,933,945 B2
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`purpose of displaying those objects as quickly as possible. (Narayanaswami at
`
`1:15-17.) Narayanaswami was purportedly designed to respond to a rendering
`
`process that had become “more complex and computationally intensive as users
`
`demand more detailed results using more objects rendered more quickly, including
`
`providing realtime motion, while using more computationally intensive processing
`
`techniques such as color, texture, lighting, transparency and other rendering
`
`techniques.” (Id. at 1:17-24.)
`
`Narayanaswami describes graphics adapter processors 220, depicted in Fig.
`
`1 below. Volkswagen asserts that each of these processors is one of the claimed
`
`“graphics pipelines.” (Pet. at 33.)
`
`10
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`Narayanaswami describes (and illustrates in Fig. 6 below) the preferred
`
`method steps to be performed by each processor: “FIG. 6 is a flowchart illustrating
`
`a preferred method for each processor to handle the graphics workload while
`
`determining ownership of pixels or regions. This process may be executed
`
`concurrently and in parallel by all processors.” (Narayanaswami at 6:66 – 7:3.)
`
`11
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`As depicted in Figure 6 and the accompanying description, each
`
`Narayanaswami processor processes all pixels, whether they are in a particular
`
`region or not. (Narayanaswami at 7:21-28.) To illustrate, step 610 requires each
`
`processor to scan convert the subobject. Narayanaswami describes the processor
`
`as completing this step before determining which pixels are “owned by the
`
`processor,” resulting in the processor scan converting and processing all of the
`
`pixels, not just those in a particular region:
`
`In step 615, the subobject is then scan converted into
`pixels, In step 620, each pixel is checked to see if it is owned by
`the processor by comparing the identifier of the processor with
`the identifier stored in the pixel ownership buffer or the region
`ownership list for that pixel.
`If yes in step 620, indicating that the processor owns the
`pixel, then the processer processes the pixel.
`
`(Id. at 7:21-28.)
`
`Gove
`B.
`Gove4 teaches a system to handle the processing of images and graphics.
`
`Gove’s focus is on improved imaging systems. (See e.g. Gove, col. 26:19-25
`
`(“One of the reasons why so much imaging capability is available under the system
`
`shown is that the single chip contains several processors working in parallel
`
`4 Volkswagen previously provided the Gove reference as Exhibit 1009.
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`together with several memories, all accessible under a crossbar switch which
`
`allows for substantially instantaneous rearrangement of the system. This gives a
`
`degree of power and flexibility not heretofore known.”).) At their core, imaging
`
`systems “obtain visual images” and process them. Gove discloses that the image
`
`inputs“[c]an be, for example, a video camera…” (Id., col. 5:22-23.)
`
`Gove’s patent embodiments would have been used in applications such as
`
`medical image processing. Gove describes operations in its “Image Processing”
`
`section such as the “removal of extraneous specks from an image” or “recognizing
`
`… a circle” and that the circle in combination with “other shapes form a human
`
`image.” (Gove, col. 7:50-64.) Those types of functions are meant to enhance the
`
`quality of the images, which decreases image turnover time. Gove Figure 11 lists
`
`the various operations or algorithms which would be typical for its imaging
`
`processing system. (Id. at col. 12:17-19; see also Fig. 11, Hart Decl. at ¶ 28.)
`
`Gove teaches that “[a] typical type of operation would be optical character
`
`recognition, target recognition or movement recognition. In each of these
`
`situations, the associated image processing would be controlled by the kind of
`
`operations to be performed.” (Gove at 12:19-24.) Gove also describes how the
`
`invention can be used for various methods of image enhancement. (See generally,
`
`id. at col. 12:33-59.) These types of operations place a premium on image quality
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`which would be contrary to maximizing graphics turnover and display rates. (Hart
`
`Decl. at ¶ 29.)
`
`Volkswagen relies heavily on Gove’s disclosure of a “transfer processor 11,”
`
`depicted in Gove’s Figure 1 reproduced below.
`
`Gove describes the “transfer processor 11” as responsible for moving data
`
`back and forth between an internal memory and an external memory:
`
`Transfer processer 11 is the interface between system
`memory 10 and the external world.
`In particular,
`it
`is
`responsible for all accesses to external memory 15.
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`14
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`Transfer processer 11, shown in in detail in FIG. 57,
`mainly performs block transfers between one area of memory
`and another. The “source” and “destination” memory may be on
`or off-chip and data transfer is via bus 5700 and FIFO buffer
`memory 5701.
`
`(Gove at 54:64 – 55:5.)
`
`Gove further describes that these data transfers between internal and external
`
`memory can occur at the instruction of various processors:
`
`Transfer processor 11 shown in FIGS. 1 and 2 and FIG 57
`transfers data between external memory and the various internal
`memory elements. Transfer processor 11 is designed to operate
`from packet requests such that any of the parallel processors or
`the master processor can ask transfer processor 11 to provide
`data for any particular pixel or a group of pixels or data, and the
`transfer processor will transfer the necessary data to or from
`external and internal memory without
`further processor
`intervention instructions. This then allows transfer processor 11
`to work autonomously and to process data in and out of the
`system without monitoring by any of the processors.
`
`(Gove at 11:36-45.)
`
`IV. The Correct Claim Construction of Material Disputed Terms
`
`The Controlling Claim Construction Standard
`A.
`The broadest reasonable interpretation standard applies in an inter partes
`
`review of a patent that, like the ’945 patent, will not expire prior to the Final
`
`15
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`Written Decision. 37 C.F.R. §100(b); Office Patent Trial Practice Guide, 77 Fed.
`
`Reg. 48,756, 48,766 (Aug. 14, 2012). Applying the broadest reasonable
`
`interpretation, claim terms are given their ordinary and customary meaning, as
`
`would be understood by a person of ordinary skill in the art at the time of the
`
`invention, in light of the language of the claims, the specification, and the
`
`prosecution history of the record. E.g., Wowza Media Sys., LLC v. Adobe Systems
`
`Inc., IPR2013-00054, No. 12 at 5 (PTAB Apr. 8, 2013); Intellectual Ventures
`
`Mgmt, LLC, v. Xilinx, Inc., IPR2012-00019, Paper 33 at 9 (PTAB February 10,
`
`2014); see also Phillips v. AWH Corp., 415 F.3d 1303, 1313-1317 (Fed. Cir. 2005)
`
`(en banc); Hill-Rom Services, Inc. v. Stryker Corporation, 755 F.3d 1367, 1371
`
`(Fed. Cir. 2014).
`
`Under this test, “[t]here is a “heavy presumption’ that a claim term carries its
`
`ordinary and customary meaning.” See Intellectual Ventures, IPR2012-00019,
`
`Paper 33 at 9; Wowza, IPR2013-00054, No. 12 at 6; Universal Remote Control,
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`Inc. v. Universal Electronics, Inc., IPR2013-00127, Paper 32 at 6 (PTAB June 30,
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`2014). This heavy presumption is overcome in specific and limited circumstances:
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`a claim term may be construed contrary to its ordinary meaning only where there is
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`clear and unambiguous evidence that the patentee, as lexicographer, provided a
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`special definition for the claim term, or the patentee otherwise disavowed the full
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`scope of the claim term either in the specification or during prosecution. Ericcson,
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`Inc. v. Intellectual Ventures I LLC, IPR2014-00921, Paper 8, at 8 (PTAB Dec. 16,
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`2014); Becton, Dickinson and Co. v. One StockDuq Holdings, LLC, IPR2013-
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`00235, Paper 30 at 6 (PTAB Sept. 25, 2014); see also Aventis Pharma S.A. v.
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`Hospira, Inc., 675 F.3d 1324, 1330 (Fed. Cir. 2012); Hill-Rom, 755 F.3d at 1371.
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`B.
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`The Material Claim Construction Issue Facing The Board
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`The Board should only construe terms to the extent such construction is
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`necessary to resolve a controversy material to the Petition. See, e.g., Wellman, Inc.
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`v. Eastman Chem. Co., 642 F.3d 1355, 1361 (Fed. Cir. 2011); Vivid Techs., Inc. v.
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`Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999). Based on the Petition
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`and this Response, the only material claim construction issues currently facing the
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`Board concerns the terms “memory controller” and “scan converter.”
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`1.
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`“memory controller”
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`a.
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`The Correct Construction Of “memory controller”
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`The claimed “memory controller” is a limitation of every challenged claim.
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`For example, each challenged claim requires:
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`a memory controller … operative to transfer pixel data between each
`of a first pipeline and a second pipeline and a memory shared among
`the at least two graphics pipelines.
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`(’945 Patent at independent claim 1, dependent claims 2-11, and independent claim
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`21.)
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`Consistent with the plain and ordinary meaning of the foregoing explicit
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`claim language, the claimed “memory controller” should be construed to mean a
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`“logic circuit operative to transmit and receive processed pixel data to and from the
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`first pipeline, the second pipeline, and the first and second pipelines’ shared
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`memory.”
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`b.
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`Volkswagen’s Petition Depends On An Incorrect And
`Unsupported Construction Of “memory controller”
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`Petitioner incorrectly contends that “memory controller” should be
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`construed to mean merely “logic that transmits data to and from a memory.” (Pet.
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`at 15). This incorrect construction—on which Petitioner’s entire Petition
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`depends—improperly confines the required functionality of the memory controller
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`merely to transferring data to and from a memory, ignoring that it must also
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`transfer processed pixel data to and from the claimed first and second pipelines.
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`But Volkswagen’s Petition presents no analysis or evidence supporting this
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`attempt to broaden the meaning of the claimed “memory controller.” (Pet. at 15-
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`16). For example, Volkswagen does not state whether it contends that its
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`construction is the ordinary meaning of the claimed “memory controller” or is
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`based on some special definition purportedly provided in the ’945 Patent. (Id.) It
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`also fails to support either such possible theory. Volkswagen has therefore failed
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`to meet its burden on this limitation and, as a result, on its entire Petition.
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`i.
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`Volkswagen neither alleges nor proves that its
`construction is the ordinary meaning of the
`claimed “memory controller”
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`Volkswagen’s proposed construction is not the ordinary meaning and it does
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`assert otherwise. (Pet. at 15-16). Nor could Volkswagen reasonably assert that its
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`construction is the ordinary meaning because the plain language of the claims
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`explicitly states that the claimed memory controller is “operative to transfer pixel
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`data between each of a first pipeline and a second pipeline and a memory shared
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`among the at least two graphics pipelines.” (’945 Patent at independent claim 1,
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`dependent claims 2-11, and independent claim 21) (emphasis added).
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`Volkswagen’s proposed construction ignores the ordinary meaning of this
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`explicit claim language, requiring merely that the memory controller transmit “data
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`to and from a memory,” while ignoring the additional requirements concerning the
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`claimed first and second pipelines. This is improper as a matter of law. See, e.g.,
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`Hockerson-Halberstadt, Inc. v. Converse Inc., 183 F.3d 1369, 1374 (Fed. Cir.
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`1999) (“proper claim construction ... demands interpretation of the entire claim in
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`context, not a single element in isolation.”); ACTV, Inc. v. Walt Disney Co., 346
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`F.3d 1082, 1088 (Fed. Cir. 2003) (“While certain terms may be at the center of the
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`claim construction debate, the context of the surrounding words of the claim also
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`must be considered....”).
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`In contrast, AST’s proposed construction is consistent with and based on the
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`plain and ordinary meaning of the explicit claim language requiring that the
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`memory controller be operative between the shared memory and between the first
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`and second pipelines. Under AST’s proposed construction, “the claimed memory
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`controller” is a “logic circuit operative to transmit and receive processed pixel data
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`to and from the first pipeline, the second pipeline, and the first and second
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`pipelines’ shared memory.”
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`ii.
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`Volkswagen neither alleges nor proves that its
`construction is some purported special
`definition of the claimed “memory controller”
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`Volkswagen’s proposed construction also is not based on some special
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`definition provided in the ’945 Patent, and Volkswagen does assert otherwise.
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`(Pet. at 15-16). Volkswagen cites to and quotes a passage from the ’945 Patent’s
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`specification, but does not assert or support that this passage is a clear and
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`unambiguous special definition of the claimed “memory controller.” Moreover,
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`special definition or not, the specification passage quoted by Volkswagen supports
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`AST’s proposed construction, not Volkswagen’s. (Pet. at 16.) (collectively citing
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`the ‘945 patent, 5:4-7 and 5:34-44.)
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`The ’945 Patent’s specification describes that each pipeline includes back
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`end circuitry for processing pixel data. (’945 Patent at 4:5-15, 4:66 – 5:7, 5:28-36.)
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`As illustrated in Fig. 2 (reproduced below), the specification describes pipeline 101
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`including back end circuitry 39 and pipeline 102 as including back end circuitry
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`42. (’945 Patent at 4:5-15, 4:66 – 5:7, 5:28-36.) The specification further
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`describes (and Fig. 2 further illustrates) that the memory controller does not just
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`transmit data to the shared graphics memory 48, but also to, from, and between the
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`pipelines 101 and 102. (E.g., ’945 Patent at Fig. 2, 5:37-40.)
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`This interaction with and between the first and second pipelines is confirmed
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`by the only passage that Volkswagen quotes in support of its claim construction.
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`(Pet. at 16.) This passage makes clear that—consistent with AST’s construction—
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`the memory controller is operative to transmit and receive the processed pixel data
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`to and from the pipelines, and not just the shared memory as Volkswagen
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`proposes: “The memory controller 46 is operative to transmit and receive the
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`processed pixel data 43-44 from the backend circuitry 39 and 42 [of pipeline
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`101 and 102, respectively, and] transmit and receive pixel data 49 from the
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`graphics memory 48 … .” (Pet. at 16, ’945 Patent at Fig. 2, 5:37-40 (emphasis
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`added).