UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`VOLKSWAGEN GROUP OF AMERICA, INC.,
`Petitioner
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`v.
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`ADVANCED SILICON TECHNOLOGIES, LLC,
`Patent Owner
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`Case IPR2016-TBA
`Patent 8,933,945 B2
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`PETITION FOR INTER PARTES REVIEW
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`Mail Stop “PATENT BOARD”
`Patent Trial and Appeal Board
`U.S. Patent & Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
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`U.S. Patent No. 8,933,945 B2
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`TABLE OF CONTENTS
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`Introduction ........................................................................................................ 1 
`I. 
`II.  Mandatory Notices ............................................................................................. 2 
`A. Real parties-in-interest .................................................................................. 2 
`B.  Notice of related matters ............................................................................... 2 
`C.  Lead and back-up counsel with service information .................................... 3 
`III.  Overview of the ’945 patent ............................................................................... 3 
`A. The ’945 patent’s alleged novelty is tile-based, screen partitioning for
`balancing the processing workload among graphics pipelines. .................... 3 
`1.  The ’945 patent alleges that conventional strip-based, screen
`partitioning resulted in poor load balance. ............................................ 4 
`2.  The ’945 patent’s solution—and purported invention—is tile-
`based, screen partitioning. ..................................................................... 5 
`B.  The ’945 patent’s prosecution history demonstrates tile-based, screen
`partitioning for graphics processing was well-known by the earliest
`possible priority date. .................................................................................... 7 
`1.  At least five prior art references that were before the examiner
`during the ’945 patent’s prosecution disclose tile-based, screen
`partitioning or an obvious variant thereof. ............................................ 7 
`2.  The ’945 patent issued because the Board determined that the
`examiner did not address how Perego discloses a memory shared
`among pipelines. .................................................................................. 13 
`IV.  Grounds For Standing ...................................................................................... 14 
`V.  Statement of Relief Requested ......................................................................... 14 
`VI.  Claim Construction .......................................................................................... 14 
`A. memory controller ....................................................................................... 15 
`B.  scan converter .............................................................................................. 16 
`C.  graphics pipeline ......................................................................................... 18 
`1.  The claimed graphics pipeline includes hardware, which may be
`one or more circuits. ............................................................................ 18 
`2.  The claimed graphics pipeline processes graphics data for some,
`but not necessarily all, of the data to be displayed. ............................. 20 
`VII. Identification Of Challenge .............................................................................. 21 
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`U.S. Patent No. 8,933,945 B2
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`A. Ground 1: The combination of Narayanaswami and Gove renders
`claims 1, 9, 10, and 21 obvious. .................................................................. 23 
`1.  Overview of Narayanaswami .............................................................. 23 
`2.  Overview of Gove ............................................................................... 27 
`3.  Rationale for combining Narayanaswami and Gove .......................... 29 
`4.  Claim 1 is obvious over Narayanaswami and Gove. .......................... 30 
`5.  Claim 21 is obvious over Narayanaswami and Gove. ........................ 42 
`6.  Claim 9 is obvious over Narayanaswami and Gove. .......................... 46 
`7.  Claim 10 is obvious over Narayanaswami and Gove. ........................ 46 
`B.  Ground 2: The combination of Narayanaswami, Gove, and Foley render
`claims 2-4 and 6-7 obvious. ........................................................................ 47 
`1.  Claim 2 is obvious over Narayanaswami, Gove, and Foley. .............. 48 
`2.  Claim 3 is obvious over Narayanaswami, Gove, and Foley. .............. 50 
`3.  Claim 4 is obvious over Narayanaswami, Gove, and Foley. .............. 50 
`4.  Claim 6 is obvious over Narayanaswami, Gove, and Foley. .............. 53 
`5.  Claim 7 is obvious over Narayanaswami, Gove, and Foley. .............. 54 
`C.  Ground 3: The combination of Narayanaswami, Gove, Foley, and
`Kelleher render claims 5, 8, and 11 obvious. .............................................. 54 
`1.  Claim 5 is obvious over Narayanaswami, Gove, Foley, and
`Kelleher. .............................................................................................. 55 
`2.  Claims 8 and 11 are obvious over Narayanaswami, Gove, Foley,
`and Keheller. ....................................................................................... 58 
`VIII.  Conclusion .................................................................................................. 60 
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`U.S. Patent No. 8,933,945 B2
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`TABLE OF AUTHORITIES
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`Cases 
`ArcelorMittal France v. AK Steel Corp.,
`700 F.3d 1314 (Fed. Cir. 2012) ............................................................................ 18
`In re Translogic Tech., Inc.,
`504 F.3d 1249 (Fed. Cir. 2007) ............................................................................ 15
`KSR Int’l Co. v. Teleflex Inc.,
`550 U.S. 398 (2007). ............................................................................................ 15
`Phillips v. AWH Corp.,
`415 F.3d 1303 (Fed. Cir. 2005) ............................................................................ 17
`Standard Oil Co. v. Am. Cyanamid Co.,
`774 F.2d 448 (Fed. Cir. 1985) .............................................................................. 15
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`Statutes 
`35 U.S.C. § 102(b) ................................................................................................... 22
`35 U.S.C. § 103 ........................................................................................................ 22
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`Regulations 
`37 C.F.R. § 42.100(b) .............................................................................................. 15
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`U.S. Patent No. 8,933,945 B2
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`Exhibit
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`EXHIBIT LIST
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`DESCRIPTION
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`1001
`1002
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`1003
`1004
`1005
`1006
`1007
`1008
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`1009
`1010
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`1011
`1012
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`1013
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`1014
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`1015
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`U.S. Patent No. 8,933,945 B2 (“’945 patent”)
`File History of Application Serial No. 10/459,797, which became
`the ’945 patent, as filed and obtained from PAIR (“’945 file
`history”)
`Declaration of Dr. Donald S. Fussell
`U.S. Patent No. 6,778,177 to Furtner (“Furtner”)
`U.S. Patent No. 5,794,016 to Kelleher (“Kelleher”)
`U.S. Patent No. 6,864,896 to Perego (“Perego”)
`U.S. Patent No. 5,408,606 to Eckart (“Eckart”)
`U.S. Patent No. 5,757,385 to Narayanaswami et al.
`(“Narayanaswami”)
`U.S. Patent No. 6,070,003 to Gove et al. (“Gove”)
`“Computer Graphics Principles and Practice: Second Edition in C,”
`by Foley et al. (“Foley”)
`“3D Computer Graphics,” by Alan Watt (“Watt”)
`“Multiprocessor Methods for Computer Graphics Rendering,” by
`Scott Whitman (“Whitman”)
`“Cramming more components onto integrated circuits,” by Gordon
`Moore (“Moore”)
`“Miniaturization of electronics and its limits,” by R. W. Keyes
`(“Keyes”)
`TMS320C80 Datasheet
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`- iv -
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`U.S. Patent No. 8,933,945 B2
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`I.
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`Introduction
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`Volkswagen Group of America, Inc., (“Volkswagen” or “Petitioner”)
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`petitions for inter partes review seeking cancelation of claims 1-11 and 21
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`(“challenged claims”) of U.S. Patent No. 8,933,945 B2 (Ex. 1001, “’945 patent”),
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`assigned to Advanced Silicon Technologies, LLC (“AST”).
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`The ’945 patent purports to have invented tile-based, screen partitioning to
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`balance a graphics processing workload (“load balance”) among graphics
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`pipelines. It did not. Tile-based, screen partitioning for load balancing in graphics
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`processors was well-known long before the ’945 patent was filed.
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`Indeed, at least five prior art references disclosing tile-based, screen
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`partitioning (or an obvious variant thereof) were cited during prosecution of the
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`’945 patent. Since these references teach the crux of the alleged invention, the ’945
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`patent applicant slowly added insignificant and obvious limitations to the claims in
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`round-after-round of prosecution. Then, after more than a decade of prosecution,
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`the ’945 patent issued because the claims require a memory shared among graphics
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`pipelines—an obvious feature.
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`This Petition demonstrates that the challenged claims are obvious, relying on
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`two primary prior art patents (Narayanaswami and Gove) and Dr. Fussell’s expert
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`testimony. Narayanaswami teaches tile-based, screen partitioning and shared
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`memory; Gove teaches a memory controller and a single-chip implementation.
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`II. Mandatory Notices
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`A. Real parties-in-interest
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`U.S. Patent No. 8,933,945 B2
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`Volkswagen Group of America, Inc., which is a subsidiary of Volkswagen
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`AG.
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`B. Notice of related matters
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`AST asserted the ’945 patent in the following cases in the D. Del.: AST v.
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`Volkswagen AG, 1-15-cv-01181; AST v. Toyota Motor Co., 1-15-cv-01180; AST v.
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`Honda Motor Co., Ltd., 1-15-cv-01179; AST v. Bayerisch Motoren Werke AG, 1-
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`15-cv-01178; AST v. NVIDIA Corp., 1-15-cv-01177; AST v. Renesas Electronics
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`Corp., 1-15-cv-00176; AST v. Texas Instruments Inc., 1-15-cv-01175; AST v.
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`Fujitsu Ten Ltd. et al., 1-15-cv-01174; and AST v. Harman Int’l Industries, Inc., 1-
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`15-cv-01173. AST has also asserted the ’945 patent in the complaint “Certain
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`Computing or Graphics Systems, Components Thereof, and Vehicles Containing
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`Same,” Investigation No. 337-TA-984, filed December 28, 2015 at the U.S.
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`International Trade Commission, naming, among numerous others, Volkswagen
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`AG, Volkswagen Group of America, Inc., Volkswagen Group of America
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`Chattanooga Operations, LLC, Audi AG, and Audi of America, LLC as
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`respondents. Volkswagen Group of America Chattanooga Operations, LLC and
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`Audi of America, LLC are subsidiaries of Volkswagen Group of America, Inc.
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`Audi AG is a subsidiary of Volkswagen AG.
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`U.S. Patent No. 8,933,945 B2
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`C. Lead and back-up counsel with service information
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`Lead Counsel: Michael D. Specht (Reg. No. 54,463); 202.772.8756
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`Backup Counsel: Daniel E. Yonan (Reg. No. 53,812); 202.772.8899
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`Backup Counsel: Richard M. Bemben (Reg. No. 68,658); 202.772.8549
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`Address:
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`STERNE, KESSLER, GOLDSTEIN & FOX P.L.L.C.
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`1100 New York Avenue, NW, Washington, DC 20005
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`202.371.2540 (fax)
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`Petitioner consents to service via email at: mspecht-PTAB@skgf.com,
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`dyonan-PTAB@skgf.com, rbemben-PTAB@skgf.com, and PTAB@skgf.com.
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`III. Overview of the ’945 patent
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`The ’945 patent’s alleged novelty is tile-based, screen partitioning for
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`balancing a graphics processing workload among graphics pipelines. However, as
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`the ’945 patent’s prosecution history demonstrates, tile-based, screen partitioning
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`for graphics processing was well-known by the earliest possible priority date of the
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`’945 patent.
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`A. The ’945 patent’s alleged novelty is tile-based, screen partitioning
`for balancing the processing workload among graphics pipelines.
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`The ’945 patent “relates to graphics processing circuitry and, more
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`particularly, to dividing graphics processing operations among multiple pipelines.”
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`(’945 patent, 1:21-23.) It concedes that conventional “graphics processing systems
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`typically include a host processor, graphics (including video) processing circuitry,
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`U.S.
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`Patent No
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`memoryy (e.g. framme buffer), and one oor more dissplay devicces.” (Id. att 1:26-30.))
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`The graaphics proccessing circcuitry geneerates pixell data, whiich is preseented as ann
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`object oor a scene oon the dispplay screenn. (Id. at 1:226-43.) Thhis “pixel ddata is
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`typicallyy stored inn the framee buffer in aa manner tthat correspponds to thhe pixels
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`locationn on the dissplay devicce.” (Id. at 1:41-43.)
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`TThe ’945 paatent conceedes that prior art graaphics proccessing sysstems typiccally
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`divided the processsing workkload amonng several ggraphics pprocessing
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`circuits to
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`e processinng time. (IdId. at 1:45-660, 2:5-14
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`partitionned the dissplay screeen into horiizontal or vvertical strrips (“strip--based, scrreen
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`partitionning”), andd assigned different ggraphics prrocessing ccircuits to ggenerate thhe
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`pixels inn different
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`strips. (Idd.) But the ’’945 patennt asserts thhat strip-baased, screenn
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`partitionning sufferred from looad balanciing problemms. (Id. at
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`2:15-26.)
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`That is, th
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`processing worklooad was noot always eevenly distrributed ammong the ci
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`1.
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`The ’9455 patent allleges thatt conventioonal strip--based,
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`screen partitioning resultedd in poor looad balannce.
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`FFIG. 1 of thhe ’945 pattent (reprodduced, righht)
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`illustrattes a conveentional strrip-based, sscreen
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`partitionning techniique. Heree, the displaay screen iis
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`partitionned into a series of v
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`ertical stripps. (’945
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`ocessing patent, 1:44-51.) DDifferent ggraphics pr
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`are responnsible for pprocessing different sstrips. (Id.
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`at 2:5-14.)) “[F]or
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`U.S. Patent No. 8,933,945 B2
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`example, one graphics processing circuit is responsible for one vertical strip (e.g.
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`13) of the frame while another graphics processing circuit is responsible for
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`another vertical strip (e.g. 14) of the frame.” (Id.)
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`The ’945 patent alleges that this screen partitioning technique resulted in a
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`poor load balance “when all of the primitives 20-23 of a particular object or scene
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`are located in one strip (e.g. strip 13 [of FIG. 1]).” (Id. at 2:15-19.) “When this
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`occurs, only the graphics processing circuit responsible [for] strip 13 is actively
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`processing primitives; the remaining graphics processing circuits are idle,”
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`resulting in wasted resources. (Id. at 2:19-26.) The ’945 patent sought to overcome
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`this load balancing problem it associates with strip-based, screen partitioning.
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`2.
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`The ’945 patent’s solution—and purported invention—is
`tile-based, screen partitioning.
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`The ’945 patent purports to have invented tile-based, screen partitioning,
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`which allegedly achieves better load balance. (’945 patent, 3:21-31.) As shown in
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`FIGS. 2 and 3 of the ’945 patent (annotated and reproduced in-part below), the
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`specification describes a graphics processing circuit (labeled “34”) that includes at
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`least two graphics pipelines (labeled “101” and “102”) and a memory controller
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`(labeled “46”) that couples the pipelines to a graphics memory or frame buffer
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`(labeled “48”). (Id. at 3:21-31, 4:5-12, 5:37-65, FIG. 2.)
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`U.S.
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`Patent No
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`IG. 2 (in-ppart, annootated)
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`FIG.
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`3 (annotaated)
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`partitionned into reegions or tiles, which corresponnd to regionns of the d
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`isplay screeen.
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`(Id.) Thhe graphicss pipelines
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`tiles—thhe pipelinee labeled “101” proceesses the ggraphics daata in the “AA” tiles
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`B” tiles
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`in blue). (IId.) As shoown by thee color codding above,, this assiggnment of
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`FIG. 3 of thhe ’945 pattent depictss the framee buffer. (IId. at 5:45--65.) It is
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`pipelinees to tiles fforms a reppeating tilee pattern. (IId.)
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`TThis tiling ttechnique aallegedly aachieves beetter load bbalance thaan prior artt
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`techniquues, such aas the strip
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`-based, scrreen partitiioning. (Idd. at 1:44-2
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`:26, 3:21-331.)
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`But, as the ’945 patent’s proosecution hhistory demmonstrates,
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`partitionning techniiques for ggraphics prrocessing wwere well-kknown by tthe earliestt
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`B.
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`U.S. Patent No. 8,933,945 B2
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`The ’945 patent’s prosecution history demonstrates tile-based,
`screen partitioning for graphics processing was well-known by the
`earliest possible priority date.
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`The ’945 patent has a rich prosecution history that lasted more than a
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`decade. During that time, at least five prior art references teaching tile-based,
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`screen partitioning or an obvious variant thereof were either cited or directly
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`applied to the then-pending claims.
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`1.
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`At least five prior art references that were before the
`examiner during the ’945 patent’s prosecution disclose tile-
`based, screen partitioning or an obvious variant thereof.
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`The ’945 patent should not have issued. The ’945 patent’s prosecution lasted
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`more than a decade and at least five prior art references that were before the
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`examiner disclose tile-based, screen partitioning or an obvious variant thereof.
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`Since these references teach the crux of the alleged invention, the ’945 patent
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`applicant slowly added insignificant and obvious limitations to the claims in round-
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`after-round of prosecution until the ’945 patent issued. These references—Furtner,
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`Crockett, Foley, Kelleher, and Perego—are discussed in turn below.
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`The Examiner relied on Furtner (Ex. 1004) in a March 13, 2006 Office
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`Action. (’945 file history, 0137-48.) Furtner discloses a “graphics system with a
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`plurality of pipelines working in parallel” to render an image. (Furtner, 2:3-34,
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`FIG. 23 (pixel pipelines coupled to memory subsystem).) “Several image-
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`rendering pipelines” can be “supported on one individual chip.” (Id. at 6:31-34.)
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`U.S.
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`Patent No
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`Furtner also disclooses both bblock-based and pixeel-based, sccreen partittioning. (Idd. at
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`1:30-366 (partitioning frame bbuffer), 1:440-44, FIGG. 21a (bloock-based,
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`screen
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`partitionning), 1:444-56, FIG. 21b (interlleaved-pix
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`el-based, sscreen parttitioning); ssee
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`also id. at 5:12-444 (memory tiling).)
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`Furtnner, FIG.
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`21B
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`SShortly afteer the examminer issued the Marcch 13, 20066 Office AAction, the
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`’945 paatent appliccant filed aan informattion disclossure statemment (IDS)) that listedd
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`Crockettt (’945 filee history, 00153, 01566-80) and ccertain pagges from chhapter 18 oof
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`Foley (iid. at 0205-34), the fuull text of wwhich is suubmitted aas Ex. 10100. Section 33.4
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`of Crockett is titleed “Load bbalancing,”” and disclooses “[s]traategies for
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`dealing wwith
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`ge-space looad imbalaance.” (Id. at 0164.) CCrockett teeaches thatt tile-basedd,
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`screen ppartitioningg (specificaally using square tilees) has certtain advanttages over
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`pixel interleaving techniques (e.g., Furrtner’s FIGG. 21b):
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`U.S.
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`Patent No
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`. 8,933,9455 B2
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`mage partiitioning strrategies
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`oduced be
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`low] showws several i
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`with differeent load balancing chharacteristiccs. Large bblocks of
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`ontiguous pixels (Figg. 6a) usuaally result iin poor loaad balancinng, while
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`ine grainedd partitioniing schemees (Fig. 6c,, d) distribuute the loaad
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`better. Howwever, fine--grained scchemes aree subject too computattional
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`overheads ddue to loss of spatial coherencee . . . . Anallytical and
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`xperimentaal results . . . indicatee that squaare regions
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`minimize thhe loss of ccoherence since they
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`oo-area ratioo of any rectangular ssubdivisionn scheme.
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`(’945 file history, 0164-65.)
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`F w c f
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`(Id. at 00165.)
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`FFoley is onee of the moost well-knnown and ccommonlyy-cited treattises in
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`graphics processinng. (Fusselll Decl. (Exx. 1003), ¶¶¶ 5, 46-522, 61; see aalso Furtnerr,
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`1:16-200 (referenciing Foley);; Narayanaaswami (Exx. 1008), 11:26-32 (reeferencing
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`Foley); Eckart (Exx. 1007), 5:55-60 (refferencing FFoley).) Siimilar to Fuurtner, the
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`U.S.
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`Patent No
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`. 8,933,9455 B2
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`pages of Foley citted in the IDDS disclosse, inter aliia, block-bbased parti
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`tioning whhere
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`Fig. 18.177a of
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`“processors are asssigned to ccontiguouss blocks off pixels” (bbelow left,
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`interleavved manneer” (below right, Fig.. 18.17b off Foley). (’
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`see alsoo id. at 0211 (describiing multiprocessor ggraphics sy
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`Foley) aand pixel-bbased partiitioning whhere “proceessors are
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`assigned ppixels in ann
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`945 file hiistory, 022
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`2;
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`stems).)
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`Inn reply to tthe March 13, 2006 OOffice Actiion, the’9445 patent aapplicant
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`argued tthat neitheer the blockk-based nor the interlleaved pixeel-based, s
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`partitionning techniiques discllosed by Fuurtner teacch tile-baseed, screen ppartitionin
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`g.
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`(Id. at 00237, 0258-60.) In response, thee Examineer issued neew rejectioons based oon
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`Kelleheer (Ex. 1005) in a Febbruary 9, 2007 Officee Action. (IId. at 02700.)
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`KKelleher is directed too load balaancing multtiprocessorr graphics
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`(Kelleher, 1:26-522 (describinng basic prroblem of bbalancing
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`graphic
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`s processors).) In FIGGS. 2-3, KKelleher disscloses grapaphics systeems with
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`systems.
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`the worklooad amongg
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`U.S.
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`Patent No
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`. 8,933,9455 B2
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`multiplee renderingg processorrs. (Id. at 33:20-26.) FFIG. 2 is reeproduced bbelow andd
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`depicts a “graphiccs system wwith two reendering prrocessors.”” (Id. at 2:445-46.)
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`artitioningd, screen pas tile-baseder discloses6, KelleheInn FIGS. 4-
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`5:64, 8:41-42 (refferring to tiiling patterrn as “checckerboard ppattern”).)
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`reproduuced above and depiccts partitionning a grapphics mem
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`ory into 166 blocks off
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`pixels (llabeled 0-115) that co
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`rrespond too locationss of a displlay screen.
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`FIG. 6 is
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`51.) Twwo renderinng processoors (labeledd 0 and 1)
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`pattern that repeatts in the hoorizontal annd vertical
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`are allocatted to the 116 blocks iin a
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`directionss. (Id.)
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`TTo overcomme Kelleher, the ’9455 patent appplicant ammended thenn-pending
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`claim 1 to includee “a memorry controller in commmunicationn with” at l
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`s pipeliness. (’945 filee history, 00291.) ’9455 patent appplicant connceded thaat
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`east two
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`graphic
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`“Kellehher teaches that it is bbeneficial to provide eeach proceessor with
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`memoryy chip(s) annd own buus to the meemory chipp(s),” but aargued thatt Kelleher
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`U.S. Patent No. 8,933,945 B2
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`does not disclose the a memory controller in communication with two pipelines.
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`(Id. at 0300-02.) Dr. Fussell explains it would have been nothing more than an
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`obvious design choice to a POSITA to use a shared memory controller as opposed
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`to individual memory controllers. (Fussell Decl., ¶ 66.) Nonetheless, the examiner
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`withdrew the Kelleher-based rejections and applied Perego (Ex. 1006). (’945 file
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`history, 0333-45.)
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`The examiner relied on Perego in an Office Action that issued on August 28,
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`2007. (Id. at 0333-45.) In FIG. 3 of Perego (reproduced below), Perego discloses
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`“a scalable unified memory architecture 300 that supports parallel processing of
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`graphical data and/or graphical instructions.” (Perego, 3:61-63.) As shown, Perego
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`discloses a plurality of rendering engines that share a memory controller. (Id. at
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`3:65-4:2, 7:35-38 (multiple graphics rendering engines connected to memory
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`controller); 4:26-36 (graphics rendering engines).) FIG. 5 of Perego (reproduced
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`below) discloses tile-based, screen partitioning. (Id. at 5:23-50, FIGS 4-5.)
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`FIG. 5 “illustrates a graphical rendering surface divided into sixteen
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`different sections of ‘tiles’ (four rows and four column).” (Id. at 5:29-31 (emphasis
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`added).) “The graphical rendering surface may be stored in, for example, an image
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`buffer of displayed on a display device.” (Id. at 5:32-33 (emphasis added).) Perego
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`discloses that the memory controller/graphics controller 310 of FIG. 3 “divide[s]
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`the processing tasks into different portions” and assigns different rendering engines
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`- 12 -
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`U.S.
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`Patent No
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`. 8,933,9455 B2
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`(e.g., REE0, RE1, RRE2, and RRE3 of FIGG. 5) “to prrocess diffeerent regioons of the
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`surface simultaneoously.” (Idd. at 5:33-550.)
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`2.
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`The ’9455 patent isssued becaause the Booard deterrmined thhat
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`the examminer did nnot addresss how Pe
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`rego disclloses a
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`memoryy shared ammong pipeelines.
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`AAfter the August 28, 22007 Officce Action, tthe ’945 paatent appliicant and thhe
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`examineer exchangged argumeents involvving Peregoo for severral years. (SSee ’945 fifile
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`history, 0345-632.) During tthis period, the ’945 ppatent appplicant madde minor
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`amendmments to then-pendingg claim 1 tto require tthe graphiccs pipeline
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`s and memmory
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`controlller to be onn the same chip (id. aat 0350, 03355, 0514),, and that aa memory iis
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`shared aamong the pipelines ((id. at 057
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`icant appe
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`ealed to thee Board in
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`early 20111.
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`(Id. at 00632-68.) OOn Appeal, the Boardd found thaat the examminer failedd to show tthat
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`Perego discloses tthe limitatiion “a memmory sharedd among thhe at least
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`two graphhics
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`- 13 -
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`U.S. Patent No. 8,933,945 B2
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`pipelines” in system claims 1 and 25 (id. at 0720), which issued as patent claims 1
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`and 21 (id. at 0737), and the application issued as the ’945 patent.
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`*
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`*
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`*
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`Thus, the ’945 patent did not issue because it discloses novel and
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`nonobvious tile-based, screen partitioning. Rather, it issued because the examiner
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`failed to establish that a simple and obvious structural feature—a memory shared
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`among pipelines—was known. (Fussell Decl., ¶¶ 69-70.)
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`IV. Grounds For Standing
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`Petitioner certifies that the patent for which review is sought is eligible for
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`inter partes review and that the Petitioner is not barred or estopped from requesting
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`inter partes review challenging the patent claims on the grounds identified in this
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`Petition. The required fee is paid via online credit card payment. The Office is
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`authorized to charge fee deficiencies and credit overpayments to Deposit Acct. No.
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`19-0036 (Customer ID No. 45324).
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`V.
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`Statement of Relief Requested
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`Petitioner respectfully requests inter partes review and cancelation of the
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`challenged claims based on the detailed statements presented below.
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`VI. Claim Construction
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`In an inter partes review, claim terms in an unexpired patent are given their
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`broadest reasonable construction in light of the specification of the patent in which
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`U.S. Patent No. 8,933,945 B2
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`they appear. 37 C.F.R. § 42.100(b). Claim terms are generally given their ordinary
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`and customary meaning as would be understood by a person of ordinary skill in the
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`art (“POSITA”) in the context of the entire disclosure. In re Translogic Tech., Inc.,
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`504 F.3d 1249, 1257 (Fed. Cir. 2007).
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`A POSITA is a hypothetical person who is “presumed to be aware of all the
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`pertinent prior art.” Standard Oil Co. v. Am. Cyanamid Co., 774 F.2d 448, 454
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`(Fed. Cir. 1985). This hypothetical person “is also a person of ordinary creativity,
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`not an automaton.” KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 421 (2007). With
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`respect to the ’945 patent, a POSITA would have at least the equivalent of a
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`Bachelor’s degree in Electrical or Computer Engineering, at least four years of
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`experience in computer hardware architecture research or development, and a
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`familiarity with computer graphics. Experience could take the place of some
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`formal training, as domain knowledge may be learned on the job. This description
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`is approximate, and a higher level of education or skill might make up for less
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`experience and vice versa. (Fussell Decl., ¶¶ 35-36.)
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`A. memory controller
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`The claims recite the term “memory controller.” In the context of the ’945
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`patent, a POSITA would have understood this term to mean “logic that transmits
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`data to and from a memory.” (Fussell Decl., ¶¶ 71-72.)
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`U.S. Patent No. 8,933,945 B2
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`The ’945 patent claims and specification support this construction. Claims 1
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`and 21 require the memory controller to be on a “chip,” and that the memory
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`controller is “operative to transfer” pixel data between graphics pipelines and a
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`memory. The specification, which provides little description of a memory
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`controller, describes a memory controller as “operative to transmit and receive the
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`processed pixel data 43-44 from the back end circuitry 39 and 42; transmit and
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`retrieve pixel data 49 from the graphics memory 48; and in a single circuit
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`implementation, transmit pixel data 50 for presentation on a suitable display 51.”
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`(’945 patent, 5:37-44; see also id. at 5:4-7, 5:34-37.) Thus, a “memory controller”
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`is “logic that transmits data to and from a memory.” (Fussell Decl., ¶¶ 72-76.)
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`B.
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`scan converter
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`Claim 5 recites the term “scan converter.” In the context of the ’945 patent,
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`a POSITA would have understood this term to mean “logic for identifying the
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`pixels to be processed.” (Fussell Decl., ¶¶ 77-79.)
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`The ’945 patent claims and specification support this construction. In the
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`’945 patent, front-end circuitry generates the pixel data. (Id. at 4:39-42, claim 4.)
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`The scan converter receives the pixel data and identifies the pixels to be processed
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`by back-end circuitry. (’945 patent, 4:39-52, claim 5.) For example, discussing
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`FIGS. 2 and 3, the ’945 patent specification states:
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`U.S. Patent No. 8,933,945 B2
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`The scan converter 37 of the first graphics pipeline 101 receives the
`pixel data 36 and sequentially provides the position (e.g. x, y)
`coordinates 60 in screen space of the pixels to be processed by the
`back end circuitry 39 by determining or identifying those pixels of
`the primitive, for example, the pixels within portions 81-82 of the
`triangle 80 (FIG. 3) that intersect the tile or set of tiles that the back
`end circuitry 39 is responsible for processing.
`(Id. at 4:45-52 (emphasis added).)
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`The ’945 patent’s description of a scan converter is not consistent with the
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`ordinary meaning of this term. (Fussell Decl., ¶¶ 80-81.) Applying its ordinary
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`meaning, a POSITA would have understood a scan converter to be logic used in
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`the process of generating pixel data. (Id. (citing Foley, 0038 (“primitives such as
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`lines and polygons are specified in terms of their endpoints (vertices) and must be
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`scan-converted into their component pixels in the frame buffer”)); Whitman, 0054
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`(“[e]ach processor scan-converts a single polygon as a task and writes the pixel
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`value into the scattered frame buffer”); Narayanaswami 1:38-39 (“scan converting
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`each received graphical object into pixels”), 7:21-22 (“the subobject is then scan
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`converted into pixels”).) But the ’945 patent expressly states that front-end
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`circuitry generates the pixel data (’945 patent, 4:39-42, claim 4), not the scan
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`converter.
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`“The specification is the ‘single best guide to the meaning of a disputed
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`term.’” Phillips v. AWH Corp., 415 F.3d 1303, 1320-21 (Fed. Cir. 2005) (int