`
`
`
`
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`
`
`
`
`
`VOLKSWAGEN GROUP OF AMERICA, INC.,
`Petitioner
`
`v.
`
`ADVANCED SILICON TECHNOLOGIES, LLC,
`Patent Owner
`
`
`
`Case IPR2016-TBA
`Patent 8,933,945 B2
`
`
`
`
`PETITION FOR INTER PARTES REVIEW
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Mail Stop “PATENT BOARD”
`Patent Trial and Appeal Board
`U.S. Patent & Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`
`
`
`
`
`U.S. Patent No. 8,933,945 B2
`
`TABLE OF CONTENTS
`
`Introduction ........................................................................................................ 1
`I.
`II. Mandatory Notices ............................................................................................. 2
`A. Real parties-in-interest .................................................................................. 2
`B. Notice of related matters ............................................................................... 2
`C. Lead and back-up counsel with service information .................................... 3
`III. Overview of the ’945 patent ............................................................................... 3
`A. The ’945 patent’s alleged novelty is tile-based, screen partitioning for
`balancing the processing workload among graphics pipelines. .................... 3
`1. The ’945 patent alleges that conventional strip-based, screen
`partitioning resulted in poor load balance. ............................................ 4
`2. The ’945 patent’s solution—and purported invention—is tile-
`based, screen partitioning. ..................................................................... 5
`B. The ’945 patent’s prosecution history demonstrates tile-based, screen
`partitioning for graphics processing was well-known by the earliest
`possible priority date. .................................................................................... 7
`1. At least five prior art references that were before the examiner
`during the ’945 patent’s prosecution disclose tile-based, screen
`partitioning or an obvious variant thereof. ............................................ 7
`2. The ’945 patent issued because the Board determined that the
`examiner did not address how Perego discloses a memory shared
`among pipelines. .................................................................................. 13
`IV. Grounds For Standing ...................................................................................... 14
`V. Statement of Relief Requested ......................................................................... 14
`VI. Claim Construction .......................................................................................... 14
`A. memory controller ....................................................................................... 15
`B. scan converter .............................................................................................. 16
`C. graphics pipeline ......................................................................................... 18
`1. The claimed graphics pipeline includes hardware, which may be
`one or more circuits. ............................................................................ 18
`2. The claimed graphics pipeline processes graphics data for some,
`but not necessarily all, of the data to be displayed. ............................. 20
`VII. Identification Of Challenge .............................................................................. 21
`
`
`
`- i -
`
`
`
`
`
`
`
`U.S. Patent No. 8,933,945 B2
`
`A. Ground 1: The combination of Narayanaswami and Gove renders
`claims 1, 9, 10, and 21 obvious. .................................................................. 23
`1. Overview of Narayanaswami .............................................................. 23
`2. Overview of Gove ............................................................................... 27
`3. Rationale for combining Narayanaswami and Gove .......................... 29
`4. Claim 1 is obvious over Narayanaswami and Gove. .......................... 30
`5. Claim 21 is obvious over Narayanaswami and Gove. ........................ 42
`6. Claim 9 is obvious over Narayanaswami and Gove. .......................... 46
`7. Claim 10 is obvious over Narayanaswami and Gove. ........................ 46
`B. Ground 2: The combination of Narayanaswami, Gove, and Foley render
`claims 2-4 and 6-7 obvious. ........................................................................ 47
`1. Claim 2 is obvious over Narayanaswami, Gove, and Foley. .............. 48
`2. Claim 3 is obvious over Narayanaswami, Gove, and Foley. .............. 50
`3. Claim 4 is obvious over Narayanaswami, Gove, and Foley. .............. 50
`4. Claim 6 is obvious over Narayanaswami, Gove, and Foley. .............. 53
`5. Claim 7 is obvious over Narayanaswami, Gove, and Foley. .............. 54
`C. Ground 3: The combination of Narayanaswami, Gove, Foley, and
`Kelleher render claims 5, 8, and 11 obvious. .............................................. 54
`1. Claim 5 is obvious over Narayanaswami, Gove, Foley, and
`Kelleher. .............................................................................................. 55
`2. Claims 8 and 11 are obvious over Narayanaswami, Gove, Foley,
`and Keheller. ....................................................................................... 58
`VIII. Conclusion .................................................................................................. 60
`
`
`
`
`
`
`
`
`- ii -
`
`
`
`
`
`
`
`U.S. Patent No. 8,933,945 B2
`
`TABLE OF AUTHORITIES
`
`Cases
`ArcelorMittal France v. AK Steel Corp.,
`700 F.3d 1314 (Fed. Cir. 2012) ............................................................................ 18
`In re Translogic Tech., Inc.,
`504 F.3d 1249 (Fed. Cir. 2007) ............................................................................ 15
`KSR Int’l Co. v. Teleflex Inc.,
`550 U.S. 398 (2007). ............................................................................................ 15
`Phillips v. AWH Corp.,
`415 F.3d 1303 (Fed. Cir. 2005) ............................................................................ 17
`Standard Oil Co. v. Am. Cyanamid Co.,
`774 F.2d 448 (Fed. Cir. 1985) .............................................................................. 15
`
`Statutes
`35 U.S.C. § 102(b) ................................................................................................... 22
`35 U.S.C. § 103 ........................................................................................................ 22
`
`Regulations
`37 C.F.R. § 42.100(b) .............................................................................................. 15
`
`
`
`
`
`
`
`
`- iii -
`
`
`
`
`
`U.S. Patent No. 8,933,945 B2
`
`Exhibit
`
`EXHIBIT LIST
`
`DESCRIPTION
`
`1001
`1002
`
`1003
`1004
`1005
`1006
`1007
`1008
`
`1009
`1010
`
`1011
`1012
`
`1013
`
`1014
`
`1015
`
`U.S. Patent No. 8,933,945 B2 (“’945 patent”)
`File History of Application Serial No. 10/459,797, which became
`the ’945 patent, as filed and obtained from PAIR (“’945 file
`history”)
`Declaration of Dr. Donald S. Fussell
`U.S. Patent No. 6,778,177 to Furtner (“Furtner”)
`U.S. Patent No. 5,794,016 to Kelleher (“Kelleher”)
`U.S. Patent No. 6,864,896 to Perego (“Perego”)
`U.S. Patent No. 5,408,606 to Eckart (“Eckart”)
`U.S. Patent No. 5,757,385 to Narayanaswami et al.
`(“Narayanaswami”)
`U.S. Patent No. 6,070,003 to Gove et al. (“Gove”)
`“Computer Graphics Principles and Practice: Second Edition in C,”
`by Foley et al. (“Foley”)
`“3D Computer Graphics,” by Alan Watt (“Watt”)
`“Multiprocessor Methods for Computer Graphics Rendering,” by
`Scott Whitman (“Whitman”)
`“Cramming more components onto integrated circuits,” by Gordon
`Moore (“Moore”)
`“Miniaturization of electronics and its limits,” by R. W. Keyes
`(“Keyes”)
`TMS320C80 Datasheet
`
`- iv -
`
`
`
`
`
`
`
`
`
`U.S. Patent No. 8,933,945 B2
`
`
`I.
`
`Introduction
`
`Volkswagen Group of America, Inc., (“Volkswagen” or “Petitioner”)
`
`petitions for inter partes review seeking cancelation of claims 1-11 and 21
`
`(“challenged claims”) of U.S. Patent No. 8,933,945 B2 (Ex. 1001, “’945 patent”),
`
`assigned to Advanced Silicon Technologies, LLC (“AST”).
`
`The ’945 patent purports to have invented tile-based, screen partitioning to
`
`balance a graphics processing workload (“load balance”) among graphics
`
`pipelines. It did not. Tile-based, screen partitioning for load balancing in graphics
`
`processors was well-known long before the ’945 patent was filed.
`
`Indeed, at least five prior art references disclosing tile-based, screen
`
`partitioning (or an obvious variant thereof) were cited during prosecution of the
`
`’945 patent. Since these references teach the crux of the alleged invention, the ’945
`
`patent applicant slowly added insignificant and obvious limitations to the claims in
`
`round-after-round of prosecution. Then, after more than a decade of prosecution,
`
`the ’945 patent issued because the claims require a memory shared among graphics
`
`pipelines—an obvious feature.
`
`This Petition demonstrates that the challenged claims are obvious, relying on
`
`two primary prior art patents (Narayanaswami and Gove) and Dr. Fussell’s expert
`
`testimony. Narayanaswami teaches tile-based, screen partitioning and shared
`
`memory; Gove teaches a memory controller and a single-chip implementation.
`
`
`
`- 1 -
`
`
`
`
`
`
`II. Mandatory Notices
`
`A. Real parties-in-interest
`
`U.S. Patent No. 8,933,945 B2
`
`Volkswagen Group of America, Inc., which is a subsidiary of Volkswagen
`
`AG.
`
`B. Notice of related matters
`
`AST asserted the ’945 patent in the following cases in the D. Del.: AST v.
`
`Volkswagen AG, 1-15-cv-01181; AST v. Toyota Motor Co., 1-15-cv-01180; AST v.
`
`Honda Motor Co., Ltd., 1-15-cv-01179; AST v. Bayerisch Motoren Werke AG, 1-
`
`15-cv-01178; AST v. NVIDIA Corp., 1-15-cv-01177; AST v. Renesas Electronics
`
`Corp., 1-15-cv-00176; AST v. Texas Instruments Inc., 1-15-cv-01175; AST v.
`
`Fujitsu Ten Ltd. et al., 1-15-cv-01174; and AST v. Harman Int’l Industries, Inc., 1-
`
`15-cv-01173. AST has also asserted the ’945 patent in the complaint “Certain
`
`Computing or Graphics Systems, Components Thereof, and Vehicles Containing
`
`Same,” Investigation No. 337-TA-984, filed December 28, 2015 at the U.S.
`
`International Trade Commission, naming, among numerous others, Volkswagen
`
`AG, Volkswagen Group of America, Inc., Volkswagen Group of America
`
`Chattanooga Operations, LLC, Audi AG, and Audi of America, LLC as
`
`respondents. Volkswagen Group of America Chattanooga Operations, LLC and
`
`Audi of America, LLC are subsidiaries of Volkswagen Group of America, Inc.
`
`Audi AG is a subsidiary of Volkswagen AG.
`
`
`
`- 2 -
`
`
`
`
`
`U.S. Patent No. 8,933,945 B2
`
`C. Lead and back-up counsel with service information
`
`Lead Counsel: Michael D. Specht (Reg. No. 54,463); 202.772.8756
`
`Backup Counsel: Daniel E. Yonan (Reg. No. 53,812); 202.772.8899
`
`Backup Counsel: Richard M. Bemben (Reg. No. 68,658); 202.772.8549
`
`Address:
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`STERNE, KESSLER, GOLDSTEIN & FOX P.L.L.C.
`
`1100 New York Avenue, NW, Washington, DC 20005
`
`202.371.2540 (fax)
`
`Petitioner consents to service via email at: mspecht-PTAB@skgf.com,
`
`
`
`
`
`
`
`
`
`
`
`
`
`dyonan-PTAB@skgf.com, rbemben-PTAB@skgf.com, and PTAB@skgf.com.
`
`III. Overview of the ’945 patent
`
`The ’945 patent’s alleged novelty is tile-based, screen partitioning for
`
`balancing a graphics processing workload among graphics pipelines. However, as
`
`the ’945 patent’s prosecution history demonstrates, tile-based, screen partitioning
`
`for graphics processing was well-known by the earliest possible priority date of the
`
`’945 patent.
`
`A. The ’945 patent’s alleged novelty is tile-based, screen partitioning
`for balancing the processing workload among graphics pipelines.
`
`The ’945 patent “relates to graphics processing circuitry and, more
`
`particularly, to dividing graphics processing operations among multiple pipelines.”
`
`(’945 patent, 1:21-23.) It concedes that conventional “graphics processing systems
`
`typically include a host processor, graphics (including video) processing circuitry,
`
`
`
`- 3 -
`
`
`
`
`
`U.S.
`
`Patent No
`
`
`
`. 8,933,9455 B2
`
`
`
`
`
`
`memoryy (e.g. framme buffer), and one oor more dissplay devicces.” (Id. att 1:26-30.))
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`The graaphics proccessing circcuitry geneerates pixell data, whiich is preseented as ann
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`object oor a scene oon the dispplay screenn. (Id. at 1:226-43.) Thhis “pixel ddata is
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`typicallyy stored inn the framee buffer in aa manner tthat correspponds to thhe pixels
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`locationn on the dissplay devicce.” (Id. at 1:41-43.)
`
`
`
`
`
`
`
`
`
`TThe ’945 paatent conceedes that prior art graaphics proccessing sysstems typiccally
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`divided the processsing workkload amonng several ggraphics pprocessing
`
`
`
`
`
`
`
`
`
`
`
`circuits to
`
`
`decreas
`
`
`
`
`
`e processinng time. (IdId. at 1:45-660, 2:5-14
`
`
`
`.) One connventional
`
`technique
`
`
`
`partitionned the dissplay screeen into horiizontal or vvertical strrips (“strip--based, scrreen
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`partitionning”), andd assigned different ggraphics prrocessing ccircuits to ggenerate thhe
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`pixels inn different
`
`
`
`strips. (Idd.) But the ’’945 patennt asserts thhat strip-baased, screenn
`
`
`
`
`
`
`
`
`
`
`
`
`
`partitionning sufferred from looad balanciing problemms. (Id. at
`
`
`
`
`
`
`
`
`
`2:15-26.)
`
`That is, th
`
`e
`
`
`
`rcuits. (Id..)
`
`
`
`processing worklooad was noot always eevenly distrributed ammong the ci
`
`
`
`
`
`
`
`
`
`
`
`1.
`
`
`
`
`
`
`The ’9455 patent allleges thatt conventioonal strip--based,
`
`
`
`
`
`screen partitioning resultedd in poor looad balannce.
`
`
`
`
`
`
`
`
`
`FFIG. 1 of thhe ’945 pattent (reprodduced, righht)
`
`
`
`
`
`illustrattes a conveentional strrip-based, sscreen
`
`
`
`
`
`
`
`
`
`partitionning techniique. Heree, the displaay screen iis
`
`
`
`
`
`
`
`
`
`
`
`partitionned into a series of v
`
`
`
`
`
`ertical stripps. (’945
`
`
`
`
`
`
`
`ocessing patent, 1:44-51.) DDifferent ggraphics pr
`
`
`circuits
`
`
`
`
`are responnsible for pprocessing different sstrips. (Id.
`
`
`
`
`
`
`
`at 2:5-14.)) “[F]or
`
`
`
`- 4 -
`
`
`
`
`
`U.S. Patent No. 8,933,945 B2
`
`
`example, one graphics processing circuit is responsible for one vertical strip (e.g.
`
`13) of the frame while another graphics processing circuit is responsible for
`
`another vertical strip (e.g. 14) of the frame.” (Id.)
`
`The ’945 patent alleges that this screen partitioning technique resulted in a
`
`poor load balance “when all of the primitives 20-23 of a particular object or scene
`
`are located in one strip (e.g. strip 13 [of FIG. 1]).” (Id. at 2:15-19.) “When this
`
`occurs, only the graphics processing circuit responsible [for] strip 13 is actively
`
`processing primitives; the remaining graphics processing circuits are idle,”
`
`resulting in wasted resources. (Id. at 2:19-26.) The ’945 patent sought to overcome
`
`this load balancing problem it associates with strip-based, screen partitioning.
`
`2.
`
`The ’945 patent’s solution—and purported invention—is
`tile-based, screen partitioning.
`
`The ’945 patent purports to have invented tile-based, screen partitioning,
`
`which allegedly achieves better load balance. (’945 patent, 3:21-31.) As shown in
`
`FIGS. 2 and 3 of the ’945 patent (annotated and reproduced in-part below), the
`
`specification describes a graphics processing circuit (labeled “34”) that includes at
`
`least two graphics pipelines (labeled “101” and “102”) and a memory controller
`
`(labeled “46”) that couples the pipelines to a graphics memory or frame buffer
`
`(labeled “48”). (Id. at 3:21-31, 4:5-12, 5:37-65, FIG. 2.)
`
`
`
`- 5 -
`
`
`
`
`
`
`
`U.S.
`
`Patent No
`
`
`
`. 8,933,9455 B2
`
`
`
`IG. 2 (in-ppart, annootated)
`
`
`
`
`
`
`
`FIG.
`
`
`
`3 (annotaated)
`
`
`
`
`
`
`
`partitionned into reegions or tiles, which corresponnd to regionns of the d
`
`
`
`
`
`
`
`
`
`isplay screeen.
`
`(Id.) Thhe graphicss pipelines
`are assign
`
`
`
`
`ed to proceess the graaphics dataa in certain
`
`
`
`
`
`
`
`
`
`tiles—thhe pipelinee labeled “101” proceesses the ggraphics daata in the “AA” tiles
`
`
`
`
`
`
`
`
`
`
`
`
`
`B” tiles
`(shown in red); thhe pipeline labeled “102” processses the daata in the “B
`
`
`
`
`
`
`
`
`
`
`
`
`
`in blue). (IId.) As shoown by thee color codding above,, this assiggnment of
`
`F F
`
`
`
`FIG. 3 of thhe ’945 pattent depictss the framee buffer. (IId. at 5:45--65.) It is
`
`
`
`
`
`
`
`
`
`
`
`
`(shown
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`pipelinees to tiles fforms a reppeating tilee pattern. (IId.)
`
`
`
`
`
`TThis tiling ttechnique aallegedly aachieves beetter load bbalance thaan prior artt
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`techniquues, such aas the strip
`
`
`
`
`
`
`
`
`
`-based, scrreen partitiioning. (Idd. at 1:44-2
`
`
`
`:26, 3:21-331.)
`
`
`
`But, as the ’945 patent’s proosecution hhistory demmonstrates,
`
`
`
`
`
`
`
`
`
`
`
` tile-basedd, screen
`
`
`
`partitionning techniiques for ggraphics prrocessing wwere well-kknown by tthe earliestt
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`possiblee priority ddate.
`
`
`
`
`
`- 6 -
`
`
`
`
`
`B.
`
`
`
`U.S. Patent No. 8,933,945 B2
`
`The ’945 patent’s prosecution history demonstrates tile-based,
`screen partitioning for graphics processing was well-known by the
`earliest possible priority date.
`
`The ’945 patent has a rich prosecution history that lasted more than a
`
`decade. During that time, at least five prior art references teaching tile-based,
`
`screen partitioning or an obvious variant thereof were either cited or directly
`
`applied to the then-pending claims.
`
`1.
`
`At least five prior art references that were before the
`examiner during the ’945 patent’s prosecution disclose tile-
`based, screen partitioning or an obvious variant thereof.
`
`The ’945 patent should not have issued. The ’945 patent’s prosecution lasted
`
`more than a decade and at least five prior art references that were before the
`
`examiner disclose tile-based, screen partitioning or an obvious variant thereof.
`
`Since these references teach the crux of the alleged invention, the ’945 patent
`
`applicant slowly added insignificant and obvious limitations to the claims in round-
`
`after-round of prosecution until the ’945 patent issued. These references—Furtner,
`
`Crockett, Foley, Kelleher, and Perego—are discussed in turn below.
`
`The Examiner relied on Furtner (Ex. 1004) in a March 13, 2006 Office
`
`Action. (’945 file history, 0137-48.) Furtner discloses a “graphics system with a
`
`plurality of pipelines working in parallel” to render an image. (Furtner, 2:3-34,
`
`FIG. 23 (pixel pipelines coupled to memory subsystem).) “Several image-
`
`rendering pipelines” can be “supported on one individual chip.” (Id. at 6:31-34.)
`
`
`
`- 7 -
`
`
`
`
`
`U.S.
`
`Patent No
`
`
`
`. 8,933,9455 B2
`
`
`
`
`
`
`Furtner also disclooses both bblock-based and pixeel-based, sccreen partittioning. (Idd. at
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`1:30-366 (partitioning frame bbuffer), 1:440-44, FIGG. 21a (bloock-based,
`
`
`
`
`
`
`
`
`
`
`
`screen
`
`
`
`partitionning), 1:444-56, FIG. 21b (interlleaved-pix
`
`
`
`
`
`
`
`
`
`el-based, sscreen parttitioning); ssee
`
`
`
`
`
`
`
`also id. at 5:12-444 (memory tiling).)
`
`
`
`
`
`3
`Furtner, FIG. 2
`
`
`
`
`
`Furtnner, FIG.
`
`21B
`
`
`
`
`
`
`
`
`
`
`
`
`
`SShortly afteer the examminer issued the Marcch 13, 20066 Office AAction, the
`
`
`
`
`
`
`
`
`
`
`
`
`
`’945 paatent appliccant filed aan informattion disclossure statemment (IDS)) that listedd
`
`
`
`
`
`
`
`
`
`
`
`Crockettt (’945 filee history, 00153, 01566-80) and ccertain pagges from chhapter 18 oof
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Foley (iid. at 0205-34), the fuull text of wwhich is suubmitted aas Ex. 10100. Section 33.4
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`of Crockett is titleed “Load bbalancing,”” and disclooses “[s]traategies for
`
`
`
`
`
`
`
`
`
`
`
`
`
`dealing wwith
`
`. . . ima
`
`
`
`
`ge-space looad imbalaance.” (Id. at 0164.) CCrockett teeaches thatt tile-basedd,
`
`
`
`
`
`
`
`
`
`
`
`
`
`screen ppartitioningg (specificaally using square tilees) has certtain advanttages over
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`pixel interleaving techniques (e.g., Furrtner’s FIGG. 21b):
`
`
`
`
`
`- 8 -
`
`
`
`
`
`
`
`U.S.
`
`Patent No
`
`
`
`. 8,933,9455 B2
`
`mage partiitioning strrategies
`
`oduced be
`
`
`Fig. 6 [repr
`
`low] showws several i
`
`
`
`
`
`with differeent load balancing chharacteristiccs. Large bblocks of
`
`
`
`
`
`
`ontiguous pixels (Figg. 6a) usuaally result iin poor loaad balancinng, while
`
`
`
`
`
`
`ine grainedd partitioniing schemees (Fig. 6c,, d) distribuute the loaad
`
`
`
`
`
`
`better. Howwever, fine--grained scchemes aree subject too computattional
`
`
`
`
`
`
`overheads ddue to loss of spatial coherencee . . . . Anallytical and
`
`
`
`xperimentaal results . . . indicatee that squaare regions
`(Fig. 6b)
`
`
`
`have the ssmallest peerimeter-
`
`
`
`minimize thhe loss of ccoherence since they
`
`
`
`oo-area ratioo of any rectangular ssubdivisionn scheme.
`
`
`
`
`
`(’945 file history, 0164-65.)
`
`F w c f
`
`i b o e m t
`
`
`
`(Id. at 00165.)
`
`
`
`
`
`
`
`
`
`
`
`
`
`FFoley is onee of the moost well-knnown and ccommonlyy-cited treattises in
`
`
`
`
`
`
`
`graphics processinng. (Fusselll Decl. (Exx. 1003), ¶¶¶ 5, 46-522, 61; see aalso Furtnerr,
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`1:16-200 (referenciing Foley);; Narayanaaswami (Exx. 1008), 11:26-32 (reeferencing
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Foley); Eckart (Exx. 1007), 5:55-60 (refferencing FFoley).) Siimilar to Fuurtner, the
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`- 9 -
`
`
`
`
`
`U.S.
`
`Patent No
`
`
`
`. 8,933,9455 B2
`
`
`
`
`
`
`pages of Foley citted in the IDDS disclosse, inter aliia, block-bbased parti
`
`
`
`
`
`
`
`
`
`
`
`tioning whhere
`
`
`
`Fig. 18.177a of
`
`
`
`“processors are asssigned to ccontiguouss blocks off pixels” (bbelow left,
`
`
`
`
`
`
`
`
`
`
`
`
`
`interleavved manneer” (below right, Fig.. 18.17b off Foley). (’
`
`
`
`
`
`
`
`
`
`see alsoo id. at 0211 (describiing multiprocessor ggraphics sy
`
`
`
`
`
`
`
`
`
`
`
`Foley) aand pixel-bbased partiitioning whhere “proceessors are
`
`
`
`
`
`
`
`
`
`
`
`
`
`assigned ppixels in ann
`
`
`
`
`
`945 file hiistory, 022
`
`2;
`
`stems).)
`
`
`
`
`
`
`
`
`
`
`
`
`
`Inn reply to tthe March 13, 2006 OOffice Actiion, the’9445 patent aapplicant
`
`
`
`
`
`argued tthat neitheer the blockk-based nor the interlleaved pixeel-based, s
`
`creen
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`partitionning techniiques discllosed by Fuurtner teacch tile-baseed, screen ppartitionin
`
`
`
`
`
`
`
`
`
`
`
`
`
`g.
`
`
`
`(Id. at 00237, 0258-60.) In response, thee Examineer issued neew rejectioons based oon
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Kelleheer (Ex. 1005) in a Febbruary 9, 2007 Officee Action. (IId. at 02700.)
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`KKelleher is directed too load balaancing multtiprocessorr graphics
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`(Kelleher, 1:26-522 (describinng basic prroblem of bbalancing
`
`
`
`
`
`graphic
`
`
`
`
`s processors).) In FIGGS. 2-3, KKelleher disscloses grapaphics systeems with
`
`
`
`
`
`
`
`
`
`
`
`- 10 -
`
`systems.
`
`
`
`the worklooad amongg
`
`
`
`
`
`
`
`U.S.
`
`Patent No
`
`
`
`. 8,933,9455 B2
`
`
`
`
`
`
`multiplee renderingg processorrs. (Id. at 33:20-26.) FFIG. 2 is reeproduced bbelow andd
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`depicts a “graphiccs system wwith two reendering prrocessors.”” (Id. at 2:445-46.)
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`artitioningd, screen pas tile-baseder discloses6, KelleheInn FIGS. 4-
`
`
`
`
`
`
`
`
`
`
`
`
`
`5:64, 8:41-42 (refferring to tiiling patterrn as “checckerboard ppattern”).)
`
`
`
`
`
`
`
`
`
`
`
`
`
`reproduuced above and depiccts partitionning a grapphics mem
`
`
`
`
`
`
`
`
`
`
`
`ory into 166 blocks off
`
`
`
`
`
`pixels (llabeled 0-115) that co
`
`
`
`
`
`
`
`rrespond too locationss of a displlay screen.
`
`
`
` (Id. at 5:119-
`
`
`
`g. (Id. at 4:660-
`
`FIG. 6 is
`
`
`
`
`
`51.) Twwo renderinng processoors (labeledd 0 and 1)
`
`
`
`
`
`
`
`
`
`pattern that repeatts in the hoorizontal annd vertical
`
`
`
`
`
`
`
`
`
`
`
`
`
`are allocatted to the 116 blocks iin a
`
`
`
`directionss. (Id.)
`
`
`
`TTo overcomme Kelleher, the ’9455 patent appplicant ammended thenn-pending
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`claim 1 to includee “a memorry controller in commmunicationn with” at l
`
`
`
`
`
`
`
`
`
`
`
`
`
`s pipeliness. (’945 filee history, 00291.) ’9455 patent appplicant connceded thaat
`
`
`
`
`
`
`
`east two
`
`its own
`
`graphic
`
`
`
`
`
`
`
`
`“Kellehher teaches that it is bbeneficial to provide eeach proceessor with
`
`
`
`
`
`
`
`
`
`
`
`
`
`memoryy chip(s) annd own buus to the meemory chipp(s),” but aargued thatt Kelleher
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`- 11 -
`
`
`
`
`
`U.S. Patent No. 8,933,945 B2
`
`
`does not disclose the a memory controller in communication with two pipelines.
`
`(Id. at 0300-02.) Dr. Fussell explains it would have been nothing more than an
`
`obvious design choice to a POSITA to use a shared memory controller as opposed
`
`to individual memory controllers. (Fussell Decl., ¶ 66.) Nonetheless, the examiner
`
`withdrew the Kelleher-based rejections and applied Perego (Ex. 1006). (’945 file
`
`history, 0333-45.)
`
`The examiner relied on Perego in an Office Action that issued on August 28,
`
`2007. (Id. at 0333-45.) In FIG. 3 of Perego (reproduced below), Perego discloses
`
`“a scalable unified memory architecture 300 that supports parallel processing of
`
`graphical data and/or graphical instructions.” (Perego, 3:61-63.) As shown, Perego
`
`discloses a plurality of rendering engines that share a memory controller. (Id. at
`
`3:65-4:2, 7:35-38 (multiple graphics rendering engines connected to memory
`
`controller); 4:26-36 (graphics rendering engines).) FIG. 5 of Perego (reproduced
`
`below) discloses tile-based, screen partitioning. (Id. at 5:23-50, FIGS 4-5.)
`
`FIG. 5 “illustrates a graphical rendering surface divided into sixteen
`
`different sections of ‘tiles’ (four rows and four column).” (Id. at 5:29-31 (emphasis
`
`added).) “The graphical rendering surface may be stored in, for example, an image
`
`buffer of displayed on a display device.” (Id. at 5:32-33 (emphasis added).) Perego
`
`discloses that the memory controller/graphics controller 310 of FIG. 3 “divide[s]
`
`the processing tasks into different portions” and assigns different rendering engines
`
`
`
`- 12 -
`
`
`
`
`
`U.S.
`
`Patent No
`
`
`
`. 8,933,9455 B2
`
`
`
`
`
`
`(e.g., REE0, RE1, RRE2, and RRE3 of FIGG. 5) “to prrocess diffeerent regioons of the
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`surface simultaneoously.” (Idd. at 5:33-550.)
`
`
`
`
`
`
`
`2.
`
`The ’9455 patent isssued becaause the Booard deterrmined thhat
`
`
`
`
`
`
`
`
`
`
`the examminer did nnot addresss how Pe
`
`rego disclloses a
`
`
`
`memoryy shared ammong pipeelines.
`
`
`
`AAfter the August 28, 22007 Officce Action, tthe ’945 paatent appliicant and thhe
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`examineer exchangged argumeents involvving Peregoo for severral years. (SSee ’945 fifile
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`history, 0345-632.) During tthis period, the ’945 ppatent appplicant madde minor
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`amendmments to then-pendingg claim 1 tto require tthe graphiccs pipeline
`
`
`
`
`
`
`
`
`
`
`
`
`
`s and memmory
`
`
`
`controlller to be onn the same chip (id. aat 0350, 03355, 0514),, and that aa memory iis
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`shared aamong the pipelines ((id. at 057
`1, 576).
`
`
`
`
`
`icant appe
`UUltimately, the ’945 ppatent appl
`
`
`
`
`
`
`
`
`ealed to thee Board in
`
`
`
`early 20111.
`
`
`
`(Id. at 00632-68.) OOn Appeal, the Boardd found thaat the examminer failedd to show tthat
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`Perego discloses tthe limitatiion “a memmory sharedd among thhe at least
`
`
`
`
`
`
`
`
`
`
`
`
`
`two graphhics
`
`
`
`- 13 -
`
`
`
`
`
`U.S. Patent No. 8,933,945 B2
`
`
`pipelines” in system claims 1 and 25 (id. at 0720), which issued as patent claims 1
`
`and 21 (id. at 0737), and the application issued as the ’945 patent.
`
`*
`
`*
`
`*
`
`Thus, the ’945 patent did not issue because it discloses novel and
`
`nonobvious tile-based, screen partitioning. Rather, it issued because the examiner
`
`failed to establish that a simple and obvious structural feature—a memory shared
`
`among pipelines—was known. (Fussell Decl., ¶¶ 69-70.)
`
`IV. Grounds For Standing
`
`Petitioner certifies that the patent for which review is sought is eligible for
`
`inter partes review and that the Petitioner is not barred or estopped from requesting
`
`inter partes review challenging the patent claims on the grounds identified in this
`
`Petition. The required fee is paid via online credit card payment. The Office is
`
`authorized to charge fee deficiencies and credit overpayments to Deposit Acct. No.
`
`19-0036 (Customer ID No. 45324).
`
`V.
`
`Statement of Relief Requested
`
`Petitioner respectfully requests inter partes review and cancelation of the
`
`challenged claims based on the detailed statements presented below.
`
`VI. Claim Construction
`
`In an inter partes review, claim terms in an unexpired patent are given their
`
`broadest reasonable construction in light of the specification of the patent in which
`
`
`
`- 14 -
`
`
`
`
`
`U.S. Patent No. 8,933,945 B2
`
`
`they appear. 37 C.F.R. § 42.100(b). Claim terms are generally given their ordinary
`
`and customary meaning as would be understood by a person of ordinary skill in the
`
`art (“POSITA”) in the context of the entire disclosure. In re Translogic Tech., Inc.,
`
`504 F.3d 1249, 1257 (Fed. Cir. 2007).
`
`A POSITA is a hypothetical person who is “presumed to be aware of all the
`
`pertinent prior art.” Standard Oil Co. v. Am. Cyanamid Co., 774 F.2d 448, 454
`
`(Fed. Cir. 1985). This hypothetical person “is also a person of ordinary creativity,
`
`not an automaton.” KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 421 (2007). With
`
`respect to the ’945 patent, a POSITA would have at least the equivalent of a
`
`Bachelor’s degree in Electrical or Computer Engineering, at least four years of
`
`experience in computer hardware architecture research or development, and a
`
`familiarity with computer graphics. Experience could take the place of some
`
`formal training, as domain knowledge may be learned on the job. This description
`
`is approximate, and a higher level of education or skill might make up for less
`
`experience and vice versa. (Fussell Decl., ¶¶ 35-36.)
`
`A. memory controller
`
`The claims recite the term “memory controller.” In the context of the ’945
`
`patent, a POSITA would have understood this term to mean “logic that transmits
`
`data to and from a memory.” (Fussell Decl., ¶¶ 71-72.)
`
`
`
`- 15 -
`
`
`
`
`
`
`
`U.S. Patent No. 8,933,945 B2
`
`The ’945 patent claims and specification support this construction. Claims 1
`
`and 21 require the memory controller to be on a “chip,” and that the memory
`
`controller is “operative to transfer” pixel data between graphics pipelines and a
`
`memory. The specification, which provides little description of a memory
`
`controller, describes a memory controller as “operative to transmit and receive the
`
`processed pixel data 43-44 from the back end circuitry 39 and 42; transmit and
`
`retrieve pixel data 49 from the graphics memory 48; and in a single circuit
`
`implementation, transmit pixel data 50 for presentation on a suitable display 51.”
`
`(’945 patent, 5:37-44; see also id. at 5:4-7, 5:34-37.) Thus, a “memory controller”
`
`is “logic that transmits data to and from a memory.” (Fussell Decl., ¶¶ 72-76.)
`
`B.
`
`scan converter
`
`Claim 5 recites the term “scan converter.” In the context of the ’945 patent,
`
`a POSITA would have understood this term to mean “logic for identifying the
`
`pixels to be processed.” (Fussell Decl., ¶¶ 77-79.)
`
`The ’945 patent claims and specification support this construction. In the
`
`’945 patent, front-end circuitry generates the pixel data. (Id. at 4:39-42, claim 4.)
`
`The scan converter receives the pixel data and identifies the pixels to be processed
`
`by back-end circuitry. (’945 patent, 4:39-52, claim 5.) For example, discussing
`
`FIGS. 2 and 3, the ’945 patent specification states:
`
`
`
`- 16 -
`
`
`
`
`
`
`
`U.S. Patent No. 8,933,945 B2
`
`The scan converter 37 of the first graphics pipeline 101 receives the
`pixel data 36 and sequentially provides the position (e.g. x, y)
`coordinates 60 in screen space of the pixels to be processed by the
`back end circuitry 39 by determining or identifying those pixels of
`the primitive, for example, the pixels within portions 81-82 of the
`triangle 80 (FIG. 3) that intersect the tile or set of tiles that the back
`end circuitry 39 is responsible for processing.
`(Id. at 4:45-52 (emphasis added).)
`
`The ’945 patent’s description of a scan converter is not consistent with the
`
`ordinary meaning of this term. (Fussell Decl., ¶¶ 80-81.) Applying its ordinary
`
`meaning, a POSITA would have understood a scan converter to be logic used in
`
`the process of generating pixel data. (Id. (citing Foley, 0038 (“primitives such as
`
`lines and polygons are specified in terms of their endpoints (vertices) and must be
`
`scan-converted into their component pixels in the frame buffer”)); Whitman, 0054
`
`(“[e]ach processor scan-converts a single polygon as a task and writes the pixel
`
`value into the scattered frame buffer”); Narayanaswami 1:38-39 (“scan converting
`
`each received graphical object into pixels”), 7:21-22 (“the subobject is then scan
`
`converted into pixels”).) But the ’945 patent expressly states that front-end
`
`circuitry generates the pixel data (’945 patent, 4:39-42, claim 4), not the scan
`
`converter.
`
`“The specification is the ‘single best guide to the meaning of a disputed
`
`term.’” Phillips v. AWH Corp., 415 F.3d 1303, 1320-21 (Fed. Cir. 2005) (int