UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`VOLKSWAGEN GROUP OF AMERICA, INC.,
`Petitioner
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`v.
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`ADVANCED SILICON TECHNOLOGIES, LLC,
`Patent Owner
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`
`Case IPR2016-TBA
`Patent 8,933,945 B2
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`DECLARATION OF DR. DONALD S. FUSSELL
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`Mail Stop “PATENT BOARD”
`Patent Trial and Appeal Board
`U.S. Patent & Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
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`Volkswagen 1003
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`0001
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`

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`U.S. Patent No. 8,933,945 B2
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`I. 
`
`TABLE OF CONTENTS
`QUALIFICATIONS ........................................................................................ 4 
`A.  Education ......................................................................................................... 5 
`B.  Professional Experience .................................................................................. 6 
`II.  MY UNDERSTANDING OF CLAIM CONSTRUCTION ......................... 11 
`III.  MY UNDERSTANDING OF OBVIOUSNESS ........................................... 11 
`IV.  LEVEL OF ORDINARY SKILL IN THE ART ........................................... 13 
`V.  OVERVIEW OF THE ’945 PATENT .......................................................... 14 
`A.  The ’945 patent alleges that conventional strip-based, screen partitioning
`resulted in poor load balance ......................................................................... 14 
`B.  The ’945 patent purports to have invented tile-based, screen partitioning ... 16 
`VI.  BACKGROUND OF THE TECHNOLOGIES DESCRIBED IN THE
`’945 PATENT ................................................................................................ 18 
`A.  Computer Graphics ........................................................................................ 19 
`B.  Miniaturization and Integration of Electronics .............................................. 25 
`C.  Screen Partitioning ......................................................................................... 27 
`1.  Furtner ...................................................................................................... 30 
`2.  Crockett .................................................................................................... 31 
`3.  Foley ......................................................................................................... 33 
`4.  Kelleher .................................................................................................... 34 
`5.  Perego ....................................................................................................... 37 
`VII.  CLAIM CONSTRUCTION .......................................................................... 39 
`A.  “memory controller” ...................................................................................... 39 
`B.  “scan converter” ............................................................................................ 42 
`C.  “graphics pipeline” ........................................................................................ 44 
`VIII.  THE COMBINATION OF NARAYANASWAMI AND GOVE ................ 49 
`A.  Overview of Narayanaswami ........................................................................ 49 
`B.  Overview of Gove .......................................................................................... 53 
`C.  Reasons that a POSITA would have combined Narayanaswami and Gove . 55 
`D.  Claim 1 ........................................................................................................... 59 
`- i -
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`0002
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`U.S. Patent No. 8,933,945 B2
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`1.  Both Narayanaswami and Gove disclose the preamble [1.P]. ................. 60 
`2.  The combination of Narayanaswami and Gove teaches the “at least
`two graphics pipelines” limitation [1.1]. ............................................. 60 
`3.  The combination of Narayanaswami and Gove teaches the “memory
`controller” limitation [1.2]. ................................................................. 71 
`4.  Narayanaswami discloses the “horizontally and vertically repeating
`pattern” limitation [1.3]. ..................................................................... 76 
`E.  Claim 21 ......................................................................................................... 79 
`1.  Both Narayanaswami and Gove disclose the preamble [21.P]. ............... 80 
`2.  The combination of Narayanaswami and Gove teaches “at least two
`graphics pipelines” limitation [21.1]. ................................................. 81 
`3.  Narayanaswami discloses the “horizontally and vertically repeating
`pattern” limitation [21.2] .................................................................... 81 
`4.  Narayanaswami discloses the “NxM” limitation [21.3]. .......................... 82 
`5.  The combination of Narayanaswami and Gove teaches the “memory
`controller” limitation [21.3]. ............................................................... 83 
`F.  Claim 9 ........................................................................................................... 84 
`G.  Claim 10 ......................................................................................................... 84 
`IX.  THE COMBINATION OF NARAYANASWAMI, GOVE, AND
`FOLEY........................................................................................................... 86 
`A.  Claim 2 ........................................................................................................... 86 
`B.  Claim 3 ........................................................................................................... 88 
`C.  Claim 4 ........................................................................................................... 88 
`D.  Claim 6 ........................................................................................................... 91 
`E.  Claim 7 ........................................................................................................... 93 
`THE COMBINATION OF NARAYANASWAMI, GOVE, FOLEY,
`AND KELLEHER ......................................................................................... 94 
`A.  Claim 5 ........................................................................................................... 94 
`B.  Claim 8 ........................................................................................................... 99 
`C.  Claim 11 .......................................................................................................102 
`XI.  CONCLUSION ............................................................................................104 
`
`X. 
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`- ii -
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`0003
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`U.S. Patent No. 8,933,945 B2
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`I, Dr. Donald S. Fussell, declare as follows:
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`1.
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`I have been retained as an expert witness by Sterne, Kessler,
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`Goldstein & Fox PLLC to provide testimony on behalf of Volkswagen Group of
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`America, Inc., for the above-captioned inter partes review proceeding. I
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`understand that this proceeding involves U.S. Patent No. 8,933,945 (“’945
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`patent”), entitled “Dividing Work Among Multiple Graphics Pipelines Using a
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`Super-tiling Technique” by Mark M. Leather and Eric Demers. I understand that
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`the ’945 patent is currently assigned to Advanced Silicon Technologies, LLC
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`(“AST”).
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`2.
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`I understand that the ’945 patent was filed on June 12, 2003, and
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`issued on January 13, 2015. I also understand that the ’945 patent claims priority to
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`a provisional application (60/429,641) that was filed on November 27, 2002. For
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`the purposes of this inter partes review, I assume that the November 27, 2002
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`filing date of the provisional application is the earliest possible priority date of the
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`’945 patent.
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`3.
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`I have reviewed and am familiar with the specification of the ’945
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`patent. I understand that the ’945 patent has been provided as Exhibit 1001. I will
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`cite to the specification using the following format (’945 patent, 1:1-10). This
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`example citation points to the ’945 patent specification at column 1, lines 1-10.
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`- 1 -
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`0004
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`U.S. Patent No. 8,933,945 B2
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`4.
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`I have reviewed and am familiar with the file history of the ’945
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`patent. I understand that the file history has been provided as Exhibit 1002.
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`5.
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`I have also reviewed and am familiar with the following prior art
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`documents:
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` U.S. Patent No. 6,778,177 to Furtner. I understand that Furtner has
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`been provided as Exhibit 1004.
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` U.S. Patent No. 5,794,016 to Kelleher. I understand that Kelleher has
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`been provided as Exhibit 1005.
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` U.S. Patent No. 6,864,896 to Perego. I understand that Perego has been
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`provided as Exhibit 1006.
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` U.S. Patent No. 5,408,606 to Eckart. I understand that Eckart has been
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`provided as Exhibit 1007.
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` U.S. Patent No. 5,757,385 to Narayanaswami et al.
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`(“Narayanaswami”). I understand that Narayanaswami has been
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`provided as Exhibit 1008.
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` U.S. Patent No. 6,070,003 to Gove et al. (“Gove”). I understand that
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`Narayanaswami has been provided as Exhibit 1009.
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`- 2 -
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`0005
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`U.S. Patent No. 8,933,945 B2
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` “Computer Graphics Principles and Practice,” Second Edition in C, by
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`Foley et al. (“Foley”).1 I understand that Foley has been provided as
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`Exhibit 1010.
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` “3D Computer Graphics,” by Alan Watt (“Watt”).2 I understand that
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`Watt has been provided as Exhibit 1011.
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` “Multiprocessor Methods for Computer Graphics Rendering,” by Scott
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`Whitman (“Whitman”). I understand that Whitman has been provided
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`as Exhibit 1012.
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` “Cramming more components onto integrated circuits,” by Gordon
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`Moore (“Moore”). I understand that Moore has been provided as
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`Exhibit 1013.
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` “Miniaturization of electronics and its limits,” by R. W. Keyes
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`(“Keyes”). I understand that Keyes has been provided as Exhibit 1014.
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`1 I am very familiar with Foley. I use it as a supplemental text in the
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`graduate-level computer graphics course that I teach.
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`2 I am very also familiar with Watt. I use it as the main text in the graduate-
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`level computer graphics course that I teach.
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`- 3 -
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`0006
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`U.S. Patent No. 8,933,945 B2
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` TMS320C80 Datasheet (“TMS320C80”). I understand that the
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`TMS320C80 has been provided as Exhibit 1015.
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`6.
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`The ’945 patent “relates to graphics processing circuitry and, more
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`particularly, to dividing graphics processing operations among multiple pipelines.”
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`(’945 patent, 1:21-23.) I am familiar with the technology described in the ’945
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`patent as of its earliest possible priority date (i.e., November 27, 2002).
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`7.
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`I have been asked to provide my technical review, analysis, insights
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`and opinions regarding the ’945 patent and the above-noted references that form
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`the basis for the grounds of unpatentability set forth in the Petition for inter partes
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`Review that this Declaration supports.
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`8.
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`In forming the opinions expressed in this Declaration, I have relied
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`upon my education and experience and the materials listed above, and I have
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`considered and applied the viewpoint of a person of ordinary skill in the art
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`(“POSITA”), as of November 27, 2002.
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`I.
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`QUALIFICATIONS
`9.
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`I have over 38 years of experience in field of computer graphics.
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`Since 1995, I have been the Trammell Crow Regents’ Professor in the Department
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`of Computer Sciences at The University of Texas at Austin (“UT Austin”), where I
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`am also a member of the Department of Electrical and Computer Engineering. I am
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`U.S. Patent No. 8,933,945 B2
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`currently the Director of the Laboratory for Real-time Graphics and Parallel
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`Systems at UT Austin.
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`10. As I will describe in more detail below, I have extensive experience in
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`both academia and industry in computer graphics, computer hardware architecture,
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`and computer software development. I am very familiar with the original assignee
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`of the ’945 patent—ATI Technologies, ULC, as well as other companies that focus
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`on computer graphics, such as NVIDIA Corporation. Indeed, many of the Ph.D.
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`candidates that I have advised are working in the graphics industry.
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`11.
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`Before describing my professional experience, I will briefly discuss
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`my formal education.
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`A. Education
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`12.
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`In 1973, I received a BA in Mathematics and Social Science from
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`Dartmouth College.
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`13.
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`In 1977, I received an MS degree in Computer Science (Mathematical
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`Science) from the University of Texas at Dallas (“UT Dallas”).
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`14.
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`In 1980, I received a Ph.D. in Computer Science (Mathematical
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`Science) from the University of Texas at Dallas.
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`15.
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`In my studies at UT Dallas, I took courses on Digital Logic Design
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`and on Microprocessor-based Systems, and as a Research Assistant, I designed and
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`0008
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`U.S. Patent No. 8,933,945 B2
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`built both the hardware and software for one of the world’s earliest experimental
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`artificial reality systems. As a result of this early experience, I have always viewed
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`computer systems design from the point of view of the interaction of hardware and
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`software rather than concentrating only on one or the other.
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`16. My formal education in mathematics and computer science provides a
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`technical foundation for work in field of computer graphics. In describing my
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`professional experience below, I focus on the activities and technologies that are
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`most closely related to this proceeding. My Curriculum Vitae, which is attached as
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`Appendix A, contains further details on my education, experience, publications,
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`and other qualifications to render this opinion as an expert.
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`B. Professional Experience
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`17.
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`I have been a professor at UT Austin since 1980. From 1980-1986, I
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`was an Assistant Professor in the Department of Computer Sciences. From 1986-
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`1994, I was an Associate Professor in the Department of Computer Sciences. And
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`since 1995, I have been the Trammell Crow Regents’ Professor in the Department
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`of Computer Sciences. I am also a member of the Department of Electrical and
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`Computer Engineering at UT Austin. And, I am currently the Director of the
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`Laboratory for Real-time Graphics and Parallel Systems at UT Austin.
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`18. At UT Austin, I have taught and continue to teach graduate and
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`undergraduate courses in computer graphics, computer game technology, computer
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`- 6 -
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`0009
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`U.S. Patent No. 8,933,945 B2
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`organization and architecture, computer systems architecture, and computer
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`organization and programming.
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`19.
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`For example, I taught CS354 – Computer Graphics in the Fall 2015
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`semester. This undergraduate-level course is an introductory course on the major
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`topics in the areas of image synthesis, interactive techniques, geometric modeling,
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`and computer-based animation. It covers numerous topics in computer graphics,
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`including OpenGL programming, the principles of operation of raster graphics
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`systems, graphics processing operations (e.g., sampling and antialiasing,
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`coordinate transformation techniques, hidden surface removal, shading techniques,
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`etc.), basic animation, as well as other topics.
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`20. As another example, I am teaching CS384G – Computer Graphics in
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`the Spring 2016 semester. This is a graduate-level course that covers numerous
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`topics in computer graphics, including (but not limited to): displays and frame
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`buffers; sampling theory and antialiasing; image processing; shading; ray tracing;
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`texture mapping; OpenGL and the OpenGL graphics pipeline; and graphics
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`hardware. As I mentioned above, I use Watt as the main text in this course, and
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`Foley as a supplemental text.
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`21. As a Professor, I also perform research. My research is focused on
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`computer graphics, computer architecture, computer systems, and computer game
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`0010
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`U.S. Patent No. 8,933,945 B2
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`technology. My research often leads to publications. My Curriculum Vitae, which
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`is attached as Appendix A, lists over 100 published papers that I have authored or
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`co-authored.
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`22.
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`Shortly after my arrival at UT Austin in 1980, I started the first
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`research and teaching program on very large scale integration (“VLSI”) system
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`design at the university. I developed a popular course on VLSI design that was
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`taken by many students in both the CS and ECE departments. I supervised a
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`number of Masters and Ph.D. students in the area, both in ECE and CS, and was
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`given an appointment in the ECE department to facilitate these efforts. We
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`designed and fabricated a number of chips as part of the teaching effort, and
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`published a number of papers on the design and analysis of VLSI systems in the
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`research effort (Vita: Conference papers 5-22 (except 7), 24, 25, 27, 30, 33-38
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`Journals: 3, 6, 7, 9, 12-14, 16-18, 20, 21). Conference paper 6 (“A VLSI-oriented
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`Architecture for Real-time Raster Display of Shaded Polygons”), in particular, was
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`an early proposal for a parallel graphics architecture. I also led the first
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`microprocessor design research effort at the university, which culminated in an
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`early general-purpose multithreaded processor, described in Vita conference paper
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`34. Multithreading is now a key feature of modern GPUs. More recently, I have
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`been involved in research aimed at improving memory systems in GPUs (Vita
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`conference papers 89, 90).
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`U.S. Patent No. 8,933,945 B2
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`23.
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`In addition to my academic and research experience, I served as a
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`technical consultant for many different companies, including: Austin Ventures,
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`Inc.; Motorola, Inc.; Cirrus Logic, Inc.; IBM Corporation; Ross Technology, Inc.;
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`AT&T Bell Laboratories; McGinnis, Lockridge and Kilgore; Bausch and Lomb;
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`and V-R Information Systems. I have also worked in research and development for
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`two startup companies, including founding Infovision, Inc., a startup company
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`directed toward developing turnkey interactive CAD systems, and working as
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`Chief Science Officer for Matrix.Net, Inc., an Internet infrastructure startup
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`company.
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`24.
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`In these positions, I have worked extensively with the design,
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`development, and evaluation of computer graphics software and systems. For
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`example, I have evaluated industrial designs for high-performance graphics display
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`subsystems and early display architectures for commodity computers. Below, I list
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`a few examples of the industry experiences that I gained in computer graphics in
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`the late 1980s and 1990s—the time period leading up to the filing of the ’945
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`patent.
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`25.
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`In 1994 I was contracted by Cirrus Logic to evaluate one of the first
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`commodity 3-D graphics accelerators for PCs. This chip had been designed by an
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`Austin-based startup (Ausgraph) and a prototype had been demonstrated at the
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`Consumer Electronics Show. At the time, Cirrus was the largest volume supplier of
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`U.S. Patent No. 8,933,945 B2
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`2D graphics accelerators for PCs and was contemplating the purchase of Ausgraph
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`to jump start a move into the then-nonexistent 3D PC accelerator market. Based in
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`part on my evaluation, the purchase was made and Ausgraph became Cirrus Logic
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`3D division. After much evolution, this group was sold to 3DFX and then to
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`NVIDIA, and is the distant ancestor of the NVIDIA Austin office.
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`26. As a visiting researcher at Bell Laboratories, I worked with several
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`members of technical staff on the architecture of a high-performance parallel
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`machine for real-time interactive display of solid models. Such models differ from
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`the more common surface models used in computer graphics in that the objects are
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`modeled as solid objects. As a result, they can be modified in ways more similar to
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`real world objects, for example by having holes drilled through them. Our machine
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`was designed to allow these objects to be moved and to interact with each other
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`and the viewer in real time and thus did not simply involve real time display.
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`27. My Curriculum Vitae (attached as Appendix A) contains further
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`details on my education, experience, publications, and other qualifications to
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`render this opinion as an expert. My work on this case is being billed at a rate of
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`$500.00 per hour, with reimbursement for actual expenses. My compensation is
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`not contingent upon the outcome of this inter partes review.
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`0013
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`U.S. Patent No. 8,933,945 B2
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`II. MY UNDERSTANDING OF CLAIM CONSTRUCTION
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`28.
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`I understand that, during an inter partes review, claims are to be given
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`their broadest reasonable construction in light of the specification as would be read
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`by a person of ordinary skill in the relevant art.
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`III. MY UNDERSTANDING OF OBVIOUSNESS
`29.
`I am not a lawyer and will not provide any legal opinions. Although I
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`am not a lawyer, I have been advised certain legal standards are to be applied by
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`technical experts in forming opinions regarding meaning and validity of patent
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`claims.
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`30.
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`I understand that a patent claim is invalid if the claimed invention
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`would have been obvious to a person of ordinary skill in the field at the time of the
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`purported invention, which is often considered the time the application was filed.
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`This means that even if all of the requirements of the claim cannot be found in a
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`single prior art reference that would anticipate the claim, the claim can still be
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`invalid.
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`31. As part of this inquiry, I have been asked to consider the level of
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`ordinary skill in the field that someone would have had at the time the claimed
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`invention was made. In deciding the level of ordinary skill, I considered the
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`following:
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`- 11 -
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`0014
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` the levels of education and experience of persons working in the field;
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`U.S. Patent No. 8,933,945 B2
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` the types of problems encountered in the field; and
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` the sophistication of the technology.
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`32.
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`To obtain a patent, a claimed invention must have, as of the priority
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`date, been nonobvious in view of the prior art in the field. I understand that an
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`invention is obvious when the differences between the subject matter sought to be
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`patented and the prior art are such that the subject matter as a whole would have
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`been obvious at the time of the invention to a person having ordinary skill in the
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`art.
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`33.
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`I understand that to prove that prior art or a combination of prior art
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`renders a patent obvious, it is necessary to (1) identify the particular references
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`that, singly or in combination, make the patent obvious; (2) specifically identify
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`which elements of the patent claim appear in each of the asserted references; and
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`(3) explain how the prior art references could have been combined in order to
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`create the inventions claimed in the asserted claim.
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`34.
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`I understand that certain objective indicia can be important evidence
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`regarding whether a patent is obvious or nonobvious. Such indicia include:
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`commercial success of products covered by the patent claims; a long-felt need for
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`the invention; failed attempts by others to make the invention; copying of the
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`U.S. Patent No. 8,933,945 B2
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`invention by others in the field; unexpected results achieved by the invention as
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`compared to the closest prior art; praise of the invention by the infringer or others
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`in the field; the taking of licenses under the patent by others; expressions of
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`surprise by experts and those skilled in the art at the making of the invention; and
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`the patentee proceeded contrary to the accepted wisdom of the prior art.
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`IV. LEVEL OF ORDINARY SKILL IN THE ART
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`35. A person of ordinary skill in the art (“POSITA”) at the time of the
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`earliest possible priority date of the ’945 patent (i.e., November 27, 2002) would
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`have at least the equivalent of a Bachelor of Science (“B.S.”) degree in Electrical
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`or Computer Engineering, at least four years of experience in the field of computer
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`hardware architecture research or development, and a familiarity with computer
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`graphics. Experience could take the place of some formal training, as domain
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`knowledge may be learned on the job. This description is approximate, and a
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`higher level of education or skill might make up for less experience and vice versa.
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`36.
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`I am well qualified to determine the level of ordinary skill in the art.
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`First, I am personally very familiar with the technology of the ’945 patent in the
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`November 2002 timeframe. By 2002, I had completed my formal education and
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`had been working in academia and as an industry consultant for more than 20
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`years. As a Professor, I have supervised, advised, and taught individuals at all
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`0016
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`U.S. Patent No. 8,933,945 B2
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`levels of training in the relevant field. And as a technical consultant, I have worked
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`with individuals in industry at all levels of training in the relevant field.
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`V. OVERVIEW OF THE ’945 PATENT
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`A. The ’945 patent alleges that conventional strip-based, screen
`partitioning resulted in poor load balance
`
`37.
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`The ’945 patent “relates to graphics processing circuitry and, more
`
`particularly, to dividing graphics processing operations among multiple pipelines.”
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`(’945 patent, 1:21-23.) It concedes that conventional “graphics processing systems
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`typically include a host processor, graphics (including video) processing circuitry,
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`memory (e.g. frame buffer), and one or more display devices.” (Id. at 1:26-30.)
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`The graphics processing circuitry generates pixel data, which is presented as an
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`object or a scene on the display screen. (Id. at 1:26-43.) This “pixel data is
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`typically stored in the frame buffer in a manner that corresponds to the pixels
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`location on the display device.” (Id. at 1:41-43.)
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`38.
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`The ’945 patent concedes that prior art graphics processing systems
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`typically divided the processing workload among several graphics processing
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`circuits to decrease processing time. (Id. at 1:44-60, 2:5-14.) One conventional
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`technique partitioned the display screen into horizontal or vertical strips (“strip-
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`based, screen partitioning”), and assigned different graphics processing circuits to
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`generate the pixels in different strips. (Id.) But the ’945 patent asserts that strip-
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`0017
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`U.S. Patent No. 8,933,945 B2
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`based, screen partitioning suffered from load balance problems. (Id. at 2:15-26.)
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`That is, the processing workload was not always evenly distributed among the
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`circuits. (Id.)
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`39.
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`FIG. 1 of the ’945 patent (reproduced below) illustrates a
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`conventional strip-based, screen partitioning technique. Here, the display screen is
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`partitioned into a series of vertical strips. (’945 patent, 1:44-51.) Different graphics
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`processing circuits are responsible for processing different strips. (Id. at 2:5-14.)
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`“[F]or example, one graphics processing circuit is responsible for one vertical strip
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`(e.g. 13) of the frame while another graphics processing circuit is responsible for
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`another vertical strip (e.g. 14) of the frame.” (Id.)
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`
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`- 15 -
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`0018
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`U.S. Patent No. 8,933,945 B2
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`40.
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`The ’945 patent alleges that this screen partitioning technique resulted
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`in a poor load balance “when all of the primitives 20-23 of a particular object or
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`scene are located in one strip (e.g. strip 13 [of FIG. 1]).” (Id. at 2:15-16.) “When
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`this occurs, only the graphics processing circuit responsible [for] strip 13 is
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`actively processing primitives; the remaining graphics processing circuits are idle.”
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`(Id. at 2:19-26.) According to the ’945 patent, “[t]his results in a significant waste
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`of processing resources as at most only half of the graphics processing circuits are
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`operating. Consequently, graphics processing system performance is decreased as
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`the system is only operating at a maximum of fifty percent capacity.” (Id.) The
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`’945 patent thus sought to overcome this load balancing problem that it associates
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`with strip-based, screen partitioning.
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`B. The ’945 patent purports to have invented tile-based, screen
`partitioning
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`41.
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`The ’945 patent purports to have invented tile-based, screen
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`partitioning, which allegedly achieves better load balance than the prior art strip-
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`based, screen partitioning. (’945 patent, 3:21-31.) As shown in FIGS. 2 and 3 of
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`the ’945 patent, the specification describes a graphics processing circuit (labeled
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`“34”) that includes at least two graphics pipelines (labeled “101” and “102”) and a
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`memory controller (labeled “46”) that couples the pipelines to a graphics memory
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`or frame buffer (labeled “48”). (Id. at 3:21-31; 4:5-12, 5:37-65, FIG. 2.) FIG. 2 is
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`U.S. Patent No. 8,933,945 B2
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`reproduced in-part and annotated below. FIG. 3 is reproduced and annotated
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`below.
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`FIG. 2 (in-part, annotated)
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`FIG. 3 (annotated)
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`42.
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`FIG. 3 of the ’945 patent depicts the frame buffer. (Id. at 5:45-65.) It
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`is partitioned into regions or tiles, which correspond to regions of the display
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`screen. (Id.) The graphics pipelines are assigned to process the graphics data in
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`certain tiles—the pipeline labeled “101” processes the graphics data in the “A”
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`tiles (shown in red); the pipeline labeled “102” processes the data in the “B” tiles
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`(shown in blue). (Id.) As shown by the color coding above, this assignment of
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`pipelines to tiles forms a repeating tile pattern. (Id.) According to the ’945 patent,
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`0020
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`U.S. Patent No. 8,933,945 B2
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`this tiling technique allegedly achieves better load balance than prior art
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`techniques, such as the strip-based, screen partitioning. (Id. at 1:44-2:26, 3:21-31.)
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`VI. BACKGROUND OF THE TECHNOLOGIES DESCRIBED IN THE
`’945 PATENT
`43.
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`The inventors of the ’945 patent did not invent tile-based, screen
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`partitioning. Nor did they invent the concept of load balancing among graphics
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`pipelines. Instead, the graphics processing circuitry and techniques described in the
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`’945 patent rely on elements and methods that were well known long before
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`November 2002.
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`44.
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`To begin with, the ’945 patent concedes that conventional “graphics
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`processing systems typically include a host processor, graphics (including video)
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`processing circuitry, memory (e.g. frame buffer), and one or more display
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`devices.” (’945 patent, 1:26-30.) It also admits that strip-based, screen partitioning
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`was known. (1:44-60, 2:5-26.) As I discuss in more detail below, at the time of the
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`alleged invention, tile-based, screen partitioning was a well-known and obvious
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`alternative to of strip-based, screen partitioning. Indeed, I note that several
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`references cited during the prosecution of the ’945 patent teach tile-based, screen
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`partitioning in a graphics processing system.
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`45.
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`Thus, the ’945 patent relies on a variety of known graphics processing
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`techniques, structures, and/or methods. Below, I provide a general overview of
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`U.S. Patent No. 8,933,945 B2
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`computer graphics and the graphics pipeline at or before the time of the alleged
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`invention, and then discuss screen partitioning and load balancing at or before the
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`time of the alleged invention (including several references that were cited or
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`applied during the ’945 patent’s prosecution).
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`A. Computer Graphics
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`46.
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`In general, computer graphics is concerned with displaying
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`information from an application in graphical form on a computer or display. In the
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`text “Computer Graphics Principles and Practice,” Foley et al. (which I’ll just
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`refer to as “Foley”) explained that “[c]omputer graphics concerns the pictorial
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`synthesis of real or imaginary objects from their computer-based models . . . .”
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`(Foley, 0026; see also id. at 0027-32 (describing advantages and representative
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`uses of computer graphics).) Similarly Watt, in his text “3D Computer Graphics,”
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`described computer graphics as “the process involved in converting a mathematical
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`or geometric description of an object – a computer graphics model – into a
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`visualization – a two-dimensional projection – that simulates the appearance of a
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`real object.” (Watt, 0016.)
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`47.
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`Fig. 1.5 of Foley, which I reproduced below, illustrates a conceptual
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`frame work for interactive graphics. (Foley, 0041; see also Watt, 0017 (depicting a
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`similar graphics system).) The application model includes information that can be
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`displayed graphically. (Foley, 0041.) The application program, which in my
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`U.S. Patent No. 8,933,945 B2
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`experience is typically executing on a central processing unit (CPU), reads
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`information from the application model and provides directives to the graphics
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`system, which processes the information and updates the display. (Id.) The purpose
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`of the graphics system is to offload graphical operations from the application
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`program. (Id.)
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`(Foley at 0041.)
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`48.
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`T