`Interface Specification
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`Revision 1.0
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`Intel Corporation
`
`July 31, 1996
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`Intel may have patents and/or patent applications related to the Various Accelerated Graphics
`Port (AGP or A.G.P).
`interfaces described in the Accelerated Graphics Port Interface
`Specification. A reciprocal, royalty-free license to the electrical interfaces and bus protocols
`descfibed in, and required by, the Accelerated Graphics Port Interface Specification Revision
`1.0 is available from Intel.
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`Page 1 01161
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`Petitioners HTC & LG — Exhibit 1024, p. 1
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`Petitioners HTC & LG - Exhibit 1024, p. 1
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`Revision 1.0
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`A.G.P. Interface Specification
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`Accelerated Graphics Port Interface Specification
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`Copyright © Intel Corporation 1996
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`All rights reserved.
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`THIS SPECIFICATION IS PROVIDED “AS IS” VVITH NO WARRANTIES WHATSOEVER INCLUDING ANY WARRANTY OF
`
`MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE OR ANY WARRANTY OTHERVVISE ARISING OUT OF
`ANY PROPOSAL, SPECIFICATION , OR SAMPLE. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
`TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED OR INTENDED HEREBY.
`
`INTEL DISCLAIMS ALL LIABILITY, INCLUDING LIABILITY FOR INFRINGEMENT OF ANY PROPRIETARY RIGHTS,
`RELATING TO USE OF INFORMATION IN THIS SPECIFICATION. INTEL DOES NOT WARRANT OR REPRESENT THAT
`SUCH USE WILL NOT INFRINGE SUCH RIGHTS,
`
`*TH]RD-PARTY BRANDS AND NAMES ARE THE PROPERTY OF THEIR RESPECTIVE OWNERS,
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`A.G.P. Interface Specification
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`Revision 1.0
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`Table of Contents
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`1. INTRODUCTION....................................................................................................................................... 1
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`1.1 MOTIVATION. ............................................................................................................................................ .. 1
`1.2 RELATIONSHIP TO PCI ............................................................................................................................... .. 1
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`2. ARCHITECTURAL CONTEXT AND SCOPE........................................................................................ 3
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`2.1 TWO USAGE MODELS: “EXECUTE” & “DMA”........................................................................................... .. 3
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`2.2 A.G.P. QUEUING MODELS ......................................................................................................................... .. 4
`2.3 PERFORMANCE CONSIDERATIONS .............................................................................................................. .. 6
`2.4 PLATFORM DEPENDENCIES ........................................................................................................................ .. 6
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`3. SIGNALS AND PROTOCOL SPECIFICATION .................................................................................... 9
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`3,1 A,G_P_ OPERATION OVERVIEW .................................................................................................................. .. 9
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`3.1.1 Pipeline Operation ......................................................................................................................... .. 9
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`3.1.2 Addressing Modes and Bus Operations ....................................................................................... .. 11
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`3.1.3 Address Demultiplexing Option................................................................................................... .. 13
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`3.2 ACCESS ORDERING RULES & FLOW CONTROL......................................................................................... .. 16
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`3.2.1 Ordering Rules and Implications ................................................................................................. .. 16
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`3.2.2 Deadlock Avoidance ................................................................................................................... .. 19
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`3.2.3 Flush and Fence Commands ......................................................................................................... .. 19
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`3.2.4 Access Request Priority............................................................................................................... .. 20
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`3.2.5 Flow Control ............................................................................................................................... .. 21
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`3.2.5.1 Introduction ........................................................................................................................... ..21
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`3.2.5.2 Read Flow Control ............................................................................................................... .. 22
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`3.2.5.3 Write Data Flow Control ...................................................................................................... .. 25
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`3.2.5.4 1 and 2 Clock Rule for IRDY# and TRDY# ......................................................................... .. 27
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`3.2.5.5 Other Flow Control Rules ..................................................................................................... .. 27
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`3.2.6 Source Throttling Address Flow Control..................................................................................... .. 27
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`3.3 PIN DESCRIPTION .................................................................................................................................... .. 28
`3.4 A.G.P. SEMANTICS OF PCI SIGNAmS ........................................................................................................ .. 31
`3.5 BUS TRANSACTIONS ................................................................................................................................ .. 33
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`3.5.1 Address Transactions .................................................................................................................. .. 33
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`3.5.1.1 AD Bus ................................................................................................................................. ..33
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`3.5.1.2 SBA Port............................................................................................................................... ..35
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`3.5.2 Basic Data Transactions .............................................................................................................. .. 36
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`3.5.2.1 1x Data Transfers .................................................................................................................. .. 37
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`3.5.2.2 2x Data Transfers .................................................................................................................. .. 39
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`3.5.3 Flow Control ............................................................................................................................... .. 42
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`3.5.3.1 Initial Data Block.................................................................................................................. .. 42
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`3.5.3.2 Subsequent Data Block ......................................................................................................... .. 44
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`3.6 ARBITRATION SIGNALING RULES ............................................................................................................. .. 51
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`3.6.1 Introduction .................................................................................................................................. .. 51
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`3.6.2 A.G.P. Compliant Master’s REQ# .............................................................................................. .. 52
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`3.6.3 GNT# and ST[2::0] .................................................................................................................... .. 53
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`3.6.4 GNT# for Single Transactions .................................................................................................... .. 53
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`3.6.5 GNT# Pipelining ......................................................................................................................... .. 54
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`3.6.6 GNT# Interaction with RBF# ...................................................................................................... .. 61
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`3 .7 A.G.P. SEQUENCER STATE MACHINE EQUATIONS ................................................................................... .. 61
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`3.7.1 Error Reporting............................................................................................................................ .. 62
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`4. ELECTRICAL SPECIFICATION........................................................................................................... 63
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`4.1 OVERVIEW ............................................................................................................................................... .. 63
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`4.1.1 Introduction .................................................................................................................................. .. 63
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`4.1.2 1X Transfer Mode Operation....................................................................................................... .. 63
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`4.1.3 2X Transfer Mode Operation....................................................................................................... .. 63
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`4.1.3.1 Transmit/Receive Outer Loop ............................................................................................... .. 65
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`4.1.3.2 Transmit to Receive Inner loop............................................................................................. .. 65
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`4.1.3.3 Transmit Outer to Inner Loop ................................................................................................ .. 66
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`4.1.3.4 Receive Inner to Outer Loop ................................................................................................. .. 66
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`4.1.3.5 SB_STB Synchronization...................................................................................................... .. 68
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`4.2 COMPONENT SPECIFICATION ................................................................................................................... .. 69
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`4.2.1 DC SPECIFICATIONS................................................................................................................ .. 69
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`4.2.1.1 A.G.P. 1X Mode DC Specification....................................................................................... .. 70
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`4.2.1.2 A.G.P. 2X Mode DC Specification....................................................................................... .. 70
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`4.2.2 AC Timings .................................................................................................................................. .. 71
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`4.2.2.1 A.G.P. 1X Timing Parameters .............................................................................................. .. 72
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`4.2.2.2 A.G.P. 2X AC Timing Parameters ........................................................................................ .. 73
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`4.2.2.3 Measurement and Test Conditions ........................................................................................ .. 76
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`4.2.3 Signal Integrity Requirement ........................................................................................................ .. 78
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`4.2.4 Driver Characteristics ................................................................................................................. .. 78
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`4.2.5 Receiver Characteristics.............................................................................................................. .. 79
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`4.2.6 Maximum AC Ratings and Device Protection .............................................................................. .. 80
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`4.2.7 Component Pinout Recommendations .......................................................................................... .. 81
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`4.3 MOTHERBOARD SPECIFICATION ............................................................................................................... .. 82
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`4.3.1 System Timing Budget ................................................................................................................. .. 82
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`4.3.2 Clock Skew.................................................................................................................................. .. 83
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`4.3.3 Reset ............................................................................................................................................ .. 84
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`4.3.4 Interconnect Delay ....................................................................................................................... .. 85
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`4.3.5 Physical Requirements ................................................................................................................. .. 85
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`4.3.5.1 Interface Signaling ................................................................................................................ .. 85
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`4.3.5.2 Pullups .................................................................................................................................. .. 85
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`4.3.5.3 Signal Routing and Layout .................................................................................................... .. 86
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`4.3.5.4 Impedances ........................................................................................................................... .. 86
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`4.3.5.5 Vref Generation .................................................................................................................... .. 86
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`4.3.5.6 Crosstalk Consideration........................................................................................................ .. 86
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`4.3.5.7 Line Tennination................................................................................................................... .. 87
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`4.4 ADD-IN CARD SPECIFICATION ................................................................................................................. .. 87
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`4.4.1 Clock Skew.................................................................................................................................. .. 87
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`4.4.2 Interconnect Delay ....................................................................................................................... .. 87
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`4.4.3 Physical Requirements ................................................................................................................. .. 88
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`4.4.3.1 Pin Assignment ..................................................................................................................... .. 88
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`4.4.3.2 Signal Routing and Layout .................................................................................................... .. 88
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`4.4.3.3 Impedances ........................................................................................................................... .. 88
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`4.4.3.4 Vref Generation .................................................................................................................... .. 88
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`4.4.3.5 Power supply delivery.......................................................................................................... .. 88
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`5. MECHANICAL SPECIFICATION ......................................................................................................... 89
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`5.1 INTRODUCTION ........................................................................................................................................ .. 89
`5.2 EXPANSION CARD PHYSICAL DIMENSIONS AND TOLERANCES ................................................................. .. 89
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`5.3 CONNECTOR: ........................................................................................................................................... .. 91
`5.4 CONNECTOR PHYSICAL DESCRIPTION...................................................................................................... .. 92
`5.5 PLANAR IMPLEMENTATION ...................................................................................................................... .. 93
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`5.5.1 ATX Planar Implementation ........................................................................................................ .. 93
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`5.5.2 Low Profile Planar Implementation ............................................................................................. .. 94
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`5.5.3 Pin List......................................................................................................................................... .. 95
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`6. SYSTEM CONFIGURATION AND A.G.P. INITIALIZATION........................................................... 97
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`6.1 POST-Tl1\/[E INITIALIZATION ..................................................................................................................... .. 97
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`6.1.1 A.G.P. Compliant Master Devices ............................................................................................... .. 97
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`6.1.2 A.G.P. Compliant Target Devices ............................................................................................... .. 97
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`6.1.3 Boot-time VGA Display Device(s) .............................................................................................. .. 98
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`6.1.4 Operating System Initialization .................................................................................................... .. 98
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`6.1.5 PCI Status Register .................................................................................................................... .. 100
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`6.1.6 Capabilities Pointer - (offset 34h) ............................................................................................. .. 100
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`6.1.7 Capability Identifier Register (Offset = CAP_PTR) ................................................................. .. 100
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`6.1.8 A.G.P. status register (Offset CAP_PTR + 4) ............................................................................. .. 101
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`6.1.9 A.G.P. command register - (offset CAP_PTR + 8) ................................................................... .. 102
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`7. APPENDIX A .......................................................................................................................................... 103
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`8. APPENDIX B .......................................................................................................................................... 105
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`A.G.P. Interface Specification
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`Revision 1.0
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`List of Figures
`FIGURE 1-1 SYSTEM BLOCK DIAGRAM: A.G.P. AND PCI RELATIONSIHP ......................................................... .. 2
`FIGURE 2-1 GRAPHICS ADDRESS RE-MAPPING FUNCTION................................................................................ .. 4
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`FIGURE 2-2 A.G.P. ACCESS QUEUING MODEL ................................................................................................. .. 5
`FIGURE 2-3 DIFFERENT CORE LOGIC ARCHITECTURES ..................................................................................... .. 7
`FIGURE 3-1 BASIC A.G.P. PIPELINE CONCEPT. .............................................................................................. .. 10
`FIGURE 3-2 A.G.P./PCI OPERATIONAL STATES.............................................................................................. .. 10
`FIGURE 3-3 LAYOUT OF AN A.G.P. ACCESS REQUEST ................................................................................... .. 12
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`FIGURE 3-4 MAXIMUM NUMBER OF GNT#S QUEUED BEFORE THE ASSERTION OF RBF# ................................. .. 24
`FIGURE 3-5 MAXIMUM DELAY BY MASTER ON WRITE DATA .......................................................................... .. 26
`FIGURE 3-6 WRITE DATA WITH ONE TP. ........................................................................................................ .. 27
`FIGURE 3-7 SINGLE ADDRESS - NO DELAY BY MASTER................................................................................. .. 34
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`FIGURE 3-8 MULTIPLE ADDRESSES ENQUEUED, MAXJMUM DELAY BY MASTER ............................................. .. 3 5
`FIGURE 3-9 1X SIDEBAND ADDRESSING......................................................................................................... .. 36
`FIGURE 3-10 2X SIDE BAND ADDRESSING ...................................................................................................... .. 36
`FIGURE 3-1 1 MINIMUM DELAY BY TARGET OF READ TRANSACTION.............................................................. .. 37
`FIGURE 3-12 MINIMUM DELAY ON BACK TO BACK READ DATA.................................................................... .. 38
`FIGURE 3-13 MASTER DOES NOT DELAY PROVIDING WRITE DATA ................................................................. .. 38
`FIGURE 3-14 BACK To BACK WRITE DATA TRANSFERS - NO DELAYS ........................................................... .. 39
`FIGURE 3-15 2X READ DATA NO DELAY ........................................................................................................ .. 40
`FIGURE 3- 16 2X BACK TO BACK READ DATA - N0 DELAY ............................................................................ .. 40
`FIGURE 3-17 2X BASIC WRIIENO DELAY ...................................................................................................... .. 41
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`FIGURE 3-18 QUADWORD WRITES BACK TO BACK - N0 DELAYS.................................................................. .. 41
`FIGURE 3-19 MASTER'S DATA BUFFER IS FULL - NO DELAY ON READ DATA ................................................. .. 42
`FIGURE 3-20 HIGH PRORITY READ DATA RETURNED WHILE RBF# ASSERTED .............................................. .. 42
`FIGURE 3-21 2X READ DATA WITH RBF# ASSERTED...................................................................................... .. 43
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`FIGURE 3-22 THROTTLE POINT FOR SUBSEQUENT DATA BLOCK - N0 DELAY ................................................ .. 44
`FIGURE 3-23 MASTER DELAYS SUBSEQUENT DATA BLOCK ........................................................................... .. 44
`FIGURE 3-24 WRITE WITH SUBSEQUENT BLOCK - NO DELAY......................................................................... .. 45
`FIGURE 3-25 TARGET DELAYS SUBSEQUENT WRITE DATA BLOCK ................................................................. .. 46
`FIGURE 3-26 EARLIEST READ DATA RETURNED AFTER A REQUEST ................................................................. .. 46
`FIGURE 3-27 REQUEST FOLLOWED BY WRITE AND THEN A READ.................................................................... .. 47
`FIGURE 3-28 REQUEST FOLLOWED BY READ DATA NO DELAY BY TARGET. .................................................... .. 48
`FIGURE 3-29 REQUEST FOLLOWED BY WRITE - NO AD TURN AROUND .......................................................... .. 49
`FIGURE 3-30 BASIC PCI TRANSACTION ON A.G.P......................................................................................... .. 50
`FIGURE 3-31 PCI TRANSACTION BETWEEN A.G.P. REQUEST AND DATA ....................................................... .. 51
`FIGURE 3-32 WRITE DATA FOLLOWED BY READ ............................................................................................ .. 54
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`FIGURE 3-33 GNT# ASSERTION FOR 16, 8, AND THEN 16 BYTE READ TRANSFERS ......................................... .. 57
`FIGURE 3-34 GNT# ASSERTION FOR NEXT READ DATA AFTER LONG DATA TRANSFER .................................. .. 57
`FIGURE 3-35 GNT# ASSERTION FOR BACK TO BACK WRITE DATA TRANSFERS ............................................. .. 58
`FIGURE 3-36 BACK TO BACK GNT# WITH DELAY ON INITIAL TRANSFER ...................................................... .. 59
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`FIGURE 3-37 PIPELINED GNT#S - READ AND WRITES (PART 1) ...................................................................... .. 60
`FIGURE 3-3 8 PIPELINED GNT#S - READ AND WRITES (PART 2) ...................................................................... .. 60
`FIGURE 3-39 LP GNT# PIPELINING STOPPED WHILE RBF# IS ASSERTED ..................................................... .. 61
`FIGURE 4-1 2X MODE TIME DOMAINS........................................................................................................... .. 64
`FIGURE 4-2 TRANSMIT STROBE/DATA TIMINGS ............................................................................................. .. 65
`FIGURE 4-3 RECEIVE STROBE/DATA TIMINGS ................................................................................................ .. 65
`FIGURE 4-4 TRANSMIT STROBE/CLOCK TIMINGS ........................................................................................... .. 66
`FIGURE 4-5 COMPOSITE TRANSMIT TIMINGS ................................................................................................. .. 66
`FIGURE 4-6 RECEIVER INNER TO OUTER LOOP TRANSFER TIMING ................................................................. .. 67
`FIGURE 4-7 COMPOSITE RECEIVE TIMINGS .................................................................................................... .. 68
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`FIGURE 4-8 SB_STB SYNCHRONIZATION PROTOCOL.................................................................................... .. 69
`FIGURE 4-9 A.G.P. 1X TIMING DIAGRAM ...................................................................................................... .. 73
`FIGURE 4-10 A.G.P. 133 TIMING DIAGRAM................................................................................................... .. 75
`FIGURE 4-1 1 STROBE/DATA TURNAROUND TIMINGS ..................................................................................... .. 75
`FIGURE 4-12 OUTPUT TIMING MEASUREMENT CONDITIONS .......................................................................... .. 76
`FIGURE 4-13 INPUT TIMING MEASUREMENT CONDITIONS .............................................................................. .. 76
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`A.G.P. Interface Specification
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`FIGURE 4-14 TVAL(MAX) RISING EDGE ........................................................................................................ .. 77
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`FIGURE 4-15 TVAL(MAX) FALLING EDGE....................................................................................................... .. 77
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`FIGURE 4-16 TVAL (MIN) AND SLEW RATE .................................................................................................... .. 78
`FIGURE 4-17 VH CURVES FOR 3.3V SIGNALING ............................................................................................. .. 79
`FIGURE 4-18 MAXIMUM AC WAVEFORMS FOR 3.3V SIGNALING ................................................................... .. 80
`FIGURE 4-19 RECOMMENDED COMPONENT PINOUT ...................................................................................... .. 81
`FIGURE 4-20 CLOCK SKEW DIAGRAM............................................................................................................ .. 84
`FIGURE 5-1 A.G.P. CARD EDGE CONNECTOR ................................................................................................ .. 90
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`FIGURE 5-2 DETAIL A, A.G.P. CARD EDGE FINGER LAYOUT .......................................................................... .. 90
`FIGURE 5-3 A.G.P. CARD EDGE CONNECTOR BEVEL ..................................................................................... .. 91
`FIGURE 5-4 MOTHERBOARD CONNECTOR FOOTPRINT AND LAYOUT DEMINSIONS. ......................................... .. 92
`FIGURE 5-5 MOTHERBOARD CONNECTOR LAYOUT RECOMMENDATION ................................................... .. 93
`FIGURE 5-6 TYPICAL ATX IMPLEMENTATION ................................................................................................ .. 94
`FIGURE 6-1 CONFIGUILATION VIEW OF AN A.G.P. TARGET ............................................................................ .. 98
`FIGURE 6-2 LOCATION OF A.G.P. CAPABILITIES ............................................................................................ .. 99
`FIGURE 8-1 SINGLE ADDRESS - NO DELAY BY MASTER................................................................................ .. 105
`FIGURE 8-2 SINGLE ADDRESS - MAXIMUM DELAY BY MASTER .................................................................... .. 105
`FIGURE 8-3 MULTIPLE ADDRESS - N0 DELAY BY MASTER ........................................................................... .. 106
`FIGURE 8-4 MULTIPLE ADDRESS - MAXIMUM DELAY BY MASTER ................................................................ .. 106
`FIGURE 8-5 1X SIDEBAND ADDRESSING....................................................................................................... .. 106
`FIGURE 8-6 2X SIDEBND ADDRESSING ......................................................................................................... .. 107
`FIGURE 8-7 MINIMUM DELAY BY TARGET OF READ TRANSACTION.............................................................. .. 107
`FIGURE 8-8 MAXIMUM DELAY BY TARGET OF READ TRANSACTION............................................................. .. 108
`FIGURE 8-9 MINIMUM DELAY OF BACK TO BACK READ DATA .................................................................... .. 108
`FIGURE 8-10 MAXIMUM DELAY OF BACK TO BACK READ DATA ................................................................. .. 109
`FIGURE 8-1 1 MINIMUM DELAY BY MASTER OF WRITE DATA ....................................................................... .. 109
`FIGURE 8-12 MAXIMUM DELAY BY MASTER OF WRITE DATA ...................................................................... .. 1 10
`FIGURE 8-13 MINIMUM DELAY BY MASTER OF BACK TO BACK WRITE DATA .............................................. .. 1 10
`FIGURE 8-14 MASTER DELAYS INITIAL WRITE NO DELAY ............................................................................ .. 1 1 1
`FIGURE 8-15 2X READ DATA - NO DELAY.................................................................................................... .. 111
`FIGURE 8-16 2X READ DATA - WITH DELAY ................................................................................................ .. 112
`FIGURE 8-17 2X BACK TO BACK READ DATA - NO DELAY .......................................................................... .. 1 12
`FIGURE 8-18 2X BACK TO BACK READ DATA - MAXIMUM DELAY............................................................... .. 1 13
`FIGURE8-19 ZXWRITEDATA-NO DELAY .................................................................................................. .. 113
`FIGURE 8-20 2X WRITE DATA - MAXIMUM DELAY....................................................................................... .. 1 14
`FIGURE 8-21 2X BACK TO BACK WRITES - NO DELAY ................................................................................. .. 1 14
`FIGURE 8-22 2X BACK TO BACK WRITES - MAXJMUM DELAY ..................................................................... .. 1 15
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`FIGURE 8-23 2X WRITES, INITIAL TRANSACTION WITH DELAY, SUBSEQUENT TRANSACTIONS NO DELAY 1 15
`FIGURE 8-24 MASTER DATA BUFFER FULL - MINIMUM DELAY FOR READ DATA.......................................... .. 1 16
`FIGURE 8-25 MASTER DATA BUFFER FULL - MAXIMUM DELAY FOR READ DATA ......................................... .. 1 16
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`FIGURE 8-26 RBF# ASSERTED, HP READ DATA RETURNED......................................................................... .. 116
`FIGURE 8-27 RBF# ASSERTED, MADGMUM DELAY BY TARGET, HP READ DATA RETURNED ........................ .. 1 17
`FIGURE 8-28 2X READ DATA, RBF# ASSERTED, MAXIMUM DELAY BY TARGET .......................................... .. 1 17
`FIGURE 8-29 2X READ, RBF# ASSERTED, N0 HP READ DATA .................................................................... .. 118
`FIGURE 8-30 2X READ DATA, WITH DELAY, RBF# ASSERTED, HP READ DATA RETURNED ......................... .. 1 18
`FIGURE 8-31 2X READ DATA, RBF# ASSERTED, HP READ DATA DELAYED ................................................. .. 1 19
`FIGURE 8-32 READ DATA, NO DELAY SUBSEQUENT BLOCK ........................................................................ .. 1 19
`FIGURE 8-33 READ DATA, MASTER READY - TARGET DELAYS SUBSEQUENT BLOCK ................................... .. 120
`FIGURE 8-34 READ DATA, TARGET READY - MASTER DELAYS SUBSEQUENT BLOCK .................................. .. 120
`FIGURE 8-35 READ DATA, TARGET DELAYS 1 CLOCK - MASTER DELAYS 2 CLOCKS SUBSEQUENT BLOCK 121
`FIGURE 8-36 WRITE DATA, NO