PCI System
`Architecture
`
`Third Edition
`
`MINDSHARE, INC.
`
`TOM SHANLEY
`
`AND
`_
`DON ANDERSON
`
`a ECEW EB
`
`JAN2 9 1996
`
`mm:
`
`SEWER
`
`‘A,
`
`Addison-Wesley Publishing Company
`
`Reading, Massachusetts I Menlo Park, California 0 New York
`
`Don Mills, Ontario I Wokingham, England 0 Amsterdam
`
`Bonn 0 Sydney 0 Singapore - Tokyo - Madrid - San Juan
`Paris 0 Seoul 0 Milan 0 Mexicci City 0 Taipei
`
`Page 1 of 235
`
`Samsung Exhibit 1019
`Petitioners HTC & LG — Exhibit 1019, p. 1
`
`Petitioners HTC & LG - Exhibit 1019, p. 1
`
`

`
`Many of the de.si.gnatiD1'1s used by manufacturers end sellers to dist1'ngu.lsh their
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`I..ibra1-gr of Congress Cataloging-in—Pub]lca1:I.on Data
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`;
`
`ISBN: U-2lJ1-40993-3
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`Copyright ID 1995 by Mirtdshnre, Inc.
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`publisher. Printed in the United State of America. Published simultaneously in
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`Sponsoring Editor: Keith Wollnum
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`First priming, February 1995
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`
`Page 2 of 235
`
`Petitioners HTC & LG — Exhibit 1019, p. 2
`
`I
`
`Petitioners HTC & LG - Exhibit 1019, p. 2
`
`

`
`To Nancy and Sheryl, two very understanding ladies.
`
`Page 3 of 235
`
`o....i._.-— --4. .. ..
`
`Petitioners HTC & LG — Exhibit 1019, p. 3
`
`Petitioners HTC & LG - Exhibit 1019, p. 3
`
`

`
`Content:
`
`Contents
`
`_
`
`-nu :1 Icon:|_n_un_|un n_|u|||_un|_Iuun_|_I|I_I|_:n|-u4_|unun-_-nu-_4-Lug-u |u|.|_|guu|uuuu an9!u.u_s_n....1|'.'.XX'. ,
`
`About This Book
`The Ml.n.dSha:e Architecture Series .............
`........
`...........................................1
`“ s
`I-IIOIIIICIIIIUIIOllllll-IllllllllnilIIIIIIIOI-IOOIIIIIIII-IIIIIIIIUIIIIIIIIIIIIIOIOOIOIIIIIDIIII 2
`is
`IIIIIIUIIOIIIIlllllllnltllllllllllllllllllllllllllII uQhIIfllIIIIlfl&llllllllllllllll—"Q.-'". a
`
`mo this
`
`Object Size Designations".......................................................................3
`Documentation Conventions.............................................._..............................
`Hex Notation
`
` l KIIIIIIIIIIIIIIIIIIC-IWWWWIII-IIIIIIIIUUIIICIOIOIOIIQIIOOHUIOIOOIQIIIHnnnnnnnnnII"I“..“.“‘3
`Q»i:5I:5|§tl-III-‘I13
`
`DecimalNotation
`
`.
`We
`
`Signal Name Representation....,.................-...........................................................
`Identification of Bit Fields (logical groups of bits or signals)
`.
`YB“! Fe nuuuuuuauuuu-nun.....Iu¢tcIIo¢IUIIIIIIOIIl|0oo-oocanooqn-nono-ouoqncnuiuuuu-cunt:‘-
` n mafiyiillillll II III I IIIGI III lIIOIIIIOflIo|nbI|IIIIIOII IIIII IIIICOOIIII I Iii: ICIIQI IIUOIIII OIICIIIII IIIIIICI-II 090 ll IIII 5
`.
`' ' Addmess
`'
`5
`Malling
`.... ..................... ........... ......-..-............... ..
`....................................
`
`Part I: Introduction to the Local Bus Concept
`
`CHAPTER 1: The Problem
`
`Block-Oriented Devices ............................................................................ 9
`Graphics Interface Perfonnance
`9
`
`Network Adapter Pufonnmoe B.. IO
`X-Bus Deviceferformenoe Comtreints.. 10
`Expansion Bus Transfer Rate Limitations ............................................
`13
`
`13
`EISA Expansion
`Micro Channel Architecture Expansion Bus ............................................................ .. 13
`
`Teleconferencing Performance Requirements 14
`
`CHAPTER 2: Solutions, VESA and PCI
`Graphics Accelerators: Before Local Bus ............................................................. 19
`Local Bus Concept.......................................................................................m
`Direct-Connect
`
`j
`
`Worlzstation Approach
`
`24
`
`I I
`
`I I
`
`|
`|
`
`/
`
`I I I I I
`
`_
`|
`
`.
`l
`
`l
`f
`I1i
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`I
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`Page 4 of 235
`
`Petitioners HTC & LG — Exhibit 1019, p. 4
`
`Petitioners HTC & LG - Exhibit 1019, p. 4
`
`

`
`3 V
`
`nu I04-an-u—uouuIllI-III I‘ III" '3 II III I! "I'll ICIIIUIUIIII-IIIIIUCIIII ll IIIIIIUI ICIQI I‘ IUI-IIOCUI
`
`E
`
`V1!
`
`........ ... ..... -4--an.......»......“nun":-nu.--uunu-u-.u--nun--no-cu u..u..u....uu-o-"......
`LOSiC
`Perfonnance.........................................;...............................
`.............
`.........
`
`.....,......
`......
`..........................
`Electricaflntegl-ity.'.........‘.....;.............-...........
`Add-in Cornnectors....................
`
`‘
`
`Revision 2.0 V1. Specification
`5D11l.tilJrI......... Ianun.-nnuuu-Inlulalinnqn[nullDI-IIIIIIIIIIIIIIIIIuugnlrirvuiou-nun:--0-ulnnlou n «non-mm
`PC!
`Market Niche for PCI and VESA VI..........................................................................
`Pu
`llolllli Ild-yd Illll I-I1II:-agqqqua-itIIII-IIIIIOIOIIbllilllliltlltulnllllnl-II!ICIII-In-Iullnnolflgfllu-u|||'|I|II III
`
`-E Bgfi my luuutupilblbl-IlliiuhllIIIIIOIIIIIIIIIOII-II-D-IAIIIGII-IIIOIUIIIIOIOIIIIIIJ III
`Obtaining PCI Bus Specificaiioms)
`
`Part II:'Revision 2.1 Essentials
`
`
`CHAPTER 3: Intro to PCI Bus Operation
`Burst TIaI1flf¢r....................m... -u-nu-pm -o -r--0 -nu-=-0-In-III--rlanllr-I-In-OI-C-II unnnnnnnnnnnnnnnnnnnnn-n
`Initiaior, Target and Agenta........................................................................................
`single was. Multi-function PCI Devices..............................................
`PCI
`Clntkquoa-nunnuannuaunnu -Iulnu no-u-nuurnu...unu-onunu no-I nun nu nu -none:-0 I-Iuouuu --
`Address Phase ..................................................
`
`Claiming the Tzumaclion......................................................................
`Data Phasetsl ..................................................................................
`Transaction D:ImItion................................................................... ........
`
`Shtennlu II IIIIINIIIIIHIIIIWIOIICOQIII
`h
`find
`-I nun you n nu I Inn | an I nu-ulliu-an“ nouanulu-nu an In Inucnu | I IIIIIII Ion-In null-uni-lino
`fin"
`
`
`CHAPTER 4: Intro to Reflected-Wave Switching
`Each'l‘ra¢:eIsaTma1IsmiesionI.ine................................................... ..
`
`Old Method: Incident-Wave Switching”...............................................................
`PEI
`RefleCted'W‘vE
`nuunnnuuouuu-tn-nuuncutunq--nun-Q--1--p----u-.-
`PC! Timing Characlerisiic: ......................
`
`'I11put’fi:ming................................................................................................ ..-
` g I II I I I II -:I I I sound I It-Ito it-I I loo I-uol I :0! tl I I OIIIILI III III I III CIIIII III IOIRI I III:-I II tau-
`Slower Clock Pannigs Longer Bus ...................................'................................
`
`Page 5 of 235
`
`
`
`Pe_ti_ti0ners HTC & LG — Exhibit 1019, p. 5
`
`Petitioners HTC & LG - Exhibit 1019, p. 5
`
`

`
`
`
`. Contents
`
`
`CHAPTER 5: The Functional Signal Groups
`Introduction........................................................ 53
`
`__ ..
`
`_
`
`.
`
`. X
`
`.
`
`56
`System Signals
`-PC1C.1oI:k.5igt'LaL(C'.l..K)...-..............n.-.......-..............-...............,...........................56——-——— -
`CLKRUN#Signa1
`57
`
`B‘lIl3.....'...m....-um-I".............................
`
`I nun-n IIIIIIIIIIIIIIIFI In IIIII I I III I III nu I II I-In nu
`
`Preventing Exnessive Cianwent Drai:n................................................................................ 62
`Transac|:'|on Control Signals
`63
`Arbitration Signals ....................................
`64
`Interrupt Request Signals
`65
`mo!
`IOOIIIIIIIIOOIIIIIIIIII II IIII.II IIIIIIIIIII IIIIIIIII-IIIOIIIII00 IIIIIII IIIIIIIIIII IIIIIIIIII-Olin: II
`6'5
`Data Parity
`66
`System
`Cache Support {Snoop Result) Signals6'7
`64-bit Extension 5igna1s................................... 68
`.................................... 69
`Resource l’..m:kin5..........................
`]TAGfBou.ndary Scan Signals ..............................................................t........................... 9'0
`IIIIIOI II!!! III! I IIIII I 7'1
`Inten-opt Request Linea......
`Sideband Signals ...............................L..................... 71
`Signal Types...... '71
`Central ResourceFunctions
`Subttactive Decode............................................................................................................ 73
`
` I!UIIIIII§Ii|IIIIIIII IUIIIIIIIIIIIIIIIIQIIIQUIQIII IOIQIIOIHIII|§!IIIII|OOC.I.|‘..ICIIlIII‘l".'U“"'"ITI"""'I--I E
`Tuning Subtractive
`....-........... ‘.74
`Reading TimingDiagrams“
`................ ?5
`
`CHAPTER 6: PCI Bus Arbitration
`IIIDI III XI-IIIIOI IOI IIIIIII III II IIIICIIIIIIIIII IIIII III I III I I I II II I IIIIIII-IIOIIXIII Ill IIII IIIIIII III IIIII IIIII III II IOIII II IIOII W
`
`Arb-il:ral'i.on. Algorithm ......................... '79
`Ba"mm"'FPI-P'f'IIl"'I‘II‘3'!'lIII“f"‘.5“'§"P!I'?*"."‘." '§I.§I1‘T‘-UIIIIUIIQIIIIIII-IIIIIflu
`Master Wishes To Perform More Than One Transaction 82
`III III IIIIIIIIII IIIII IIIII II I I I -I III IOIIIIIIIII
`Hidden Bus Arbitration-........................................................
`-
`
`B115 P gIII I -I II I III! Ioouuuuou-I Iuuuul Is I I III Iona IIIIIIII II III II II I II III I IIIII IIIHIIIIIIHIMIIIII II III II IIIuuuuuuuuuunn 5:
`IIIIIIIIII II IIIIIIIIIII-IIIICIVII.‘IIIII IIIII‘IIUIUIIIII.IIIIIIIIUIIIIUIIRIIIIIDII IIIIIII-UICIIIOQIOO-OI-I
`Example of Arbitration Between Two
`Bus
`OIIIDIIII IIIIIIIII IIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIII IIIIIIIII IIUIOIOIIII IIIIIIIInca-IIII-an nnnnnnI-u
`Master Latency Timer: Prevents Master From Monopolizingflus.. 91
`Location and Purpose of Master Latency
`91
`
`35
`
`
`
`Page 6 of 235,
`_
`- _
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`_
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`_
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`Petitioners HTC & LG — Exhibit 1019, p. 6
`
`Petitioners HTC & LG - Exhibit 1019, p. 6
`
`

`
`PCI Sgtem Architecture
`
`How LT
`
`.
`
`.
`
`Is Implementation of LI‘ RegisterMandatory? ..
`Can LT Value Be Hardwired (read-only)?
`How Does Configuration Software Delemflne Time-slioe To
`Be Allocated To
`Treatment of Memory Write and Invalidate Co
`Limit on Master's
`Preventing Target From Monopolizing Bus.........................................................
`- --n 9--uoouoo col Ion-90 Iuiol-Isa III IODII-IO lnnconna an-nu-up-H
`
`I.'5388333333
`
`............
`
`.......
`
`Target Latency on 1"-‘int Data Phase
`Options for Ach.ievirI.g Maximu.m'16 Clock latency ........................................ ..
`Different Master Attempts Access To Device With
`I’reviously=Laiched Request...
`Special Cycle Monitoringwhile Proowsing Request
`Delayed Roqumt and Delayed Completion ......................
`Handling Multiple Data Phases
`Master or Target Abort
`Commands Thatcan Use Delayed Transactions
`
`95
`3
`
`case
`
`97'
`......... 98
`
`Request Queuing and Ordering Rules........................................................... 98
`Locking, Delayed Transactions and Posted Writes
`IEB
`IIIIIIIIIIIIIIIIIIIIIIIIIGIIIIIIIIIIIIIIIIDIQI'IOI:5§QII1IDIIlOvl0Ui¢-lpm
`Decision to Implement Fast Back—to~Back Capability ............
`..........
`.................... 106
`Scenario One: Master Guarantees Lack of Contention
`106
`
`How Collision Avoided Onfiignala Driven By106
`How CoIi'mioen Avoided On Signals Driven By '.l'arget.......................................... 107
`How Targets Recognize New Transaction Has
`109
`M
`CUIIDIIIIIIIII IIIIIllllllllIQIIIIICUHIIHOHIIIIUIIIIIIIIII-IlIIOvIIF'l
`110
`Scenario Two: Targets Guarantee Lack of Contention....
`State of Rl3Q# and GNT# During R5-'I'#................................................................. 111
`Pullups On REQ#F1-am Add-In Connectors .................................................112
`llrolten Master.....................................................................-......................... 112
`
`CHAPTER '7: The Commands
`Qltlttl IIII I Iucnu ulouolol IIIII uh: I-I n IHIIIIII I-Iuoluahlu ill II all I Ildld noun-Inc-u c u nu n I u n u n nun Iannnml u n
`
`II
`
`Interrupt Aclcnowledge CuInmand......................................................... 114
`Introduction........................................................................................................ 1141
`
`115
`Host/PCI Bridge Handling of Interrupt Acknowledge Sequence
`116
`PCI Interruptlkclmowledge Transaction ..
`Special Cycle Command .............................................................................................119
`
`viii
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`Page 7 of 235
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`Petitioners HTC & LG — Exhibit 1019, p. 7
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`Petitioners HTC & LG - Exhibit 1019, p. 7
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`

`
`119
`General .......................
`121
`Special Cycle Generation......
`121
`Special Cycle
`....
`121
`Single-Data’ Phase Special Cycle
`Multiple Data Phase Special Cyde Tramaciioum......................................... 122
`HO Read and Write Commands .............................................................. .. 124
`
`
`
`....
`
`‘ Accessing Me:nury.'.:.;..:.........;..:.;.;..'..:.......'.‘............-.'.'.............'......:........
`Reading Meninry.
`
`124
`125
`
`125
`Memory Read Line
`12.5
`Memory Read Multiple
`Writing Memory......................................;............................................ 126
`Memory Write Command ................................... 126
`
`127
`Description of Mamorywrite andlmralidate Command
`More Infomiafion On Memory Transfers ................................................................. 12?
`Configuraflon Read and Writecommands ............................................... 125
`Dual-Address Cycle...............................................a..............................12fl
`Resenfcd Bus Commands
`......-......................................................................12B
`
`
`' CHAPTER 3; The Read and Write Transfers
`some Basic Rules
`
`.IIIII IIIII!|Inotnoncnultnonuuosnun-nununil-I--I-I-nu-u-u 129.
`
`
`
`PaIily.....-..............................................................................................................................13l}
`Read 'I'rensnction.......,................................................................................................... 130
`
`'IEreah:nent of Byte Enables During Read orWrite...... .. 134
`Byte Enable Settings Mayvmy from Data Phase to Data Phase".....................134
`Data Phase with No Byte Enables
`135
`Target wifiu Limited Byte Enable
`136
`Rule for Sampling of Byte
`136
`Ignnre Byte Enables During LineRead.........
`
`W1-iteTraxuautiun............................................................................................ .. 139
`
`139
`
`Posted-Write Buffer
`
`.................... .............. 146
`
`
`
`Page 8 of 235
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`._
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`_
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`_
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`Petitioners HTC & LG — Exhibit 1019, p. 8
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`Petitioners HTC & LG - Exhibit 1019, p. 8
`
`

`
` .
`
`PCI System Architecture
`
`Ildvlllnlldll-IIOIIIDWIQOIIIIIIIIQIUISIIIII-OIIIFFUOll:-nmoulolvillIDIIII|I-I-IIIIIUOIUI-Iwlllllliltiujjnlllil lII-
`1417
`Cache Lino Merging
`Addressing Sequence During Memory Burst.... 143
`Linear and Cacheline Wrap Addressing.................................................................... 148
`Target-Response to Reservetlfietfi-TF3 on AD[1:0].................................. 150
`Do Not Mu'ge'P:ooessor I10 Writ into Single Burst.I....I.....-lL.2.-;.;.....J.'..;......;;.:.a..~... 150-
`PCI U0Addressing.......... 150
`General........................................................................................................................... 150
`Situatlon Resultirlg in
`151
`HO Acldlesu Management ................ ... ................................................................... 153
`When H0 Target Doesn't Support Molt!-Dal: Phase Transactions..........'............... 153
`Addressiflste Stepping................................................................................—.----— 154
`Advantages: Diminished Current Drain and
`154
`Why Targets Don't Latch Address During Stepping-Process .............................. 155
`Data Stepping ..
`155
`How Device Indicates Ability to Use Stepping
`15
`Designer May Step Address, Data, PAR (and PARE-4) and IDSEL.......................... 156
`
`Disadvantages of
`Preemption While Stepping in
`
`.......................................
`
`......................... 157
`15?
`
`161
`When Not to Use
`161
`Who Must Support
`Response to Illegal Bchavior............................................................................. 151
`
`
`CHAPTER 9: Premature Transaction Termination
`Introduction ................................................................................................. 163
`Master-Initiated '1‘enninatioo.................
`........................................................ ..1fi5
`
`'I‘i.meslioe Expiration Followed by Pneeruption.................................................. 165
`Master Abott: Target Doesn't Claim 'I'ra:1anction
`................
`16?
`Introd.ucb'.on ...................................................... ......................... .. ................. ... 16'?
`MasterAbortonSing1eDatnP1-Iase Transaction.......
`............
`......
`..... ".167
`Master Abort on Multi-Data Phase
`169
`Action Taken byMa_s1:er in Response to Master Ahort
`171
`
`H
`
`171
`Special Cycle and Configurationhcoess
`Target-Initiated............ 171
`
`n£'—-.
`
`Page 9 of 235
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`‘*—"‘* '"—-—- — -——— ——— -———__P.E‘l.iIiQLl61‘S HTC 8LLG__—_E_)g1Libit 1019, p. 9
`
`Petitioners HTC & LG - Exhibit 1019, p. 9
`
`

`
`
`
` .:..........................................................................................
`
`‘
`
`173
`Reasons Target Issue Discon11ect.........
`173
`Target Slow to Complete Data
`1.73
`Memory Target Does.n’t Understand Addresaing Sequence .
`'Trens£e1'Crosses Over Target’: Add:-ess'Bound'a:y..;'....-.LL...;._.-.H 173
`Bunst Memory Transfer C1-ones Cadre Line Boundary............................. 1'74
`‘Type “A” Disconnect: In1'tiatorNot Ready When Target Says
`174
`Type “B” Disconnect: Initiator Reedywhen Target Says STOP
`1?5
`Retry (Type C) Disconnect ........................
`178
`
`Reasons Target Issues Retry ...................................................................... 179 -
`Memory Target Doesn't Understand Addressing Sequence
`1??
`Target Very Slow to Complete First Data
`179
`Snoop Hit onMod.i.fied Cache
`179
`
`Memory Target Loc1oed..........................................2................................. 180
`
`Target Abort
`
`.........
`
`....
`
`182
`
`................. 1
`Reascms Target Issues Target
`....._...................................183
`1/0 Addressing Eu-or ...........-........... 183
`Address Phase Parity Error ..............
`183
`Mastefs Response to Target Abort...................................................................... 183
`Target AbortExample. 183
`How Saon Does Initiatorfiitempt to Re-Estab]ishTnnsfeI After
`
`Tatget—h1itiat:edTetminationS:urunery..............
`
`...........
`
`185
`
`CHAPTER 10: Error Detection and Handling
`Introduacflon to PCI Parity....................................................................... 137
`Plillki Signal-......................................................................................1B9
`Data Parity .......................................................................................1ss
`Data Patity Generation and Checking on
`189
`189
`
`190
`........
`Example Burst Read .......................................
`Data Parity Generation and Checkirlg canWrite........ 193
`m IIIIIIIIIIIIIIIIIIIICIIIUI-UIUCOHIIC IAIIIIAIIII IIIIOUIOIOUIIIIIIIIICI ICIUIII lvl-II-IIIIIIIIIIIlllJIICIl1II.
`
`Example Burst Wflte .......-...... ........................................................
`
`193
`
`
`
`Page 10 of 235
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`Petitioners HTC & LG — Exhibit 1019, p. 10
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`Petitioners HTC & LG - Exhibit 1019, p. 10
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`

`
` :
`
`PCI Szstem Architecture
`
`DataParity 195
`
`Parity Error bu:-mgRead196
`Parity Em D‘-fins
`------------u-u-1--M-ounonu--Inn-cu.“-an-n nu-in"wontwoQ-nut-I-I-Ilihouuu
`-----------------Innn-n-punun nu
`Illliinnu-unlnoutilnI|n.|
`Caméva Dab: Pa’:-it? Error
`Cycle ....‘..'........?...'.......;:;.....;.....;;.:.. 199 '
`
`'
`
`.......... 200
`Chipeete......
`or Data ................... 200
`Devices ThatDon."t Deal with OS/Application
`smuu SigI1|l...................................................................................................... 201
`Address Parity.................................................................................. 202
`Address Parity Generatiozn and
`102
`
`system
`
`205
`
`205
`DataPariIy Error During Special Cycle
`205
`Target Abort
`Other Possible Causes of System Error ....................... . ............................................ .. 2435
`Devices Excluded from SEER! Requirement -......-........................ 205
`
`CHAPTER 11: Interrupt-Related Issues
`‘
`
`Single-Ptmclion PC] Device .......................................................................................
`PC]. ma .......-..—..-euuuuuud-uuuuu--uuuuucnuou-nuuuuuuuu ----nqnlnulllllnnnncu
`Connection of IN'l'x# line: To System Board 'l'raoes....................;................................ 209
`I.nten_-upt Routing.................................. 2.10
`General ........................................................................................................... .. 21:]
`
`Platform "Knows" Interrupt Trace Layout ............................................................... 216
`Well-Designed Platform Has Programmable In!-ermpl:216
`
`PCI Interrupts Ame Shaw.-abie .............................................................................................217
`UUIIIIIIIIIIIIIIUlIIII*.‘IXIIIIOIIIIlIOII‘nnnnnnluouqquuuuIIOOOIIC Innnoultnqgnotldlfillllllnill
`chain-i-l1.Bo-nuu-an-«nu:uunoo-nu-on»-nnuouunun-nu nu-uunuuuu ueunuueunnnuuuunnunun
`
`1|
`
`Step One: Initialize All Entries In Table To Null Value
`Step Two: Initialize All Entries For EmbeddedDevices 219
`Step Three: Hook Entries For Embedded Device BIOS Routines ....................._..... 219
`
`221
`Step Five: Perform Expansion Bus ROM
`........................................... 221
`Step Six: Load Operating System..................................
` M for
`OICIIIICI-IOIIOIIIIIIIIIIIlI§QIOIOIIOIIUIllII‘- m
`
`L
`
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`Page 11 of 235
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`Petitioners HTC & LG — Exhibit 1019, p. 11
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`Petitioners HTC & LG - Exhibit 1019, p. 11
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`

`
`Contents
`
`..__._ ,
`
`Servicing Shared Inten-upls..............................................................,............... 223
`.........................................‘.................................»....................."223
`1LI‘;or-1--L---uiuruluunI-In-oiIII-nun---uni 224’ "_'
`30th
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`
`.
`
`u
`
`Remm to Interrupted Promm. Follow by Second Interrupt.. 22?
`Pint Handler Executed Again. Passes Control to Second .....................................22.‘7
`Implied Priority 5t.‘.l‘I.¢llIl!....-..«.....:...........................................................12'?
`Interrupts and PCI-lo—PCI Bridges ............................................................. 228
`
`
`CHAPTER 12: Shared Resource Acquisition
`Using Semaphore to Gain Exclusive Ownership of Resource................................. 229
`Memory Semaphore De:t'inition..... .......
`230
`Synchronization Problem
`PC! Solutions: Bus and Resource Loc|:Ing............................................................ :31
`
`Bus Lock: Peonisailale but Not Preieued ..................;......................................... 231
`Resource Lock: Preferred Solution
`232
`
`233
`Establishing Look on Memory Tau-get...........
`23?
`Unlocked 'I'argelsMayBeAec:essecI byany
`237
`Access to Locked Target by Master Other than Owner:
`Conlimmtiorl. and!or End of Locked ‘fin Series ............................ 239
`
`Potential Deadlock Condiflon................................................................................a..........2!!
`Assumptions............................................................................................................"241
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`242
`
`Device: that Most Implement Lock Support ......................................................... 2-I4
`Use of LOCK# with Sdrbit Addressing ........................................................ ................... 244
`Summary of Looking Rules ............................................................................................., 2-I-I
`Iartplexrterztalion Rules for
`244
`hnplementation Rules for Targets ............................................. 245 '
`
`CI-IAP'I'ER 13: The 64-bit PCI Extension
`
`and
`
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`Fttlltipi Prevent 64-bit Extension from Floating When Not in lJse.............................249
`in
`Pa
`III III III II IIII UII II IO IIIIIIUIIIIII Illli
`How mm Card Deter:-.ru‘nes Type of Slot Installed 1n..........
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`
`250
`
`
`
`..
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`Page 12 of 235
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`\
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`Petitioners HTC & LG — Exhibit 1019,.p. 12
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`J,
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`Petitioners HTC & LG - Exhibit 1019, p. 12
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`

`
`PCI Szstern Architecture
`
`253
`onlymemary Commands May Use 64-biz Transfers
`Start Address Qusdworlsl-Aligned ........................................................................ 253
`64-bitTarget'sInte1-pretetiom of
`253
`32-bit Targers Interpretation of
`254
`64-bit lilitiator and 64-bit‘!‘a.rget............;........... 254
`
`260
`Null Data Phase ‘Example-...........
`32-bit Initiator and 64-bitTarget 262
`
`......................... 263
`With 64-bit Target. .............................................
`263-
`With 32-hit
`
`Simpler and Inst as Fast: Use 32-bit Transfers............................................... 264
`With Known -64-bit Target ....................................................................................2'.64
`
`....
`
`64-bit Addressing......................................................................................-.........2sr
`Used to Address Memory Above-1GB
`................... .., ................... ........................................
`..... 268
`
`268
`64-bit Addressing
`64-bit Addressing by 32-bit Init1nt:or................................................... 268
`64-bit Addressing by 64-bit
`2?1
`32.-‘bit Initiator Addressing Above453........
`274
`Subtrsclive Decode ‘Turning274
`Master Abort Timing ‘Affected .............................................................................. .. 275
`Address Bhzpgpcing......................................................................275
`FRAMIE# Timing in Single Data Phase Tramsction
`276
`64-l:IitParily.......................................................................................z7s
`
`PA1§6-LNot Used for Single Address
`PAR64 Not Used for Dual-Address Pines by 32-bit
`PAR64 Used for Dual-Address Phase by 64-bit Master {when
`requesting 64-bit data transfers}
`....
`Data Phase
`
`
`2.76
`276
`
`226
`
`CHAPTER 14: Add-in Cards and Connectors
`
`Expansion Connectors........................................... 279
`32 and 64-bit Connectors
`.....
`....
`
`64-bit Connector.. 284
`
`
`adv
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`§n:.|uI.l.w._
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`Page 13 of 235
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`'--~
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`-
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`~ -
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`-
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`---T
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`. -
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`Petiti_0ners HIC &_L_.G — _]_Eg<_11ibit 1019, p. 13
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`Petitioners HTC & LG - Exhibit 1019, p. 13
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`

`
`Shared Slot ..................................................................................................... 286
`
`....................................
`Snoop Resultsignalson Add-inconnactor..............
`Expansion Cards............................_....._.......................................... 289
`3.3V. 5V and Universal ........,..............,.................... 289
`Long and. Short Form
`" Componanfllayotit
`Maintain Integrity of Boundary Scan Chain
`Card Power
`
`289'
`291
`291
`
`..............................................................................292
`
`
`Part 111: Device Configuration In System With
`a Single PCI Bus
`
`
`CHAPTER 15: Intro to Configuration Address Space
`I
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`................................................................... ... 296
`PC] Package vs. PCI Function
`Tlrrge Address Spaces: U0, Memory and Configuration........................... 2.97
`S with
`M ‘Hm-Iii-VIII‘-IllIIlQIO‘OOOII*“|IOflflflflflflflflflflflflIIIIIIIIIIIIIIIIQIIIIIIICIIOIII‘itI'IPIlFl 299
`
`CHAPTER 16¢ Configuration Transactions
`Which “Type? Arewe Talldng Abonfl-........................................................... 301
`Who Perfonrla Con.fi5I.I:ra|:ion?..........................................................................
`Bus Hierarchy ..................................................................J................................................... 302
`Intro to Configuration
`304
`
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`
`General I nun H In Iubuuuuot II on
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`
`Configuration Address Port ............
`‘Bus Compare and Data Port Usage
`Muljiple Host/PC] Bridges ............................................................................
`Single I-IostlPCI Bridge................................................................................... .. 311
`Genemtion of Special Cycles....................................................................................
`311
`Configuration Mechanism Two
`312
`
`................................................... 307
`308
`
`Configuration Space Enable, orC5E, Regia$er........ 314
`
`support for Peer Bridges on Hoot
`
`......................................................... 315
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`Page 14 of 235
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`_._ j _. Petitioners HTC &L__G - Exhmit 1_()19, g. 14
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`Petitioners HTC & LG - Exhibit 1019, p. 14
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`

`
`——
`
`PCI System Architecture
`
`Generation of Special315
`Pane-rl'C Pita? Memory»-Mapped Conflguntlocn
`516
`Typezan Configutalion Transaction................................................................................ 319
`- Address Phase
`319
`Implementation of
`......320
`Data Phase
`................ ....-................................................
`..........
`........ 321
`
`Type Zero Configuration ‘Transaction .........321
`Target Device Donn’! E:clst.................................................................... 325
`Configunfion Bun! 'I‘rannacl'lo:u........... S25
`6-1-3:: canflguuum Truuactimu Not Permitted ........................................................s-,2;-,
`Rnainlively-Coupled IDSEL in Slow..-.........................I................................................... 326
`
`
`CHAPTER 17: Configuration Registers
`Intro to Configuration Header Region ............................................................................ 327
`Mandatory Hamlet llegisterm.........................................................................._................ 3:9
`...................
`329
`Vendor 11:: Register ..................
`........................._............329
`Device ID
`
`..... ...........
`
`VGA Color Palette 5nooping........................................................................
`333
`Status Register
`Revision IDRegimn-........-............- 335
`Class Code Register
`...........
`.........
`........................................ 335
`Header '1‘ype Register
`34:1
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`Illtroduzflnn......... ................................
`..................
`.............................
`
`341
`
`Cache Line Size......... 341
`
`............ .._..343
`.............
`BISTRegister...........
`Base Address ..............3H
`
`Memory Base Address Regina:-r............-.................................
`HO BaseAdd1-as
`De|:erm.i:1bLg Bloc]: Size andAs5i.gningAddress Range
`
`345
`347
`34?
`
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`353
`
`
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`Page 15 of 235
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`.___,
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`Petitioners HTC & LG — Exhibit 1019, p. 15
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`Petitioners HTC & LG - Exhibit 1019, p. 15
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`

`
`Priority-Level Request
`Max_LaI
`Add'In Memuqtlln Ill ll LIIHI-In-I1-nnri and III I I I III nun Ila-nu unit-I In II - I III In: -In III n in mi