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`Petitioners HTC & LG - Exhibit 1005, p. 1
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`

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`Page 2 of 23
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`Petitioners HTC & LG - Exhibit 1005, p. 2
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`Petitioners HTC & LG - Exhibit 1005, p. 2
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`

`
`digest of papers
`
`FI:brI_Iai'y 25 -23. ‘IBEQE
`
`UIIIPQ
`
`IFITY-F|FIST1EEE CDl‘.'IF‘LJTER SOCIETY If-JTEFWATIOPJAL CICINFEFIENCE
`
`Page 3 of 23
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`Petitioners HTC & LG - Exhibit 1005, p. 3
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`Petitioners HTC & LG - Exhibit 1005, p. 3
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`

`
`digest ofpapers
`
`COMPCON ’96
`
`Technologies for the Information Superhighway
`
`Forty—First IEEE Computer Society International Conference
`
`Sponsored by — The IEEE Computer Society
`
`February 25-28, 1996
`
`Santa Clara, California
`
`IEEE Computer Society Press
`Los Alamitos, California
`
`Tokyo
`. -
`Brussels
`-
`Washington
`
`
`Page 4 of 23
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`

`
`
`
`,
`
`.
`
`‘
`
`
`
`IEEE Computer Society Press
`10662 Los Vaqueros Circle
`P.O. Box 3014
`Los Alamitos, CA 90720-1264
`
`Copyright © 1996 by The Institute of Electrical and Electronics Engineers, Inc.
`All rights reserved.
`
`Copyright and Reprint Permissions: Abstracting is permitted with credit to the source. Libraries may
`photocopy beyond the limits of US copyright law, for private use of patrons, those articles in this volume
`that carry a code at the bottom of the first page, provided that the per-copy fee indicated in the code is paid
`through the Copyright Clearance Center, 222 Rosewood Drive, Danvers, MA 01923.
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`IEEE Copyrights Manager, IEEE
`Other copying, reprint, or republication requests should be addressed to:
`Service Center, 445 Hoes Lane, P.O. Box 1331, Piscataway, NJ 08855-1331.
`
`The papers in this book comprise the proceedings of the meeting mentioned on the cover and title page. They
`reflect the authors’ opinions and, in the interests of timely dissemination, are published as presented and
`without change. Their inclusion in this publication does not necessarily constitute endorsement by the
`editors, the IEEE Computer Society Press, or the Institute ofElectrical and Electronics Engineers, Inc.
`
`IEEE Computer Society Press Order Number PR07414
`ISBN 0-8186-7414-8
`ISSN 1063-6390
`
`IEEE Order Plan Catalog Number 96CB35911
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`Microfiche ISBN 0-8186-7416-4
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`IEEE Computer Society Press
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`Page 5 of 23
`
`®
`
`The Institute of Eiectricai and Electronics Engineers, Inc.
`
`3° wig giigéiflfi
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`Petitioners HTC & LG - Exhibit 1005, p." 5
`
`Petitioners HTC & LG - Exhibit 1005, p. 5
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`

`
`Proceedings of COMPCON '96
`
`Table of Contents
`
`Message from the General Chair .............................................
`
`............................................. .. xi
`
`Message from the Program Chair ..................................................................
`
`.................... .. xiii
`
`Organizing Committees ........................................................................................................... ..xiv
`
`Session 1: Wireless Interconnects
`
`Chair: John Barr ——— Motorola
`
`CDPD and Emerging Digital Cellular Systems ...................................... ..
`
`
`
`W
`
`T. Melanchuk, P. Dupont, and S. Backer
`
`a
`
`Wireless Network Extension Using Mobile IP ............................ .
`R.L. Geiger, J.D. Solomon, and KJ. Crisier
`
`The Bay Area Research Wireless Access Network (BARWAN) ............................................. .. 15
`R.H. Katz, E.A. Brewer, E. Amir, H. Balakrishnan, A. Fox, S. Gribble,
`T. Hades, D. Jiang, G.T. Nguyen, V. Padmanabhan, and M. Stemm
`
`Session 2: ATM Networks
`
`Chair: Anujan Vanna —— University of California, Santa Cruz
`
`Performance of Explicit Rate Flow Control in ATM Networks ............................................... ..22
`L. G. Roberts
`
`MPEG-2 Over ATM: System Design Issues ........................................................................... . .26
`S. Varma
`
`FAST: A Simulation Testbed for ATM Networks .................................................................. .. 32
`D. Stiliadis and A. Varma
`
`Session 3: Broadband Interactive Data Services
`
`Chair: Ilja Bedner — Hewlett—Packard
`
`HP BIDS — Broadband Interactive Data Solution .................................................................. .. 39
`I. Bedner and A. Ranous
`
`Design Considerations for a Hybrid Fiber Coax High-Speed Data Access Network ................. ..45
`D. Picker
`
`Session 4: Agent Languages
`
`Chair: Adam Hertz —- General Magic
`
`Mobile Telescript Agents and the Web ................................................................................... .
`P. Dome!
`_
`
`. 52
`
`Mobile Agent Security and Telescript ..................................................................................... ..58
`J. Tardo and L. Valente
`
`Page6of 23
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`

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`
`
`Session 5: World Wide Web
`
`Chair: Robert Hagrnann —— Oracle
`People, Places, and Things: The Next Generation Web .......................................................... ..65
`J. Gwertzman and M. Seltzer
`An Internet Difference Engine and its Applications ................................................................. .771
`T. Ball and F. Donglis
`Don’t Get Caught in the Web: A Fieldguide to Searching the Net .......................................... _.7'l
`W.R. Tathill
`
`Session 6: World Wide Web Sewers
`
`Chair: Winfried Wilcke »— HAL Computer Systems
`A Scalable and Highly Available Web Server .......................................................................... .. 85
`D.M. Dias, W. Kisli, R. Makherjee, and R. Tewari
`
`Session 7: Performance Characterization and Analysis
`Co-Chairs: Nasr Ullah and Marianne I-Isiung —-— Motorola
`The Capture, Characterization, and P61‘f0I'1Tl3I1C6 Analysis of Macintosh® Traces .................... ..94
`S. McMahon
`
`A Measurement Study of Memory Transaction Characteristics on a
`PowerPC-Based Macintosh ................................................................................................... .. 100
`T. Adams
`Load Miss Performance Analysis Methodology Using the PowerPCTM 604 Performance
`Monitor for OLTP Workloads ............................................................................................... .. 111
`E.H. Well:-on, RS. Moore, RE. Levine, and C.P. Roth
`Workload Effects on SMP Scaling in AIX Version 4 ............................................................ .. 117
`K. Dixit, J. Van Fleet, and B. Olszewski
`
`Session 8: Panel — Networking Virtual Environments
`Chair: Michael Zyda —-— Naval Postgraduate School
`Panelists: M. Zyda —— “Networking Large—Scale Virtual Environrnents”
`T. Meyer — “The Future of VRML”
`M. Macedonia —»~— “A Taxonomy for Networked Virtual Environrnents”
`W. Kata — “Defense and Entertainment Industry Efforts in Networking
`Virtual Environments”
`
`Session 9: PowerPC Microprocessors and Systems
`
`Co-Chairs: Nasr Ullah ~— Motorola
`
`Kaivalya Dixit — IBM
`Design of the PowerPC 604eTM Microprocessor .................................................................... .. 126
`M. Derirnan, P. Anderson, and M. Snyder
`The Performance and PowerPC Platform” Specification Implementation of the
`MPC106 Chipset .................................................................................................................. .. 132
`C.D. Bryant, MJ. Garcia, B.K. Reynolds, L.A. Weber, and GE. Wilson
`
`Page 7 of 23
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`

`
`PowerPC Platform: A System Architecture .......................................................................... ..140
`S. Bunch, R. Hochsprimg, and T. Moore
`
`_ Motorola PowerPCTM Migration Tools — Emulation and Translation ................................... .. 145
`T. Afzal, M. Bretemitz, M. Kacher, S. Menyhert, M. Ommermtm, and W. Sit
`
`Session 10: PA-RISC Evolution
`
`Chair: Ruby Lee — Stanford University
`
`64-bit and Multimedia Extensions in the PA-RISC 2.0 Architecture ...................................... .. 152
`R. Lee and J. Huck
`
`Mid—Range and High—End PA—RISC Computer Systems ....................................................... ,. 161
`R. Eisbemd
`
`PA"/30OLC Integrates Cache for Cost/Performance ............................................................... .. 167
`D. Holleribeck, S.R. Unciy, L. Johnson, D. Weiss, P. Tobin, and R. Carlson
`
`Session 11: Having it your Way — High-Code-Density, High-Integration,
`and High-Performance ABMs
`
`Chair: Allen Baum — Apple Computer
`
`Thumb: Reducing the Cost of 32-bit RISC Performance in Portable and
`Consumer Applications ............................................................. .
`._.......................................... .. 176
`L. Goiidge and S. Segars
`_
`
`ARM”/' 100 — A High—Integrati0n, Low—Power Microcontroller for PDA Applications .......... .. 182
`G. Budd and_G. Milne
`—
`'
`StrongARM: A H'rgh—Performance ARM Processor ............................................................. .. 188
`R. Wirek and J. Montonaro
`
`Session 1 2: MPEG2
`
`Chair: Vivian Shen — Hewlei‘r—Pockcird
`
`A Scalable Chip Set for MPEG2 Real-Time Encoding ..... . .'................................................... .. 193
`A. Ngai, J. Sutton, C. Boice, and C. Gebler
`
`Performance Comparison of MPEG1 and MPEG2 Video Compression Standards ................. .. 199
`S. Liu
`
`Mediaprocessing in the Compressed Domain ........................................................................ 1.204
`V. Bhoskaron.
`
`Session 1 3:
`
`Interactive Television
`
`Chair: Robert I-lagmann — Oracle
`
`A Distributed System Clienti’Se1'ver Architecture for Interactive Multimedia Applications ..
`S. Rege
`
`.
`
`. 211
`
`Dynamic Bandwidth Allocation for Interactive Video Applications over Corporate
`Networks .............................................................................................................................. .
`C.J. Beckmorm
`
`. 219
`
`-The Tiger Shark File System ................................................................................................. ..226
`R.L. Hoskin and F.B. Schmuck
`
`A Page 8 of 23
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`vii
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`

`
`
`
`Session 1 4: Interactive TV Settop
`Chair: Deven Kaira —- HewleIt—Packard
`Interactive Television Settop Terminal Architectures ............................................................ ..233
`A.N. Nair
`Multimedia Transmission Link Protocol ——~ A Proposal for Digital Information
`Transmission in HFC Cable Systems .................................................................................... ..
`R~F. Chin and R. Hutchinson
`DAVID® System Software v2.0 for Interactive Digital Television Networks ........................ ..
`A. Davidson
`
`239
`
`241
`
`Session 1 5: Scalable Clusters
`Chair: Marco Annaratone —- DEC Western Research Laboratory
`Overview of Memory Channel Network for PCI ................................................................... .244
`R. Gillett, M. Collins, and D. Pimm
`Digital’s Clusters and Scientific Parallel Applications ........................................................... ..
`R. Kaufinann and T. Reddin
`Overview of Digital UNIX Cluster System Architecture ........................... .; .......................... ..
`W.M. Cardoza, F.S. Glover, and W.E. Snaman, Jr.
`
`250
`
`254
`
`Session 16: HAL Computer Systems
`Chair: Winfried Wilcke — HAL Computer Systems
`
`A 9.6 GigaByte/s Throughput Plesiochronous Routing Chip ................................................. ..
`A. Mu, J. Larson, R. Sastry, T. Wieki, and WW. Wilcke
`Performance Limiting Factors in Http (Web) Server Operations ............................................ ..
`F. Prefect, L. Doan, S. Gold, T. Wicki, and W. Wilcke
`
`261
`
`267
`
`Session 1 7: Exploiting New Storage and Network Technologies
`Chair: Norman J. Pass —— IBM Almaden Research Center
`SSA: A High—Performance Serial Interface for Unparalleled Connectivity ............................ .274
`A. Wilson
`Redundant Arrays of Independent Libraries (RAIL): A Tertiary Storage System .................. ..
`D.A. Ford, R.J.T. Morris, and A.E. Bell
`Randomized Data Allocation for Real—Time Disk I/O ........................................................... ..
`S. Berson, R.R. Muntz, and WK. Wong
`
`Services and Architectures for Electronic Publishing ............................................................. ..
`D.M. Choy and R]. T. Morris
`
`Session 18: Multimedia Authoring
`Chair: Michael A. Harrison —- University of California, Berkeley
`Graphical Object-Oriented Multimedia Application Development: Technology
`and Market Trends ................................................................................................................ ..
`
`299
`
`H. Steger
`
`-
`
`' Page 9 of 23
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`280
`
`286
`
`291
`
`Petitioners HTC & LG - Exhibit 1005, p. 9
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`

`
`Graphical Containment in Multimedia Authoring .................................
`H. Epelman—Wang, S. Markowitz, and B. Roddy
`
`............................ .. 300
`
`User Interfaces for Authoring Systems with Object Stores .................................................... .. 305
`B. Roddy, S. Markowitz, and H. Epelman-Wang
`
`Session 19: Competing Architectures for Multimedia Processing
`
`Chair: Cary Komfeld — consultant
`
`The MpactTM Media Processor Redefines the Multimedia PC ....... .; ....................................... .. 311
`P. Foley
`
`An Architectural Overview of the Programmable Multimedia Processor, TM—l
`S. Ratlmam and G. Slavenlmrg
`
`.................... .. 319
`
`Improving Performance for Software MPEG Players ............................................................ .. 327
`DF. Zucker, MJ. Flynn, and RB. Lee
`
`Session 20: The Microllnity Mediaprocessor
`Chair: Steve Manser -— Micro Unity Systems
`
`Architecture of a Broadband MediaProcessor ........................................................................ .. 334
`C. Hansen
`-
`
`MicroUnity Software Development Environment .................................................................. .. 341
`R. Hayes, G. Loyola, C. Abbott, and H. Massalin
`
`Broadband Algorithms with the Microilnity Mediaprocessor ................................................ .. 349
`C. Abbott, H. Massalin, K. Peterson, T. Karzes, L. Yamano, and G. Kellogg
`
`Session 21: DRAM Technologies
`
`Chair: S. Peter Song W Samsung
`
`Burst and Latency Requirements Drive EDO and BEDO DRAM Standards .......................... .356
`A. Mormonn
`
`Synchronous DRAM Evolutionary Changes Bring Cost/Performance Advantages in
`Memory Systems .................................................................................................................. .. 360
`A.B. Cosoroaba
`-
`
`High Bandwidth RDRAM Technology Reduces System Cost
`R. Crisp
`'
`
`.......................................... ..365
`
`Multi—Gigabyte/sec DRAM with the MicroUnity MediaChannelTM Interface ......................... .. 378
`T. Robinson, C. Hansen, B. Herndon, and G. Rosseel
`
`Session 22: Pentium®Pro System Architecture
`Chair: Konrad Lai — Intel
`
`An Overview of the Pentium®Pro Processor Bus .................................................................. .383
`N. Samngalhar and G. Slngh
`
`Pentium®Pro Processor Workstation/Server PCI Chipset ...................................................... .. 388
`M. Bell and T. Holman
`
`Multiprocessor Validation of the Pentium®Pro Microprocessor ............................................. .. 395
`D. Marr, S. Thakkar, and R. Zucker
`
`Page 10 of 23
`
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`

`
`
`
`Session 23: Storage Technology
`
`Chair: Harry S. Gill — IBM
`
`Data Storage IC Technolgy ................................................................................................... .
`J. Kovacs and R. Kroesen
`'
`'
`
`. 402
`
`Session 24: UItraSPARC and Java
`
`Chair: Robert Garner — Sun Micrasystems
`
`UltraSPARCTM: Compiling for Maximum Floating-Point Performance ................................ ..408
`P. Tirumalai, D. Greenley, B. Beylin, and K. Subramanian
`_
`
`UltraSPARC—IFM: The Advancement of U1traComputing .................................................... ..417
`G. Goldman and P. Tirumalai
`
`Java” and Hotiavaz A Comprehensive Overview ............................................................... ..424
`S. Shaio, A. van Hajj”, and H. Jellinek
`
`Session 25: Desktop Color — From Eye to Paper
`Chair: Allen Baum —Apple Computer
`
`'
`
`Digital Cameras and Electronic Color Image Acquisition ...................................................... ..43l -
`J. Dalton
`.
`
`Electronic Color Printing Technology ........................................................
`GK. Smrkweather
`
`......................... ..435
`-
`
`ColorSyncTM: Synchronizing the Color Behavior of Your Devices ...................................
`W~L. Chu and S. Swen
`
`.
`
`. . 440
`
`Session 26: Architecture" of Workflow Management Systems
`
`Chair: Berthold Reinwald — IBM Almaden Research Center
`
`Object—Oriented Workflow Technology in InConcert ...............
`SR’. Sarin
`.
`'
`
`...............
`
`.........
`
`............... ..446
`‘
`
`Structured Workflow Management with Lotus Notes Release 4 .......................................... . .451
`B. Reinwald and C. Mohan
`
`An Architecture for Large—Scale Work Management Systems ...................................... . .'........_458
`M. Beizer
`-
`.
`
`Session 27: “Toy Story”
`
`Chair: Darrell Long — University of California, Santa Cruz
`
`The Making of Toy Story ...................................................................................................... ..463
`M. Henne, H. Hickel, E. Johnson, and S. Konishi
`
`Additional Paper: The following paper was presented as the last paper in Session 12
`
`Single Chip MPEG2 Decoder with Integrated Transport deocder for Set—top Box _................. .
`J. Fandrianto
`'
`'
`
`. 469
`
`Author Index ..................................................................
`
`................................................. ..473
`
`Page 1 1 of 23
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`Petitioners HTC & LG - Exhibit 1005, p. 11
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`,3
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`
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`
`
`-,..:ozWrfi">323.-’.7»«.£:-;\.~f3.;.___.,4..;$.é.»5i__;.....
`
`
`
`Petitioners HTC & LG - Exhibit 1005, p. 11
`
`

`
`An Architectural Overview of the Programmable
`Multimedia Processor, TM-1
`
`Selliah Rathnam, Gert Slavenburg
`
`Philips Semiconductors
`811 E. Arques Avenue, Sunnyvale, CA 94088
`
`_
`
`ABSTRACT
`
`can range from low-cost, stand alone systems such as
`video
`ones to programmable, multipurpose plug-in
`cards jgar traditional computers.
`
`_ INTRODUCTION
`1.0
`TM-1 is a buildin -block for hi h— erformance multi-
`media a plications t at deal with ig -quality video and
`audio.
`-1 easil
`irn lernents o ular multimedia stan-
`dards such as MP G— and MP
`-2, but its orientation
`around a powerful general-purpose CPU makes it capa-
`ble of implementing a variety of multimedia algorithms,
`whether open or proprietary.
`
`More than just an inte rated microprocessor with up-
`usual penpherals, the T -1 m.1C1'Opl‘0CeSS01' IS a fluid
`
`
`
`3'nz:5*’a\o
`
`_
`.~
`
`I20 Interface
`2
`-' 1st
`
`Synchronous :>’«
`-
`‘*2
`Sena.
`.
`..
`
`V.34 or ISBN
`Front End
`Down at up scaling
`YUV —> HGE
`
`Huflman decoder
`Slice-at—a-time
`MPEG4 8. 2
`
`CCIHSO1/656
`YUV 4:222
`
`CC|Fl6D1;'656
`YUV 4:222
`
`I S DC-+80 kHz
`Stereo digital audio
`
`I S D0-80 kHz
`Stergo dlital audio
`
`I20 bus to
`camera, etc.
`
`Image
`coprocessor
`
`PCE Bus
`
`319
`
`‘
`
`
`
`jthe irst in afamily ofprogrammable multimedia
`cessor fiiom the Trimedia product group of Philips
`m onductors. This "C” programmable processor
`" high performance VLIW-CPU core with video and
`eripheral units designed to support the popular
`'ltim'eo'ia applications. TM—l
`is designed to concur-
`§;g[y.p'rocess video, audio, graphics, and communica-
`'
`Etta. The VLIW—CPU core is capable of executing a
`.. rmum of twenty seven operations per cycle, and the
`"ned execution rate is about five operations per cy-
`.o the tuned a plications. The audio unit easily han-
`s'dfi”erent au io formats including the 16-bit stereo
`-The video unit is capable o processing different
`a_l_ RGB pixelformats with orizontal and vertical
`d color space conversion. TM-I applications
`
`mg‘
`
`Petitioners HTC & LG - Exhibit 1005, p. 12
`
`

`
`CCli'-l601l65t3
`YUV 4:2:2
`
`Stereo
`Audio In
`
`CCIHEOUGSB
`YUV 412:2
`
`Stereo
`Audio Out
`
`Front End
`
`v.34 Modem
`
`Figure 2. TM-1 system connections. A minimal
`T -1 system requires few supporting compo-
`nents.
`..
`
`com uter system controlled by a smail real—time OS ker-
`nel t at runs on the VLIW processor core. TM-l contains
`a CPU, a hi h-bandwidth internal bus, and internal bus-
`mastering D A peripherals.
`
`TM—1 is the first member of a famil of chips that will
`carry investments in software forwar
`in time. Compati-«
`bility between family members is at the source~code lev—
`el; binary compatibility between family members is not
`guaranteed. Al
`family members, however, will be able
`to
`erform the most important multimedia functions,
`sue as running MPEG-2 software.
`
`Defining software com atibility at the source-code
`level
`ives Philips the free cm to strike the optimum bal-
`ance etween cost and performance for all the chips in
`the TM—1 family. Powerful compilers ensure that pro-
`grammers seldomly need to resort to non— ortable as-
`sembler
`rogramming. Programmers use T —1’s power-
`ful low— evel operations from source code; these DSP—
`like operations are invoked with a familiar function-call
`syntax. Trimedia also
`rovides hand—coded and tuned
`multimedia libraries w ich can be used to increase the
`performance of the multimedia applications.
`
`As the first member of the family, TM—1 is tailored for A
`use in PC-based ap lications. Because it is based on a
`generaclfpurpose C
`, TM—1l can serve as a(r:nulti—ft£i1nc;
`tion P enhancement vehic e. Typically, a P must c
`with inulti—standard video and audio streams, and users
`desire both decompression and compression,_if possible.
`While the CPU chips used in _PCs are becoming ca able
`of low-resolution real—tim_e video decompression,
`igh»
`‘§11‘3i‘i“”i§"§'iifi ?ii‘i°§i‘1§‘§§i°“i$.'ifi駰.lE§§?‘3§1§§n’“ {E31
`their systems prov_ide live video and’audio without sacri-
`ficing the responsiveness of the system.
`
`TM-l enhances a PC system to rovide real—time mul-
`timedia, and it does so with the a vantages of a special-
`pugpose, embedded soiution—low cost and chip count—
`an the advantages of a eneral-purpose rocessor—re—
`programmability. For P
`ap lications, M—l far sur-
`passes the capabilities of
`ixed-function multimedia
`c ips.
`-
`
`Other Trimedia family members will have different
`sets of interfaces appro riate for their intended use. For
`example, a TM—] c ip fiir a cable~TV decoder box would
`eliminate the video—in interface.
`
`2.0
`
`TM-1 CI-I[P OVERVIEW
`
`The key features of TM—1 are:
`
`eneral— urpose VLIW proces~
`- A very powerful,
`sor core that coor 'nates al on—cliip activities. In
`addition to irnplementin the non—trivial parts of
`multimedia algorithms,
`is
`rocessor runs a small
`real-time operating system at is driven by inter-
`rupts from the other units.
`- DMA—driven multimedia input/output units that
`operate independently and that properly format
`data to make processing efficient.
`- DMA-driven multimedia coprocessors that operate
`independently and erform_ operations specific to
`important multime ia algorithms.
`system that
`- A high-performance bus and memo
`provides communication between T —l s process
`ing units.
`
`Figure 1 shows a block diagram of the TM—1 chip. The
`bulk of a TM~l system consists of the TM-1 micro ro~
`cessor itself, a block of synchronous DRAM (SDRAIl.\/I),
`and minimal external circuitry to interface to the incom~
`ing and/or outgoing multimedia data streams. TM—1 can
`gluelessly interface to the standard PCI bus for ersonal-
`computer-based a plications; thus, TM=l can e placed
`directly on the P mainboard or on a plug—in card.
`
`Figure 2 shows a possible TM—1 system application. A
`video-in ut stream, if present, might come directly from
`a CCIR 01-compliant digital video camera chip in YUV
`422 format; the interface is glueless in this case. A non-
`standard camera chi
`can be connected via a video de-
`coder chi
`(such as t e Phili
`s SAA711l). A CCIR 601
`out ut vi eo stream is provi ed directly from the TM—]
`to rive a dedicated video monitor. Stereo audio input
`and output reguire external ADC and DAC support. he
`operation of
`e video and audio interface units is highly
`customizable through programmable parameters.
`
`The glueless PCI interface allows the TM—1 to display
`video via a host PC’s video card and to"
`lay audio via a
`host PC’s sound hardware. The Image oprocessor pro-
`vides dis lay support for live video in an arbitrary num-
`ber of ar itrarily overlapped windows.
`
`Finally, the V.34 interface requires only an external
`modem front-end chip and phone line interface to pro-
`vide remote communication support. The modern can be
`used to connect TM—1—based systems for video phone or
`video conferencing applications, or it can be used for
`general—purpose data communication in PC systems.
`
`3.0 BRIEF EXAMPLES OF OPERATION
`
`The ke to understanding TM— 1’ operation is observing
`that the . PU and peripherals are time—share_d and that
`communication between units is through SDRAM mem-
`
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`Cry. The CPU switches from one task to the next; first it
`decompresses a video frame, then it decompresses a slice
`of the audio stream, then back to video, etc. As neces-
`Sal‘
`, the CPU issues commands to the peripheral units. to
`orc estrate their operation.
`
`the PCI bus for archival on local mass storage, or the host
`can transfer the compressed video over a network, such
`as ISDN. The data can also be sent to a remote system us-
`ing the integrated V34 interface to create, for example,
`a video phone or video conferencing system.
`
`The TM~l CPU can -enlist the ICP and video-in units
`to help with some of the straightforward, tedious tasks
`associated with video processing. The function of these
`units is programmable. For example, some video streams
`are——o1' need to be—scaled horizontally, so these units
`can handle the most common cases of horizontal down-
`and up—scaling without
`intervention from the TM—l
`CPU.
`
`3.1 Video Decompression in a PC
`A typical_mode of operation for a TM—l s stem is to
`serve -as a video-decom ression engine on a CI card in
`a PC. In this case, the C doesn’t know the TM—l has a
`powerful, general-purpose CPU; rather, the PC just treats
`the hardware on the PCI card as a “black-box” engine.
`
`. Video decompression begins when the PC operating
`5 stem hands the TM—l a pointer to compressed video
`ata in the PC’s memo
`(t e details of the communica-
`tion protocol are typica ly handled by a software driver
`insta led in the PC s operating system).
`
`The TMvl CPU fetches data from the compressed vid-
`eo stream via the PCI bus, decompresses frames from the
`video stream, and places them into local SDRAM. De-
`. compression Ina be aided by the VLD (variable—length
`decoder) unit, w ich implements Huffman decoding and
`is controlled by the TM-l CPU.
`
`When a frame is ready for dis lay, the TM-l CPU
`
`gives the ICP (image coprocessorfa display command.
`
`he ICP then autonomously fetches the decom ressed
`frame data from SDRAM and transfers it over
`e PCI
`bus to the frame buffer in the PC’s video dis Ia card (or
`the frame buffer in PC system memory if t e C uses a
`UMA (Unified Memory Architecture) frame buffer).
`The ICP accommodates arbitrary window size, position,
`and overlaps.
`
`3.2 Video Compression
`
`Another typical application for TM-l is in video com-
`pression. In this case, uncompressed video is usually
`supplied directly to the TM-1 system via the video—in
`unit. A camera chip connected direetl
`to the video-in
`unit supplies YUV data in eight-bit,
`12:2 format. The
`video—in unit takes care of sampling the data from the
`camera chip and demultiplexing the raw video to
`§/DRAM in three separate areas, one each for Y, U, and
`
`When a complete video frame has been read -from the
`camera chip b the video—in unit, it interrupts the TM-1
`CPU. The CPU compresses the video data in software
`(using a set of powerful data—para1lel operations) and
`Writes
`the compressed data to a separate area of
`SDRAM.
`
`Since the powerful, general—purp)ose TM-1 CPU is
`available, the corn ressed data can e encrypted before
`being transferred or security.
`
`4.0 VLIW CORE AND PERIPHERAL
`UNITS
`
`4.1 VLIW Processor Core
`
`The heart of TM—l is its powerful 32-bit CPU core.
`The CPU implements a 32~bit linear address space and
`128, fully general—purpose 32-bit registers. The registers
`are not separated into banks; any operation can use any
`register for any operand.
`
`The core uses a VLIW instruction—set architecture and
`is fully eneral-purpose. TM—l uses a VLIW instruction
`length t at allows up to five simultaneous operations to
`be issued. These operations can target any five of the 27
`functional units in the CPU, including inte er and float-
`ing-point arithmetic units and data—par
`el DSP—like
`units.
`
`Instruction Cache (32Kb)
`
`Instr. Fetch Buffer
`
`Decompression Hardware
`
`Issue Register ( S Ops )
`
`Operation Routing Network
`
`Execution Unit ( 27 Functions )
`
`Register Routing and Forwarding Network
`
`Register File ( 128 X 32 )
`
`The compressed video data can now be disposed of in
`any of several ways. It can be sent to a host system over
`
`Figure 3. VLIW Processor Core and Instruction
`Cache.
`
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`
`Although the processor core runs a tiny real—time op-
`erating system to coordinate all activities in the TM—l
`s stem, t e processor core is not intended for true gener-
`a —purpose use as the only CPU in a computer system.
`For example, the processor core does not irn lement vir-
`tuai memory address translation, an essentia feature in a
`general—purpose computer system.
`
`TM—1 uses a VLIW architecture to maximize roces—
`sor throughput at the lowest possible cost. VL
`archi-
`tectures have performance exceeding that of superscalar
`genera}-purpose CPUs without the extreme complexity
`of a superscalar implementation. The hardware saved by
`eliminating superscalar logic reduces cost and allows the
`integration of multimedia—specific features that enhance
`the power of the processor core.
`
`The TM—l operation set includes all traditional micro-
`processor operations. In addition, multimedia-specific
`operations are included that dramatically accelerate stan-
`dard video compression and decompression algorithms.
`As just one of the five operations issued in a single TM-
`1 instruction, at single special or “custom” operation can
`implement up to
`1 traditional microprocessor o era-
`tions. Multimedia-specific operations combined wit
`the
`VLIW architecture result in tremendous throughput for
`multimedia applications.
`
`Internal “Data Highway” Bus
`4.2
`The internal data bus connects all internal blocks to-
`ether and provides access to internal control registers
`gin each on—chi peripheral units), external SDRAM, and
`the external P I bus. The internal bus consists of sepa-
`rate 32-bit data and address buses, and transactions on
`the bus use a block~transfer protocol. Peripherals can be
`masters or slaves on the bus.
`
`_ Access to the internal bus is controlled by a central arv
`biter, which has a request line from each otential bus
`master. The arbiter is configurable in a num er of differ-
`ent modes so that the arbitration al orithm can be tai-
`lored for different ap lications. Perip eral units make re-
`quests to the arbiter (gr bus access, and dependin on the
`arbitration mode, bus bandwidth is allocated to t e units
`in different amounts. Each mode allocates bandwidth
`differently, but each mode guarantees each unit a mini-
`mum bandwidth and maximum service latency. All un-
`used bandwidth is allocated to the TM-1 CPU.
`
`The bus allocation mechanism is one of the features of
`. TM—l that makes it a true real—time system instead ofjust
`a highly integrated microprocessor with unusual periph-
`era s.
`
`4.3 Memory and Cache Units
`TM—1’s memory hierarchy satisfies the low cost and
`high bandwidth requirement of multimedia markets.
`Since multimedia video streams can require relatively
`large temporary storage, a significant amount of DRAM
`is required.
`
`TM—l has a glueless interface with s nchronous
`DRAM (SDRAM) or
`synchronous grap ics RAM
`
`(SGRAM), which provide higher bandwidth than the
`standard DRAM. As the SDRAM has been supported by
`major DRAM vendors,
`the competition among those
`vendors will kee the SDRAM rice in par