Case IPR2016-00825
`Petition for Inter Partes Review of Patent RE43,729
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`UNITED STATES PATENT AND TRADEMARK OFFICE
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`BEFORE THE PATENT TRIAL AND APPEAL BOARD
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`ARM, Ltd.
`Petitioner
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`GODO KAISHA IP BRIDGE 1
`Patent Owner
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`Case IPR2016-00825
`Patent No. RE43,729
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`PETITION FOR INTER PARTES REVIEW OF
`U.S. PATENT NO. RE43,729
`UNDER 35 U.S.C. §§ 311-319 AND 37 C.F.R. § 42.100 ET SEQ.
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`
`Mail Stop: Patent Board
`Patent Trial and Appeal Board
`United States Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
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`Case IPR2016-00825
`Petition for Inter Partes Review of Patent RE43,729
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`TABLE OF CONTENTS
`INTRODUCTION ............................................................................................. 1
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`I.
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`II. BACKGROUND ................................................................................................ 4
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`A. The Technology Of The Challenged Claims And State Of The Prior Art.... 4
`B. Summary of the Prosecution History of the ‘729 Patent. ............................. 5
`III. REQUIREMENTS FOR INTER PARTES REVIEW UNDER 37 C.F.R. §
`42.104 ................................................................................................................10
`
`A. Grounds for Standing under 37 C.F.R. § 42.104(a) ....................................10
`B. Identification of Challenge under 37 C.F.R. § 42.104(b) ...........................11
`1. Grounds for Challenge .......................................................................11
`2. How the Challenged Claims Are to be Construed under 37 C.F.R. §
`42.104 (b)(3) .....................................................................................................15
`3.
`Level of a Person Having Ordinary Skill in the Art ..........................19
`IV. THERE IS A REASONABLE LIKELIHOOD THAT THE
`CHALLENGED CLAIMS ARE UNPATENTABLE ..................................19
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`A. Van Hook Anticipates Claim 21 and 22 under at least 35 U.S.C. 102(e)
`And / Or Alone Renders Claims 21 and 22 Obvious. .................................20
`B. Van Hook in View of the Knowledge of One Skilled in the Art, as
`Described in Patterson, Renders Claims 21 and 22 Obvious Under 35
`U.S.C. § 103(a)............................................................................................38
`C. The MMX References Render Claims 21 and 22 Obvious Under 35 U.S.C.
`§ 103(a). ......................................................................................................43
`D. The Bases for Invalidity Are Not Duplicative, and Petitioner Requests the
`Board to Consider all Bases for Invalidity. .................................................55
`V. SECONDARY CONSIDERATIONS ............................................................57
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`VI. NOTICES, STATEMENTS AND PAYMENT OF FEES UNDER 37
`C.F.R. § 42.8(A)(1) ...........................................................................................57
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`A. Real Party in Interest under 37 C.F.R. § 42.8(b)(1) ....................................57
`B. Related Matters Under 37 C.F.R. § 42.8(b)(2) ...........................................58
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`C. Lead and Back-Up Counsel Under 37 C.F.R. § 42.8(b)(3) ........................59
`D. Service Information Under 37 C.F.R. § 42.8(b)(4) .....................................59
`E. Fees under 37 C.F.R. § 42.103 ....................................................................59
`VII. CONCLUSION ...............................................................................................59
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`Petition for Inter Partes Review of Patent RE43,729
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`PETITIONER’ EXHIBIT LIST
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`Exhibit No.
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`Description
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`Exhibit 1001 U.S. Pat. No. 5,847,729 (the ‘729 patent)
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`Exhibit 1002 U.S. Pat. No. 5,734,874 to Van Hook (“Van Hook”) based upon
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`application Ser. No. 08/236,572, filed April 29, 1994.
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`Exhibit 1003 U.S. Pat. No. 5,822,232 to Dulong (“Dulong”) based upon
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`application Ser. No. 08/609,601, filed March 1, 1996.
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`Exhibit 1004
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`Intel MMX Technology Developers Guide, March 1996
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`Exhibit 1005
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`Intel Architecture MMX™ Technology Programmer’s Reference
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`Manual, March 1996, Order No. 243007-002.
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`Exhibit 1006 MMX Technology Extension To The Intel Architecture, Peleg et
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`al., IEEE Micro, Volume 16, Issue 4, August 1996, Page 42-50,
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`IEEE Computer Society Press, Los Alamitos, CA, USA.
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`Exhibit 1007
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`Patterson et al., Computer Organization & Design The Hardware
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`Software Interface, Morgan Kaufman Publishers, Inc. (1994)
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`(“Patterson”) (excerpted).
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`Exhibit 1008 U. S. Pat. No. 4,722,066 to Armer (“Armer”) based upon
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`application Ser. No. 06/760,382, filed July 30, 1985.
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`Exhibit 1009 U. S. Pat. No. 4,519,031 to Magar (“Magar) based upon
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`application Ser. No. 06/350,953, filed February 22, 1982.
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`Exhibit 1010 U.S. Pat. No. 5,801,977 to Karp (“Karp”) based upon application
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`Ser. No. 08/826,817, filed April 7, 1997 and claiming priority to
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`an application filed January 17, 1995
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`Exhibit 1011 Complaint in Case No. 2:16-cv-00134-JRG-RSP in the Eastern
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`District of Texas
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`Exhibit 1012
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`File History of application no. 10/366,502 (now U.S. Pat. No.
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`RE39,121) (excerpted)
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`Exhibit 1013
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`File History of application no. 11/016,920 (now U.S. Pat. No.
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`RE43,145) (excerpted)
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`Exhibit 1014
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`File History of application no. 13/092,453 (now U.S. Pat. No.
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`RE43,729) (excerpted)
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`Exhibit 1015
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`IEEE Std 100-1996, The IEEE Standard Dictionary of Electrical
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`and Electronics Terms, Published by the Institute of Electrical
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`and Electronics Engineers, Inc. (approved December 10, 1996)
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`(excerpted).
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`Exhibit 1016 March 5, 1996 Intel MMX Press Release.
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`Exhibit 1017 Declaration of Internet Archive Manager, Chris Butler, with
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`attached Exhibit A containing Internet Archive 1996 Printout of
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`Intel Architecture MMX™ Technology, Programmer's Reference
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`Manual (March 1996) and Internet Archive 1996 Printout of
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`Intel MMX Technology Developers Guide, March 1996
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`Exhibit 1018 University of Berkeley Card Catalog entry for Patterson (Exhibit
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`1007)
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`Exhibit 1019 U.S. Pat. No. 5,896,493 to Rao (“Rao”) based upon application
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`Ser. No. 08/785,374, filed January 17, 1997
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`Exhibit 1020 U.S. Pat. No. 3,930,232, to Nissen (“Nissen”) based upon
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`application Ser. No. 04/418641, filed November 23, 1973
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`Exhibit 1021 Declaration of V. Thomas Rhyne
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`Exhibit 1022
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`Printout from IEEE database identifying citations to Patterson
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`(Exhibit 1007)
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`Exhibit 1023 Copy of Exhibit 1020 from IPR2015-00081 (excerpts to
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`Patterson, Exhibit 1007)
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`Case IPR2016-00825
`Petition for Inter Partes Review of Patent RE43,729
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`I.
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`INTRODUCTION
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`Petitioner ARM, Ltd. (“ARM”) requests inter partes review of claims 21-22
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`(the “challenged claims”) of U.S. Pat. No. RE43,729 (the “‘729 patent”). The
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`challenged claims are unpatentable because the ‘729 patent merely applies known
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`circuitry to perform a known function called “saturation,” which is described
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`below. The prior art and the ‘729 patent implement the claimed saturation function
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`using identical logical circuitry (with more detail in the prior art). During the
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`prosecution of the challenged claims, the Patent Owner1 overcame the prior art by
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`arguing and claiming that this saturation circuitry must “operate in a single cycle.”
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`The fundamental problems with the Patent Owner’s argument are: (a)
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`performing saturation in a single cycle is not novel and (b) the ‘729 patent has no
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`discussion or disclosure of the saturation circuitry operating in “one cycle.” The
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`‘729 patent does not recite the word “cycle” nor does it contain any discussion
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`whatsoever of the concept of “cycles” or even the concept of clocking which can
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`be related to cycles. When challenged during prosecution to provide support for
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`the “one cycle” limitation in at least five separate rejections occurring over six
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`years, the Patent Owner could point only to a standard five-stage RISC2 pipeline
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`1 “Patent Owner” refers to the current and previous assignees as the current
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`assignee is bound by the representations made to the PTO by any prior assignee.
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`2 RISC stands for “Reduced Instruction Set Computer.” “CISC” stands for
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`diagram (long known in the prior art) that contained a stage called the “execute
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`stage” which purportedly implied a “one cycle” execution.
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`The Patent Owner’s argument created at least two separate problems with
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`the disclosure. First, the ‘729 patent does not link pipeline stages and cycles, and
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`the Patent Owner was forced to expressly state that such a link would come from
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`the knowledge of one skilled in the art – which, of course, is equally applicable to
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`such diagrams found in the prior art. Second, disclosures of five-stage processor
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`pipelines with “execution” stages long predate the ‘729 patent. If the ‘729 patent
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`disclosure of a five-stage pipeline sufficiently describes the “one cycle” limitation
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`(as was successfully argued by the Patent Owner to overcome the new matter
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`rejections), then the prior art featuring five-stage pipelines with execution stages
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`necessarily does so as well. The prior art need only disclose as much as the ‘729
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`patent to be invalidating. See SRI Int'l, Inc. v. Internet Sec. Sys., 511 F.3d 1186,
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`1194 (Fed. Cir. 2008) (recognizing that the prior art need only have the same
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`“level of technical detail” as the asserted patent to be invalidating).
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`The Petition presents four invalidity grounds detailed below. First, U.S. Pat.
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`No. 5,734,874 (“Van Hook”) (Ex. 1002), which predates the ‘729 patent by
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`several years, invalidates claims 21 and 22 of the ‘729 patent. Van Hook describes
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`a new processor instruction called the FPACK16 instruction. As shown below, the
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`“Complex Instruction Set Computer.” Ex. 1013 at 1013-0028.
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`FPACK16 instruction converts signed 16-bit input data to unsigned 8-bit output
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`data. During the conversion, if the result is less than 0, then the result is saturated
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`to 0. If, alternatively, the result is too large to fit in the 8-bit result, then the result
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`is saturated to 255 (which can be represented in hexadecimal format as “0xFF”),
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`which is the largest value that can be represented in an 8-bit result. If the result
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`falls between the maximum (255) and minimum (0) then it is passed through
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`unchanged. As shown below, Van Hook teaches the same logical circuit that the
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`‘729 patent uses to perform the saturation (with greater detail). Therefore, if the
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`‘729 patent adequately teaches performing these operations in “one cycle,” then so
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`does Van Hook and Van Hook either anticipates (ground one), or renders obvious
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`(ground two), claims 21 and 22 of the ‘729 patent. Invalidity ground three is Van
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`Hook combined with the Patterson textbook (Ex. 1007) which shows a five-stage
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`pipeline with a single “execute stage,” like the Patent Owner cited as disclosure for
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`the “one cycle” limitation during prosecution.
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`The fourth invalidity ground relies upon four Intel-related documents from
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`1996 that describe the operation of the PACKUS instruction that Intel included in
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`its MMX instruction set. Collectively, these are referenced to herein as the “MMX
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`References.” The MMX References each show relevant aspects of the PACKUS
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`instruction. Specifically, the PACKUS instruction converts a signed 16-bit integer
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`word into an unsigned 8-bit byte value. During the conversion, if the result would
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`be less than 0, then the result is saturated to 0. If, alternatively, the resulting value
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`is too large to fit in the 8-bit result memory location, then the result is saturated to
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`255 (or, in hexadecimal, 0xFF), which is the largest value that can be represented
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`in an 8-bit unsigned result. The MMX References confirm that the PACKUS
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`instruction executes in one cycle. Indeed, one of the MMX references taught this
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`limitation in haec verba: “[o]n the first implementation, a Pentium processor, all
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`MMX instructions with the exception of the multiply instructions execute in
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`one cycle.” Ex. 1006 at 0002 (p. 43) (emphasis added).
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`Petitioners respectfully request that inter partes review be instituted for
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`claims 21-22 of the ‘729 patent and that these claims be cancelled.
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`II. BACKGROUND
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`A. The Technology Of The Challenged Claims And State Of The Prior Art.
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`The ‘729 patent is entitled: “[P]rocessor which can favorably execute a
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`rounding process composed of positive conversion and saturation calculation.” Ex.
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`1001, Title. The ‘729 patent generally relates to an operation known as
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`“saturation” in computer processors. Id. at 2:41-43. “Saturation” is generally the
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`process of ensuring that a value that is calculated in a processor is not too large nor
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`too small to be accurately stored by the number of bits used to store and represent
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`such values, such as registers. E.g., Ex. 1001 at 2:41-53. “Saturation” may also be
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`referenced in the art as “rounding,” “clipping” or “clamping.” For example, when
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`a processor is adding multiple 8-bit numbers together, the result might require
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`more than 8 bits to represent the total. In this situation, the result is “saturated” –
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`meaning that the result is set to the maximum value (e.g., 255) that can be
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`represented in the available number of bits (e.g., 8). Exhibits 1008 and 1009 show
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`examples of how such overflow or underflow conditions might result in saturation.
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`The Karp patent (U.S. Pat. No. 5,801,977) (cited during the prosecution of the ‘729
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`patent) describes saturation of an input value ix as (referenced as “clipping”):
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`
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`Ex. 1010 at 0009, 2:1-5.
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`Claims 21 and 22 of the ‘729 patent seek to build on this well-known
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`concept by asserting that this saturation operation be “performed within one
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`cycle.” However, as discussed and shown below, claims 21 and 22 do not add
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`anything that was not already well-known in the art.
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`B. Summary of the Prosecution History of the ‘729 Patent.
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`U.S. Pat. App. No. 13/092,453, which resulted in the ‘729 patent, was filed
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`on April 22, 2011 and claims priority through a chain of applications to application
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`No. 08/980,676 filed on December 1, 1997.
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`The Patent Owner introduced the “one cycle” limitation in the prosecution of
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`the grandparent application 10/366,502, filed February 13, 2003 (now U.S. Pat.
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`No. RE39121) (the “’502 Application”). On February 13, 2004, the Patent Owner
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`submitted a Preliminary Amendment with claims that included the “within one
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`cycle” limitation. Ex. 1012 at 1012-0002 - 0004, pp. 2-3 (claims 67, 68, and 72).
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`On September 14, 2004, the Examiner rejected this “within one cycle” as
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`adding new matter:
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`The added material which is not supported by the original disclosure is as
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`follows: The recitation in claims 53-62, 67-68, and 72 that the operation
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`occurs “within one cycle”. The originally filed specification gives no
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`indication that the operation happens within one cycle, and as such, to
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`claim that it occurs in one cycle is an addition of new matter to the
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`specification.
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`Ex.1012 at 1012-0025 - 0026, pp. 3-4. The Examiner also held that the claims
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`containing the “within one cycle” limitation were invalid over various references.
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`Id. at 1012-0028, 0032, 0033, 0038 (p. 6, 10, 11 and 16).
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`On March 15, 2005, the Patent Owner cited only the following passage as
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`support for the “one cycle” limitation (seemingly describing an interview with the
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`Examiner): “Applicants further directed the Examiner to Figure 12B for providing
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`support for performance of operations in one cycle.” Ex. 1012 at 1012-0057. The
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`disputed claims were cancelled and moved to divisional application 11/016,920
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`(the ‘920 application) that is the parent to the ‘729 patent via a preliminary
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`amendment filed on December 21, 2004. Ex. 1013 at 1013-0243, (e.g., claim 21).
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`On October 21, 2008, the Examiner again rejected the “within one cycle”
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`limitation as adding new matter, noting that “the specification as originally filed
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`makes absolutely no mention of the operation being performed in one cycle.” Ex.
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`1013 at 1013-0213 – 0214, pp.4-6 (emphasis added). The Examiner also rejected
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`the claims as obvious. Id. at 1013-0021 – 0035, pp. 12-26.
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`The Patent Owner on November 13, 2009, submitted an Amendment with
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`the following arguments related to the “within one cycle” limitation:
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`Although the specification does not directly contain the phrase “one cycle,”
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`as recited in the claims, the recited limitations can be directly derived from
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`the disclosure provided in FIGS. 12A and 12B，and col. 11, lines 1-20 and
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`col. 19, line 50 to col. 20, line 16 of [the parent] U.S. Pat. No. 6,237,084.
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`To one of skill in the art, it would have been understood that each interval
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`in the horizontal direction in FIGS. 12A and 12B represents one cycle.
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`Further, from the explanation “that the processing can be seen to be
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`performed without confusion in the pipeline" (col. 20, lines 6-8) and the
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`subsequent discussion at col. 20, lines 9-16，it would have been clear to
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`those skilled in the art that the processing is executed cycle by cycle, such
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`that the recited operations are performed “within one cycle” as recited in
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`the claims.
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`Id. at 1013-0192, p. 20. On December 4, 2009, the Examiner once again rejected
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`the Patent Owner’s purported support for the “within one cycle” limitation in an
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`extensive discussion. Id. at 1013-0129 - 0133, pp. 3-7.
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`During an interview held on April 21, 2010, the Patent Owner presented
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`extensive arguments for support for the “within one cycle” limitation and that the
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`Examiner indicated that he would withdraw the new matter rejection if these
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`arguments were made of record in a response. Id. at 1013 - 1022 (p. 2).
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`On May 10, 2010, the Patent Owner subsequently submitted arguments that
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`resulted in the Examiner withdrawing the new matter rejections on the “within one
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`cycle” limitation. Id. at 1013-0094 - 0099, pp. 20-24. These arguments focused on
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`Figure 12B and its associated text.
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`The Patent Owner argued that Figure 12B shows a standard RISC pipeline
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`diagram – which has been long known in the art prior to the ‘729 patent:
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`The text associated with Fig. 12B merely describes the well-known
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`operation of a five-stage pipeline:
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`FIG. 12B shows the execution of the matrix multiplication subroutine
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`according to a pipeline process composed of five stages which namely are
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`an instruction fetch stage, an instruction decoding stage, an execution
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`stage, a memory access stage, and a register write stage. … After this, the
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`execution stage of instruction 10:“MCSST D1” is performed at the same
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`time as the memory access stage of instruction 9:“BCS LP1_NEXT”. The
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`positive conversion saturation calculation processing for the matrix
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`multiplication result of one row of elements by one column of elements is
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`performed when the instruction located before it is in the memory access
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`stage ….
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`Ex. 1001 at 19:50-20:6; see also id. at 11:9-19. According to the Patent Owner,
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`“Figure 12B illustrates a pipeline with a latency of 5 cycles and a throughput of 1
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`cycle.” Ex. 1013 at 1013-0095, p. 21.
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`The Patent Owner argued specifically “Diagrams for illustrating pipelined
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`execution, such as FIG 12B of this application, were used extensively in the art,
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`and accordingly FIG 12B would have been understood by those of skill in the art
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`that the recited operations are executed in a single cycle, as recited in claims 53
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`and 54.” Id. at 1013-0096, p. 22 (emphasis added).
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` After this representation by the Patent Owner, the Examiner did not assert
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`the new matter rejections related to the “one cycle” limitation in the next office
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`action on June 17, 2010. Id. at 1013-0067 - 0073 (no new matter rejection).
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`The Patent Owner subsequently filed application 13/092,453, which ripened
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`into the challenged ‘729 patent. Claims 21 and 22 (presently challenged) were
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`added by an amendment dated March 26, 2012 and both recited that the “rounding
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`… is performed within one execution cycle.” Ex. 1014 at 1014-0017. The
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`Examiner rejected claims 21 and 22 over the prior art. Id. at 1014-0034. After an
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`interview (id. at 1014-0044), the claims were amended to their now-issued form.
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`Id. at 1014-0048. The Patent Owner did not explain the deletion of “execution”
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`from the “one execution cycle.” Id. at 1014-0048 – 0051. Claims 21 and 22
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`subsequently were allowed on October 5, 2012. Id. at 1014-0056.
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`III. REQUIREMENTS FOR INTER PARTES REVIEW UNDER 37 C.F.R.
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`§ 42.104
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`A. Grounds for Standing under 37 C.F.R. § 42.104(a)
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`
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`Petitioner certifies pursuant to 37 C.F.R. § 42.104(a) that the ‘729 patent is
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`available for inter partes review, and that no Petitioner is barred or estopped from
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`requesting inter partes review based on the grounds herein. Petitioner certifies that
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`(i) no Petitioner owns the ‘729 patent; (ii) no Petitioner has filed a civil action
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`challenging the validity of any claim of the ‘729 patent, and (iii) no Petitioner has
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`been served with a complaint alleging infringement of the ‘729 patent.
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`B. Identification of Challenge under 37 C.F.R. § 42.104(b)
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`In view of the prior art detailed in the claim charts below, claims 21 and 22
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`of the ‘729 patent should be found to be unpatentable and cancelled. None of the
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`prior art references relied upon herein was considered during prosecution.
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`1. Grounds for Challenge
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`Petitioner requests inter partes review of the challenged claims in view of
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`the references, and on the grounds described, below:
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`1.
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`Claims 21 and 22 are anticipated under 35 U.S.C. §102(e) by U.S. Pat. No.
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`5,734,879 to Van Hook, et al. (“Van Hook”) (based upon application Ser. No.
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`08/236,572, filed April 29, 1994 and issued March 31, 1998). (Ex. 1002, which is
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`prior art under 35 U.S.C. §102(e)).
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`2.
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`3.
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`Claims 21 and 22 are rendered obvious by Van Hook alone.
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`Claims 21 and 22 are rendered obvious by Van Hook in view of Patterson
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`(1994) (Ex. 1007, which is prior art under 35 U.S.C. §102(b)). Multiple United
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`States patents issued prior to the date of the ‘729 application cite Patterson thus
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`confirming its public availability. E.g., U.S. Pat. No. 5,535,365 (filed on October
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`22, 1993 and issued on July 9, 1996); U.S. Pat. No. 5,555,387 (filed on June 6,
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`1995 and issued on September 10, 1996); U.S. Pat. No. 5,619,664 (filed on March
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`10, 1995 and issued on April 8, 1997); U.S. Pat. No. 5,630,157 (filed on October
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`25, 1994 and issued on May 13, 1997).
`
`
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`Additionally, IEEE publication records indicate that Patterson was cited by
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`at least 4 separate papers published by IEEE in 1994, by at least 10 separate papers
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`published by IEEE in 1995, by at least 7 separate papers published by IEEE in
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`1996 and by at least 9 separate papers published by IEEE in 1997. Exhibit 1022.
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`Exhibit 1018 contains the online card catalog excerpt from the University of
`
`California at Berkeley for Patterson. The catalog shows a “MARC” tag 005 with a
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`value of “19930817” indicating that this card catalog entry was last modified on
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`August 17, 1993. As of at least that date, Patterson was indexed and available in
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`that library. The PTAB has accepted Patterson in other Inter Partes Review
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`proceedings. See Exhibit 1023 (a copy of Exhibit 1020 from IPR2015-00081
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`showing that Patterson was available at the Library of Congress no later than
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`November 8, 1994); see also IPR2015-00061 (Exhibit 1020 therein); IPR2015-
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`00059 (Exhibit 1020 therein); IPR2015-02001 (Exhibit 1030 therein).
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`4.
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`Claims 21 and 22 are rendered obvious under 35 U.S.C. §103 by the
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`combination of references which describe the PACKUS instruction implemented in
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`Intel’s MMX instruction set: (1) U.S. Pat. No. 5,822,232 to Dulong et al.
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`(“Dulong”) based upon application Ser. No. 08/609,601, filed March 1, 1996 and
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`issued October 13, 1998 (Ex. 1003, which is prior art under 35 U.S.C. §102(e));
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`(2) Intel MMX Technology Developers Guide, March 1996 (Ex. 1004, which is
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`prior art under 35 U.S.C. §102(a) and (b)); (3) Intel Architecture MMX™
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`Technology Programmer’s Reference Manual, March 1996, Order No. 243007-
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`002 (Ex. 1005, which is prior art under 35 U.S.C. §102(a) and (b)); and (4) MMX
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`Technology Extension To The Intel Architecture, Peleg et al., IEEE Micro,
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`Volume 16, Issue 4, August 1996, Page 42-50, IEEE Computer Society Press, Los
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`Alamitos, CA, USA (Ex. 1005, which is prior art under 35 U.S.C. §102(a) and (b))
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`(collectively, the “MMX References”).
`
`
`
`The two Intel manuals (Exs. 1004 and 1005) were publicly available as of
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`March 1996. Both exhibits are dated March 1996. See Ex. 1004 at 0002 (header);
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`Ex. 1005 at 0001. Ex. 1004 states that the information is provided “for Developers
`
`and ISVs” and is distributed by “Intel® Developer Services” and lists the website
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`“www.intel.com/IDS.” Ex. 1004 at 0001. Ex. 1005 states: “Copies of documents
`
`which have an ordering number and are referenced in this document, or other Intel
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`literature, may be obtained from [Intel at the specified address and phone
`
`number].” Exhibit 1005 at 0002. On March 5, 1996, Intel announced the MMX
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`technology with a press release. Ex. 1016. That press release states that the
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`“Developers who are interested in obtaining additional information about MMX
`
`technology, including a Programmer's Reference Manual, should consult Intel's
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`site
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`on
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`the World Wide Web
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`at URL
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`http://www.intel.com/pc-
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`supp/multimed/mmx/index.htm.” Id. That these materials were available to third
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`parties is also evidenced by U.S. Pat. 5,896,493, which issued from U.S. Pat.
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`Application No. 08/785,374, filed in the United States Patent Office on January 17,
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`1997, which expressly incorporated by reference the documents of Ex. 1004 and
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`Ex.1005. See Ex. 1019 at 2:37-41 (“This processor and multimedia technology is
`
`described in the ‘Intel Architecture MMX(TM) Technology, Programmer’s
`
`Reference Manual,’ March 1996, and the ‘Intel MMX(TM) Technology.
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`Developer's Guide’ which are hereby incorporated by reference in their entirety.”),
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`
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`Also, as of 1996, Intel’s internet website included copies of both the MMX
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`Programmer’s Reference Manual (Ex. 1005) and the MMX Developers Guide (Ex.
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`1004). Copies of these manuals are available from the Internet Archive on
`
`webpages dated from 1996. Ex. 1017 at 1017-0005 – 0062 (a copy of Ex. 1005
`
`that was archived in 1996 from the publicly accessible Intel website); Id. at 1017-
`
`0063 - 0098 (a copy of Ex. 1004 that was archived in 1996 from the publicly
`
`accessible Intel website). The Intel website is an “on-line database or Internet
`
`publication that is considered to be ‘printed publication’ within the meaning of 35
`
`U.S.C. §§ 102(a) and (b).” MPEP § 2128; see also Voter Verified, Inc. v. Premier
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`Election Solutions, Inc., 698 F.3d 1374, 1380 (Fed. Cir. 2012) (online article that
`
`had been available on a public website by the critical date qualified as a “printed
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`publication” under 35 U.S.C. § 102(b)). Moreover, the PTO has long accepted the
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`Wayback Machine as a proper means for establishing a website as prior art. See
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`IPR2013-00086, Paper 66 at 29-31 (accepting web sites as printed publications and
`
`citing cases accepting Wayback Machine materials as sufficient authentication).
`
`
`
`Also, the Intel MMX Technology Developers Guide cross-references, and
`
`explains that additional information on the instruction format can be found in, the
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`“Intel Architecture MMXTM Technology Programmers Reference Manual, Intel
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`Corporation (Order Number 243007)” which is Exhibit 1005. Ex. 1004 at 0007.
`
`
`
`To the extent that Patent Owner attempts to challenge the public availability
`
`of either of Exs. 1004 or 1005, Petitioner has included a declaration from the
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`Internet Archive organization establishing the authenticity and date of the printouts
`
`in Exhibit 1017. Petitioner would also expect to introduce a declaration or
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`deposition testimony from Intel Corporation confirming the public availability of
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`Exhibits 1004 and 1005 prior to the earliest priority date of the ‘729 patent.
`
`
`
`Section IV identifies where the prior art teaches each element of claims 21
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`and 22. 37 C.F.R. § 42.104(b)(4). Exhibit numbers of supporting evidence relied
`
`upon to support the challenges and the relevance of the evidence to the challenges
`
`raised are in a table at p. iii and in Section III.B. 37 C.F.R. § 42.104(b)(5).
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`2.
`
`How the Challenged Claims Are to be Construed under 37 C.F.R. §
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`42.104 (b)(3)
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`In this proceeding, claim terms are given their broadest reasonable
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`interpretation consistent with the specification and prosecution history. See Office
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`Patent Trial Practice Guide, 77 Fed. Reg. 48756, 48766 (Aug. 14, 2012). The
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`broadest reasonable interpretation of the relevant claim terms is discussed below.
`
`Claim terms that are not addressed below are believed to require no additional
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`clarification for purposes of the present IPR.3
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`a. “operations which are performed in one cycle”
`
`Based upon the Patent Owner’s statements and positions taken during
`
`prosecution, this claim term should be construed to mean that the cited operations
`
`are performed within a single processor stage.
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`This claim term was a critical claim term during prosecution yet the
`
`specification does not provide any support or description of this term. As noted
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`above, the Examiner rejected the “within one cycle” limitation as unsupported by
`
`the specification in at least five separate rejections over a period of six years.
`
`As discussed above, the Patent Owner overcame the at least five new matter
`
`rejections after six years by stating unequivocally that pipeline diagrams, such as in
`
`Figure 12B of the ‘729 patent, would be understood to disclose single cycle
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`operation. See supra at 9-10. (discussing Ex. 1013 at 1013-0096, pp. 22).
`
`the Patent Owner’s express representations during
`If one accepts
`
`
`3 Petitioner does not acknowledge that any claim or claim term complies with 35
`
`U.S.C. § 112, through any construction for terms that follow, or otherwise.
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`prosecution, the ‘729 specification might be said to teach that elements 21(a)
`
`through (c) occur in the “execution stage.” This is wholly unsurprising and not
`
`novel because all of the arithmetic operations performed in a standard five-cycle
`
`RISC processor are performed in the “executi