U. S. Patent No. RE43,729
`Petition for Inter Partes Review, Reply Declaration of V. Thomas Rhyne, Ph. D
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`ARM Ltd.
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`Petitioner
`
`V.
`
`GODO KAISHA IP BRIDGE 1
`
`Patent Owner
`
`Case IPR2016-00825
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`Patent No. RE43,729
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`Case No. IPR2016-00825
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`REPLY DECLARATION OF V. THOMAS RHYNE, PH.D., P.E., R.P.A.
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`PETITIONER EXHIBIT 1028-0001
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`Petition for Inter Partes Review, Reply Declaration of V. Thomas Rhyne, Ph. D
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`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`ARM Ltd.
`
`Petitioner
`
`V.
`
`GODO KAISHA IP BRIDGE 1
`
`Patent Owner
`
`Case IPR2016-00825
`
`Patent No. RE43,729
`
`Case No. IPR2016-00825
`
`REPLY DECLARATION OF V. THOMAS RHYNE, PH.D., P.E., R.P.A.
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`PETITIONER EXHIBIT 1028-0001
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`U. S. Patent No. RE43,729
`Petition for Inter Partes Review, Reply Declaration of V. Thomas Rhyne, Ph. D
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`I, Vernon Thomas Rhyne, declare:
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`1.
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`I have been retained by Wiley Rein LLP to provide my opinions
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`concerning the background of the computer art as related to the
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`validity of U.S. Patent No. RE43,729 (“the ’729 Patent”). In
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`particular, in this Declaration I provide my opinions regarding the state
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`of that art as of the priority date of the ’729 Patent for processor
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`architectures with respect to instructions that could perform saturation
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`operations and in reply to certain opinions in the Declaration of
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`Thomas M. Conte, Ph.D.
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`I am being compensated for my work in
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`preparing this Declaration at the rate of $695 per hour, plus
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`reimbursement of reasonable direct expenses.
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`I have no other interest
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`in this matter or the parties involved in this matter; my compensation
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`does not depend upon the outcome of the Petition for Inter Partes
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`Review with which this Declaration is submitted.
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`I. QUALIFICATIONS
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`2. My qualifications for forming the opinions set forth in this Declaration
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`are summarized in the following paragraphs and explained in more
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`detail in my curriculum vitae which is attached as part of Exhibit A to
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`this Declaration. Exhibit A also includes a list of my publications and
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`a list of my testimony during the past four years.
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`1
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`PETITIONER EXHIBIT 1028-0002
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`U. S. Patent No. RE43,729
`Petition for Inter Partes Review, Reply Declaration of V. Thomas Rhyne, Ph. D
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`3.
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`I have studied, taught, and practiced electrical engineering for over
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`fifty years.
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`I hold degrees from Mississippi State University
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`(Bachelors of Science in Electrical Engineering with Honors, 1962),
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`the University of Virginia (Masters of Electrical Engineering, 1964),
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`and the Georgia Institute of Technology (Ph.D. in Electrical
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`Engineering, 1967).
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`I have been a registered Professional Engineer in
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`the State of Texas since 1969 (TX, No. 28,728).
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`I have been a
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`Registered Patent Agent since 1999 (No. 45,041).
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`4.
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`I taught electrical engineering, computer engineering, computer
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`architecture, and computer science at the undergraduate and graduate
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`levels full-time at Texas A&M University from 1967 to 1983 and part-
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`time at the graduate level at the University of Texas from 1983 to
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`1991. My twenty-plus years of industrial experience include work for
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`the Electric Power Research Institute, Texas Instruments, Control Data
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`Corporation, NASA, Texas Digital Systems, Inc. (a company I co-
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`founded to produce microprocessor-based computer peripherals in
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`1976), the Microelectronics and Computer Technology Corporation
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`(MCC), and Motorola, Inc.
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`5.
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`I have extensive experience with computer technology, including
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`design and teaching experience with a variety of computer systems,
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`2
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`PETITIONER EXHIBIT 1028-0003
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`U. S. Patent No. RE43,729
`Petition for Inter Partes Review, Reply Declaration of V. Thomas Rhyne, Ph. D
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`microcomputer systems, and microcontrollers.
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`I have participated in
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`the design of several computer systems and microprocessors, and have
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`designed systems that made use of those devices as control elements.
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`I
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`am an experienced programmer in a variety of programming languages
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`as well as assembly-level language on a number of different computers
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`and microprocessors.
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`6. During my academic career, I authored thirty technical papers and
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`research reports, as I noted above, those papers and reports are listed in
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`Exhibit 1.
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`I also presented papers at a number of technical conferences
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`and authored an award-winning textbook, Fundamentals ofDigital
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`System Design, published by Prentice-Hall in 1973 and adopted at over
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`thirty-five U.S. and international universities during its lifetime. My
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`textbook has been cited as a reference by the U.S. Patent and
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`Trademark Office.
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`I have also served as a technical reviewer for
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`Prentice-Hall, the IEEE Transactions on Computing, and IEEE
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`Spectrum.
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`7.
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`I have been a member of the IEEE for over fifty years and am a Life
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`Fellow of that professional organization.
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`I was elected to serve on the
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`IEEE Board of Directors for two terms representing the engineering
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`PETITIONER EXHIBIT 1028-0004
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`U. S. Patent No. RE43,729
`Petition for Inter Partes Review, Reply Declaration of V. Thomas Rhyne, Ph. D
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`education community and the IEEE Computer Society.
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`I was also
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`elected to two terms as the IEEE Treasurer.
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`8.
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`I have extensive experience with the accreditation of engineering and
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`computer science programs in the U.S. and abroad, an activity that
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`provided me an excellent opportunity to become familiar with the
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`program curricula, faculties, and graduates from a large number of
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`U.S. and international colleges and universities.
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`1 represented the
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`IEEE for five years on the Engineering Accreditation Commission and
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`for six years on the Board of Directors of the Accreditation Board for
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`Engineering and Technology (ABET).
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`I have assisted Japanese
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`universities and industries in the establishment of the Japanese
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`Accreditation Board for Engineering Education, and have led several
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`other international accreditation missions.
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`9. Iwas appointed by the U.S. National Research Council to the Panel of
`
`Assessment for the Electronics and Electrical Engineering Laboratory
`
`of the U.S. National Institute of Standards and Technology.
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`I served
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`on that Panel for seven years, including three terms as its chair, based
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`on that work I was invited to provide testimony before the U.S.
`
`Congress regarding the status of the Laboratory.
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`PETITIONER EXHIBIT 1028-0005
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`U. S. Patent No. RE43,729
`Petition for Inter Partes Review, Reply Declaration of V. Thomas Rhyne, Ph. D
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`10.My experience and qualifications have been recognized by the Texas
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`Society of Professional Engineers (Young Engineer of the Year in
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`Texas, 1973); the American Society for Engineering Education
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`(Terman Awardee as the “Outstanding Young Electrical Engineering
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`Educator in the US,” 1980), the Institute of Electrical and Electronics
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`Engineers (IEEE Fellow, 1990, recognizing my contributions to
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`“computer engineering and computer engineering education”); the
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`Accreditation Board for Engineering and Technology (ABET Fellow,
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`1992); and the IEEE Computer Society (Golden Core Awardee, 2000).
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`11.Based on my academic and consulting experience, I am familiar with a
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`variety of computer-based user interfaces, database technologies, and
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`data-communications protocols.
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`I have managed large and complex
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`software-development programs and have been and am familiar with
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`the development of software systems for supporting complex
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`operations.
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`12.My teaching and industrial experience has included the architectural
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`design of a number of computers ranging from microprocessors to
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`supercomputers. As part of that experience I have worked with the
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`design of computer processors that operated on fixed-point data,
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`including integers.
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`I taught computer architecture at the graduate level
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`5
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`PETITIONER EXHIBIT 1028-0006
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`U. S. Patent No. RE43,729
`Petition for Inter Partes Review, Reply Declaration of V. Thomas Rhyne, Ph. D
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`at both Texas A&M and the University of Texas. At the latter
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`institution, 1 used an early version of the Hennessey and Patterson
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`textbook cited by both myself and Dr. Conte for my graduate-level
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`class.
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`13.1 retired from full-time work as of 1997 and draw retirement benefits
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`from Texas A&M University. In addition to the work described above
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`and in my curriculum vitae which is attached to this expert report as
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`Exhibit 1, I have worked part-time as a consulting engineer for the past
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`thirty years doing computer systems design, application-specific
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`system design, and expert witness work in intellectual property
`
`litigation.
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`14.1 have read and am familiar with the ’729 Patent and the file history of
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`that patent, including its parent applications.
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`15 .As part of my preparation for forming the opinions set forth in this
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`Declaration, I have reviewed and relied upon Exhibits 1001 — 1020 as
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`identified in the Exhibit list attached to the Petition for Inter Partes
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`Review (referred in this declaration as the Petition) to which this
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`Declaration is also attached. In particular, I reviewed and relied upon
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`the following:
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`PETITIONER EXHIBIT 1028-0007
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`U. S. Patent No. RE43;729
`Petition for Inter Partes Review; Reply Declaration of V. Thomas Rhyne, Ph. D
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`0 The ’729 Patent;
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`0 The prosecution history of the ’729 Patent including the
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`prosecution history of the parent applications;
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`0 The prior art cited in the Petition including Exhibits 1002 — 1007;
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`0 The Patterson and Hennessy textbook cited in Exhibit 1007;
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`0 All of the materials cited within this Declaration.
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`II.
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`BACKGROUND OF THE ART
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`16.The technology in the’729 patent that relates to claims 21 and 22 is
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`long known in the art. Data within processors is organized generally
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`by the number of bits that are used to store the data. Eight bits is
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`generally considered a “byte.” In many common computers; the
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`available memory locations are arranged as some combination of
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`different numbers of bytes such as 16-bits (2 bytes); 32-bits (4 bytes)
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`or 64 bits (8 bytes). There is nothing magical about the number of bits
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`or bytes stored in each location; but the processor must be designed to
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`properly account for the defined number of bits used to store values.
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`17 .Because each memory location is a discrete set of bits; the issue of
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`overflow arises. A simple example illustrates the concept of overflow.
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`If the data representation is 8-bits; the maximum value that can be held
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`PETITIONER EXHIBIT 1028-0008
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`U. S. Patent No. RE43,729
`Petition for Inter Partes Review, Reply Declaration of V. Thomas Rhyne, Ph. D
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`in 8-bits is 255 (unsigned) or 127 (signed). If the processor adds two
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`unsigned 8-bit values, the result might be larger than 255, and thus
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`larger than an 8-bit value can represent. This would an example of be
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`overflow. Similarly, a subtraction of two unsigned values might result
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`in a negative number. This would be an example of underflow.
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`18.The overflow and underflow of values can be handled in many
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`different ways. The particular manner of representation depends upon
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`the type of processing being performed.
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`19.0ne means for managing overflow and underflow is simple; it is
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`known as “saturation” which is also referenced in the art as clipping or
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`clamping. If a value that results from an operation is too large to be
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`stored in the number of bits assigned to a memory location, then the
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`maximum value that can be stored is used instead. If a resultant value
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`is negative, then a value of 0 is stored. If the resultant value is between
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`0 and the maximum possible value for the number of bits, then the
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`resultant value is stored unchanged.
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`20. Saturation is a well-known process that has been implemented for
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`decades prior to the filing of the parent application of the ’729 patent.
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`PETITIONER EXHIBIT 1028-0009
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`U. S. Patent No. RE43,729
`Petition for Inter Partes Review, Reply Declaration of V. Thomas Rhyne, Ph. D
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`III.
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`PROSECUTION HISTORY AND MEANING OF CLAIM TERMS.
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`211 have reviewed the prosecution history of the ’729 patent and its
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`parent applications including the applications that led to RE43,145
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`and RE39, 121 .
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`IV. KNOWLEDGE OF ONE SKILLED IN THE ART
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`22. After reviewing the ’729 patent and the relevant materials cited in my
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`declaration, I believe that in 1997 one skilled in the art in the
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`technology described and claimed in the ’729 patent would have a
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`Bachelor’s of Science degree in Electrical Engineering, Computer
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`Engineering or a closely related field, and at least three years of
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`professional experience in the development of computer processors.
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`V.
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`PRIOR ART
`
`A. THE VAN HOOK PATENT
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`23.1 have reviewed U.S. Patent No. 5,734,874 which was issued to Van
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`Hook, et al. (“Van Hook”).
`
`1 have also reviewed my prior Declaration
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`24.In that Declaration, I noted that Van Hook taught a “scaling factor”
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`that is stored in the GSR register within the graphics unit and which
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`allows a user to specify where the implicit binary (radix) point should
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`be within the scaled operand, and how a 16-bit field within that
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`operand should are to be interpreted.
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`9
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`PETITIONER EXHIBIT 1028-0010
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`U. S. Patent No. RE43,729
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`25.Van Hook also teaches that the “scale_factor” within the GSR register
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`is programmable, and that it is intended to be used for pixel formatting.
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`,“The GSR related instructions include a RDASR and WRASR
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`instruction for reading and writing the
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`scale_factor from and into
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`the GSR.” Van Hook at 6:38-41 “[T]he GSR 50 is used to store
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`a
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`scaling factor to be used for pixel formatting...” Ex. 1002, 4: 16-18.
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`This “pixel formatting” indicates that the scale_factor is intended to be
`
`used to convert intermediate data values into the 8-bit unsigned format
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`used by pixels.
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`26.Furthermore, Van Hook teaches that the disclosed “Fixed16 and
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`Fixed32 formats 66b-66c provide enough precision and dynamic range
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`for storing intermediate data computed during filtering and other
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`simple image manipulation operations performed on pixel data.” Id. at
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`5:60-6:3. The “precision and dynamic range for storing intermediate
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`data computer during filtering and other simple image manipulation”
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`statement indicates to one of skill in the art that programmers could use
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`these formats with different numbers of bits assigned to the “int” and
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`“frac” portions of the pixel data values.
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`27 .The programmability of the scale factor in the GSR and its use for
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`“pixel formatting” (and to provide enough “precision and dynamic
`
`10
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`PETITIONER EXHIBIT 1028-0011
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`range” for various algorithms) demonstrates that the scale factor of
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`Van Hook was intended to allow programmers the flexibility to
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`perform their calculations using the number of “frac” and “int” bits
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`they felt were appropriate for their calculations (within the bounds of
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`the range of the scaling factor from O to 15).
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`28.In Figure 8e, for example, Van Hook shows that if the scaling factor
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`were 0, then the programmer would be using 9 bits of “int” and 7 bits
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`of “frac” for a 16-bit operand. However, the programmer could
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`program the scaling factor to be any value between 0 and 15, and thus
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`could adjust the number of bits of “frac” down to 0 (corresponding to a
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`scale factor of 7) and, if desired, also could perform calculations using
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`powers of two as the lower bits of significance (for scaling factors 8
`
`and above). This was explained in my original Declaration’s
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`discussion of Van Hook’s Figure 8b with its scale factors of 10 and 4.
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`291 have reviewed the presentation in the Patent Owner’s Response at
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`pages 44-54. There, the Response discusses and depicts an “adder” in
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`juxtaposition to Figure 9b in Van Hook on page 49, apparently seeking
`
`to show that the circuitry needed to perform a 64-bit addition was
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`much simpler that that required to perform the Pixel Distance operation
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`of Van Horn.
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`11
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`PETITIONER EXHIBIT 1028-0012
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`U. S. Patent No. RE43,729
`Petition for Inter Partes Review, Reply Declaration of V. Thomas Rhyne, Ph. D
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`30. That same figure is included in 11 111 of Dr. Conte’s Declaration,
`
`and based on the figure, Dr. Conte opines in his 11 112 that “As
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`visualized in the above diagram, for each pipe stage in Van Hook’s
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`system to be executed within one cycle, the cycle time would have
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`to be increased significantly, potentially by several times the
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`amount of increase needed for conventional RISC architectures that
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`comprise only simpler instructions such as the ADD instruction.” 1
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`disagree with that opinion.
`
`31. In my experience, designers of pipelined arithmetic units always
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`consider the time allowed for each instruction that their unit is to
`
`execute on a case-by-case basis, and then dedicate hardware
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`resources to speed up execution of the more complex instructions
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`so as to obtain the fastest pipeline cycle time as possible. That
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`approach can be seen in the circuitry of Van Hom’s Pixel Distance
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`instruction where Van Horn elected to use a tier of “Carry Save”
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`adders to save execution time.
`
`32.Further, since the left hand figure in Dr. Conte’s side-by-side diagram
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`is intended to represent an “adder,” I note that the simple icon
`
`representing that adder hides what may very well be a complex set of
`
`logical circuitry, especially for a 64-bit processor. It is well known
`
`12
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`PETITIONER EXHIBIT 1028-0013
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`U. S. Patent No. RE43,729
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`that a 64-bit adder designed as simply a string of full-adders would
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`take over 200 levels of logic, meaning that it would be far too slow for
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`use in a pipelined architecture.
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`33.lnstead, such adders are typically implemented by using multiple
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`cany-save adders in a tier structure similar to that shown on the right
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`side of Dr. Conte’s figure, with each of those adders processing a
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`smaller number of bits in a manner that provides aa greatly accelerated
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`carry chain to allow combination of sums produced by the smaller
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`adders to properly process the larger set of bits. Representing such a
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`complex set of fast addition circuitry by a simple “Adder” icon,
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`especially when comparing it with a detailed logic diagram for a
`
`different instruction, is misleading.
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`VI. CONCLUSION
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`For the foregoing reasons, it continues to be my opinion that each limitation
`
`of claims 21 and 22 of the ’729 Patent is met by the prior art identified and
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`discussed above.
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`I declare under penalty of perjury under the laws of the United States of
`
`America that the foregoing is true and correct, and that all statements are made of
`
`my own knowledge are true.
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`13
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`PETITIONER EXHIBIT 1028-0014
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`U. S. Patent No. RE43,729
`Petition for Inter Partes Review, Reply Declaration of V. Thomas Rhyne, Ph. D
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`Executed this 13th day of March, 2017, in Austin, TX.
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`V. Thomas Rhyne, Ph.D., P.EiEz.P.A.
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`14
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`PETITIONER EXHIBIT 1028-0015
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`U. S. Patent No. RE43,729
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`VII. EXHIBIT A
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`A.
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`Curriculum Vitae of Vernon Thomas Rhyne III
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`PETITIONER EXHIBIT 1028-0016
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`U. S. Patent No. RE43,729
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`VERNON THOMAS (TOM) RHYNE, III
`
`8407 Horse Mountain Cove
`
`Austin, TX 78759-6828
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`Phone and FAX: (512) 219-0849
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`E-Mail: trhyne@texas.net or t.rhyne@ieee.org
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`BIOGRAPHICAL DATA
`
`Birthdate: February 18, 1942
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`Citizenship: USA
`
`Married: Glenda Pevey Rhyne
`
`Children: Amber Rhyne Compton and Vernon Thomas Rhyne, IV
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`Grandchildren: Truett Rhyne Compton and Tate James Compton
`
`Security Clearance: Department of Defense Secret (Inactive)
`
`PROFESSIONAL INTERESTS
`
`0 Microprocessor/l\/Iicrocomputer Design and Application
`
`0 Computer-Aided Design
`
`0 Computer Architecture
`
`0 Digital Systems Design and Synthesis
`
`0 Digital Communications
`
`0 Electronic Circuit Design
`
`0 Semiconductor Manufacture
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`0 Technology Maturation and Commercialization
`
`0
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`Intellectual Property Litigation
`
`EDUCATION
`
`0 Ph.D.
`
`(Electrical Engineering) — Georgia Institute of Technology, 1967.
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`Ph.D. Dissertation entitled “Real-Time Signal Enhancement of the Fetal
`
`Electrocardiogram.”
`
`16
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`PETITIONER EXHIBIT 1028-0017
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`U. S. Patent No. RE43,729
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`0
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`— University of Virginia, 1964. Master’s Thesis entitled
`
`“Ferroelectric Devices for Nondestructive Memory.”
`
`0 B.S.E.E. (Special Honors) — Mississippi State University, 1962.
`
`0
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`Japanese Language Instruction, 1988-89, 1996, 1997.
`
`0 Modern Semiconductor Manufacturing, Motorola University, 1996.
`
`WORK EXPERIENCE
`
`Industrial and Research:
`
`1997-Present: Retired from Texas A&M University, part-time engineering
`consultant.
`
`1995-1997: Manager of Strategic Programs, Strategic Asset Group,
`Semiconductor Products Sector, Motorola, Inc., Austin, TX. Responsible
`for technology transfer negotiations and management ofjoint ventures with
`strategic partners.
`
`1994-1995: Vice President, Research and Development, Information Systems
`Division, Microelectronics and Computer Technology Corporation (MCC).
`Responsible for MCC R&D in neural network applications, data mining,
`software interface standardization, and other advanced software
`development projects.
`
`1991-1994: Director, MCC ATLAS Standards Laboratories. Responsible for
`definition and testing of CAD framework and interfaces in support of the
`CAD Framework Initiative, Inc.
`
`1989-1991: Manager, CAD Framework Laboratory, MCC CAD Program.
`Responsible for definition and testing of CAD framework and interfaces.
`
`1988-1989: Manager, Systems Engineering Group, MCC CAD Program, 1988.
`Responsible for alpha testing of MCC CAD System.
`
`1986-1989: Deputy Director, MCC CAD Program. Responsible for general
`program administration.
`
`1983-1986: Director, Systems Technology Laboratory, MCC CAD Program,
`Austin, TX. Responsible for development of supporting technologies for
`MCC CAD System including distributed databases, natural-language
`interface, and rule-based design management.
`
`1962-1965: Aerospace Technologist, Analysis and Computer Technology
`
`17
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`PETITIONER EXHIBIT 1028-0018
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`U. S. Patent No. RE43,729
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`Division, NASA Langley Research Center, VA
`
`1965-1967: System Engineer (Part-Time), Lockheed-Georgia Research Center,
`Marietta, GA.
`
`1961: Summer Intern, Union Carbide Corporation, Texas City, TX.
`
`Academic:
`
`0 Senior Lecturer in Electrical/Computer Engineering, University of Texas at
`
`Austin, 1984-1994.
`
`0 Adjunct Faculty Member, Department of Electrical
`
`and Computer
`
`Engineering, Carnegie-Mellon University, 1986-1992.
`
`0 University/SRC Coordinator, MCC CAD Program, 1988-1990, SRC Design
`
`Sciences Advisory Committee, 1989-1990.
`
`0 Professor, Electrical Engineering, Texas A&M University 1974-1986 (on
`
`leave to MCC during 1983-86).
`
`0 Coordinator of Computing, Texas A&M University, 1982-1983.
`
`0 Director, Digital Systems Laboratory, Department of Electrical Engineering,
`
`Texas A&M University, 1978-1983.
`
`0 Associate Professor, Electrical Engineering, Texas A&M University, 1969-
`
`1974.
`
`0 Assistant Professor, Electrical Engineering, Texas A&M University, 1967-
`
`1969.
`
`0
`
`Instructor, Electrical Engineering, Georgia Institute of Technology, 1965-
`
`1967.
`
`0 Lecturer, Computer Systems, George Washington University Extension,
`
`1964.
`
`Consulting:
`
`PETITIONER EXHIBIT 1028-0019
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`U. S. Patent No. RE43,729
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`0 Consultant to a number of companies and law firms re intellectual property
`
`litigation, 197 8-present (part-time).
`
`0 Consultant to the Electric Power Research Institute, including serving as
`
`technical project manager on the EPRI/DOE Distribution Automation
`
`Project, 1979-1983.
`
`0 Consulting engineer to a variety of national and international
`
`industries
`
`dealing with microelectronics and computer design. Clients have included
`
`Texas Instruments, Control Data Corporation, AI\/ID, ETA, and Signetics.
`
`0 Consulting engineer to a variety of clients dealing with computer systems for
`
`satellite navigation.
`
`Clients have included Texas Instruments, Gould,
`
`Matsushita, ITE-Europe, and the Federal Republic of Germany.
`
`0
`
`Invited member of NASA Shuttle-GPS Advisory Panel and EPRI/DOE
`
`Distribution Automation Research Review Panel, 1979-1981.
`
`0 Consultant to U.S. Coast Guard, developing on-line data acquisition system
`
`for shipboard navigation data and off-line data processing/analysis systems,
`
`1979-1982.
`
`0 Principal investigator on research projects dealing with automated Boolean
`
`minimization, high-speed computer arithmetic, bit-serial processing, special-
`
`purpose VLSI architectures, marine navigation systems, and computer-aided
`
`design of digital systems, 1967-83.
`
`OTHER PROFESSIONAL ACTIVITIES
`
`0 Member, Panel on Assessment, Electrical and Electronics Engineering
`
`Laboratory, U.S. National Institute for Standards and Technology, 1993 to
`
`1999, Panel Chair, 1996-99. (Appointed by National Research Council)
`
`19
`
`PETITIONER EXHIBIT 1028-0020
`
`
`
`U. S. Patent No. RE43,729
`Petition for Inter Partes Review, Reply Declaration of V. Thomas Rhyne, Ph. D
`
`0 Planning Committee, 1997 Workshop for National Technology Roadmap for
`
`Semiconductors, SIA.
`
`0 Member, Technical Working Group
`
`(TWIG)
`
`on
`
`Semiconductor
`
`Manufacture, SIA, 1995-97.
`
`0 Secretary, Board of Directors of White Oak Semiconductor, Inc., Richmond,
`
`VA, 1996-97.
`
`0 Executive Secretary, Board of Directors of the Tohoku Semiconductor
`
`Corporation, Sendai, Japan, 1996-97.
`
`0 Board of Directors Alternate, Semiconductor Research Corporation,
`
`representing Motorola, 1995-96.
`
`0 Roadmap Coordinating Committee, Semiconductor Industries Association,
`
`1995.
`
`0 Book reviewer, American Scientist, 1993.
`
`0 Reviewer for State-funded research proposals in microelectronics, computer
`
`science, and computer engineering, Texas Higher Education Coordinating
`
`Board, 1993.
`
`0 Visitor for Accreditation Board for Engineering and Technology, accrediting
`
`undergraduate programs in Computer Science, Computer Engineering and
`
`Electrical Engineering, 1981-1983, 1991-92, 1997-present.
`
`0 Chair for nine U.S.
`
`engineering program accreditation teams, 1984-90,
`
`including accreditation teams for the University of California at Berkeley
`
`(1988) and the University of Illinois (1989).
`
`0 Advisor, Texas State Board of Education (1985), Texas State Coordinating
`
`Board for Higher Education (1987).
`
`20
`
`PETITIONER EXHIBIT 1028-0021
`
`
`
`U. S. Patent No. RE43,729
`Petition for Inter Partes Review, Reply Declaration of V. Thomas Rhyne, Ph. D
`
`0 Consultant on international engineering accreditation, Kuwait University
`
`College of Engineering and Petroleum (1990 and 1992), Korean Institute for
`
`Advanced Science and Technology (1993), Bilkent University, Ankara,
`
`Turkey (1995), University of the United Arab Emirates (1998), ITESM,
`
`Querétaro, Mexico (1999), Kyoto University, Japan (2000), Ritsumeikan
`
`University, Japan (2000), Mapua Institute of Technology, Manila (2004).
`
`0 Consultant on engineering accreditation to the Japan Accreditation Board for
`
`Engineering Accreditation, 2000-2004.
`
`0 Advisor
`
`to
`
`the Washington Accord
`
`on
`
`lntemational Engineering
`
`Accreditation, 2003-04.
`
`0 Consultant on engineering education and long-range planning, George
`
`Washington School of Engineering and Applied Science, 1990 and 1993-94.
`
`PROFESSIONAL LICENSES
`
`0 Registered Professional Engineer, Texas, No. 28,728.
`
`0 Registered Patent Agent, No. 45,041.
`
`0 Pilot (Single-Engine Land).
`
`PROFESSIONAL AND HONORARY SOCIETY MEMBERSHIPS
`
`Professional Societies:
`
`0 Member, Institute of Electrical and Electronics Engineers, 1963-present.
`
`0
`
`0
`
`0
`
`0
`
`IEEE Treasurer, 1994 and 1995.
`
`IEEE Board of Directors, 1991-1995.
`
`IEEE Executive Committee, 1993-1995 .
`
`IEEE Board of Directors, Division VIII Director, 1993, Division VI
`
`Director, 1991-1992.
`
`21
`
`PETITIONER EXHIBIT 1028-0022
`
`
`
`U. S. Patent No. RE43,729
`Petition for Inter Partes Review, Reply Declaration of V. Thomas Rhyne, Ph. D
`
`0
`
`0
`
`0
`
`0
`
`0
`
`IEEE Technical Activities Board, 1991-93.
`
`IEEE Employee Benefits Committee, Member, 1991 to 1999, Chair, 1997,
`
`1998.
`
`IEEE Computer Society, 1964 to present.
`
`IEEE Computer Society Board of Governors, 1985.
`
`IEEE Computer Society Executive Committee, 1993.
`
`0 Accreditation Board for Engineering and Technology, 1994 to 1999,
`
`representing IEEE.
`
`Honorary Societies:
`
`0 Upsilon Pi Epsilon (Computer Science).
`
`0 Eta Kappa Nu (Electrical Engineering).
`
`0 Tau Beta Pi (Engineering).
`
`0 Phi Kappa Phi (Scholarship).
`
`0 Sigma Xi (Research).
`
`OTHER HONORS
`
`0 The Contemporary Who’s Who, 2003.
`
`0 Strathmore’s Who’s Who, 2000-present.
`
`0
`
`IEEE Millennium Award, 2000.
`
`0 Golden Core Award, IEEE Computer Society, 1996.
`
`0 Fellow of the Accreditation Board for Engineering and Technology, 1992.
`
`0 Outstanding Engineering Graduate, Mississippi State University, 1992.
`
`0
`
`IEEE Educational Activities Board Award for Meritorious Achievement in
`
`Accreditation Activities, 1991.
`
`22
`
`PETITIONER EXHIBIT 1028-0023
`
`
`
`U. S. Patent No. RE43,729
`Petition for Inter Partes Review, Reply Declaration of V. Thomas Rhyne, Ph. D
`
`0 Who’s Who in America, 1991-present.
`
`0 Who’s Who in Engineering, 1991-present.
`
`0 Elected as an IEEE Fellow for “contributions to computer engineering and
`
`the computer engineering profession,” 1990.
`
`0 F. E. Terman Award (Outstanding Young Electrical Engineering Educator
`
`in U.S.), American Society for Engineering Education, 1980.
`
`0 Outstanding Young Engineer (Honorable Mention), National Society of
`
`Professional Engineers, 1974.
`
`0 Young Engineer of the Year, State of Texas, Texas Society of Professional
`
`Engineers, 1973.
`
`0 Outstanding Faculty Member, Texas A&M University Student Engineers
`
`Council Award, 1973.
`
`0 General Dynamics Award for Excellence in Engineering Teaching, 1972.
`
`0 American Men and Women of Science.
`
`COMMITTEE MEMBERSHIPS
`
`Professional:
`
`0 Technical Program Chair for 1992 IFIPS Workshop on Electronic CAD
`
`Design Environments, March 23-25, 1992, Paderbom, Germany.
`
`0 Chair,
`
`ISO TC184/SC4-IEC TC3 Joint Working Group (JWG9)
`
`for
`
`Electrical/Electronic Product Data Exchange, 1991-1993.
`
`0 DARPA Principal
`
`Investigators Advisory Panel,
`
`Information Systems
`
`Technology, 1990-1994
`
`23
`
`PETITIONER EXHIBIT 1028-0024
`
`
`
`U. S. Patent No. RE43,729
`Petition for Inter Partes Review, Reply Declaration of V. Thomas Rhyne, Ph. D
`
`0 Review team member
`
`for
`
`academic
`
`and
`
`research
`
`programs
`
`in
`
`microelectronics at
`
`the Microelectronics Research Center,
`
`Iowa State
`
`University, 1989.
`
`0 CAD Framework Initiative: Interim Steering Committee, 1988-1989; Board
`
`of Directors,
`
`1989-1992, Treasurer,
`
`1989-1992, Chair, Technical
`
`Coordinating Committee, 1989-1990.
`
`- Member, IEC TC3, WG11, 1990-1991.
`
`0 Member, Working Group 2, IEC Technical Committee TC3, and IEEE SCC
`
`11.9, developing IEEE Standard 91-1984, “Explanation of Logic Symbols,”
`
`1982-1985.
`
`Civic:
`
`0 Elected to Eanes Independent School District Board of Trustees, 1986-1997 ,
`
`President, 1987-1990, 1996-97.
`
`0 Texas Association of School Boards Finance Committee, 1989-1994, Tax
`
`Restructuring Committee, 1990.
`
`0 Citizens Advisory Committee, Westlake Picayune, 1988-90.
`
`0 Advisory Committee for Electric Power Distribution, City of West Lake
`
`Hills, 1987-1990.
`
`0 Capital Area Easter Seal Rehabilitation Center Advisory Board, 1985-1986,
`
`Telethon Committee, 1986.
`
`PUBLICATIONS
`
`Books, Contributions to Books, Published Notes, and Standards:
`
`0 Electronic Design Automation Framewor/cs—When Will the Promise Be
`
`ReaZized?, North-Holland, Amsterdam, 1992 (editor and contributor).
`
`24
`
`PETITIONER EXHIBIT 1028-0025
`
`
`
`U. S. Patent No. RE43,729
`Petition for Inter Partes Review, Reply Declaration of V. Thomas Rhyne, Ph. D
`
`0
`
`ISO 10303 Standard for Product Data Exchange, Parts 103 (Electrical
`
`lnterconnectivity), 212 (Electrotechnical Plants), 210 (Printed Circuit
`
`Assembly Design and Manufacture), and 211 (PCA Test and Logistics),
`
`editor and technical contributor, 1991-1993.
`
`0
`
`“An Introduction to CAD Framework Technology,” Published notes for
`
`DAC Tutorial, 1991 Design Automation Conference, June 21, 1991.
`
`0
`
`“NAVSTAR Global Position
`
`System, A User’s Approach
`
`to
`
`Understanding,” published notes for IEEE Continuing Education Course
`
`No. 1125 (1982), with p. S. Noe and J. H. Painter.
`
`0 Trafic Control Systems Handbook, Chapter
`
`8,
`
`“Communications
`
`Concepts,” Federal Highway Administration, 1976.
`
`0 Fundamentals ofDigital Systems Design, Prentice-Hall, 1973.
`
`0
`
`“Supplementary
`
`lnforrnation
`
`for Computer Engineering Program
`
`Evaluators,” IEEE Manual for Program Evaluators on EAC Accreditation
`
`Teams, IEEE Educational Activities Board, May 1987.
`
`0
`
`“ABET/EAC Program Criteria for Computer Engineering and Similarly
`
`Named Engineering Programs,” contributor, 1985-87.
`
`0
`
`“Graphic Symbols for Logic Devices,” ANSI/IEEE Standard 91-1982,
`
`(co-author), IEEE Standards Office, New York, March 1982.
`
`0
`
`“The NAVSTAR Global Positio
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