PROCEEDINGS OF THE FIRST J_NTERNATIONAL
`SYMPOSIUM ON ULTRA LARGE SCALE INTEGRATION
`SCIENCE AND TECHNOLOGY
`
`ULSI SCIENCE AND TECHNOLOGY/ 198~--
`
`Edited by'
`
`S. Broydo
`ZyMOS Corporation
`Sunnyvale, California
`
`C.M. Osburn
`MCNC
`Research Triangle Park, North Carolina
`
`Assistant Editors
`
`J.M. Andrews
`D.A. Anto nia dis
`W .M. Bullis
`G.K. Getter
`D.B. F rase r
`S . Goodwin-Jo hansson
`G .J . Hu
`Y. lida
`R.J. Jacco dine
`H .J . Levinste in
`E. Middlesworth
`
`Y . Nis hi
`L .C . Parrillo
`J.R . Pf iester
`A. Re isman
`G.C. Schwartz
`A . S inh a
`R.B. Swaro op
`J. V an d er Spiegel
`A .M . Voshchenkov
`D.N.K. W a ng
`
`ELECTRONICS AND DIELECTRICS AND INSULATION DIVISIONS
`
`Proceedings Volume 87- 11
`
`THE ELECTROCHEMICAL SOCIETY, INC., 10 South Main St., Pennington, NJ 08534-2891
`
`Case No. IPR2016-00782
`DSS.2008.001
`
`

`
`Copyright 1987
`by
`The Electrochemical Society, Incorporated
`
`Papers contained herein may not be
`reprinted and may not be digested by pub(cid:173)
`lications other than those of The Electrochemical
`Society in excess of 1/6 of the material presented.
`
`Library of Congress Catalog Number: 87-82381
`Printed in the United States of America
`
`Case No. IPR2016-00782
`DSS.2008.002
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`

`
`SELF ALIGNED BITLINE CONTACT FOR 4 MBIT DRAM
`
`K.H.Kuesters, H.M.Muehlhoff, G. Enders, E.G.Mohr
`and W.Mueller
`
`Corporate Research and Technology,Techn .Center
`for Microe l ectronics,Siemens AG,Otto- Hahn-Ring 6,
`D-8000 Munich 83,
`Ge rma~y
`
`reduction in 4 Mbit dRAM cell ~ize is
`A 25 %
`achieved by a self aligned bitline contact, which
`is £ully overlapping gate and field oxide(FOBIC).
`No additional masks are
`required. The gate
`is
`encapsulated by oxide using an oxide spacer
`t echnique. A
`thin oxide/nitride/oxide dielectric
`allows
`a
`contact hole etch, which does not
`significantly affect
`t he oxide insulation of the
`gate and
`the field oxide. The nitride serves as
`an etch stop for top oxide etch, t he final etch
`step removes only a thin dielectric.
`A 0.9 pm contact between polycide (TaSi) bitline
`and n+ diffusion (Rc <SOQ), 0.2 ~m distance to
`gate is realized without deterioration of tran(cid:173)
`sistor properties . No yield
`reduction due
`to
`gate/bitline shorts
`occurs. No
`influence of
`nitride on device properties
`is observed
`for
`nitride thickness <SOnm.
`
`1. Introduction:
`
`4M DRAM concepts are based on 3 dimensional cell structures
`such as
`trench capacitor cell (1)
`and stacked capacitor
`cell. Their integration into the process flow and the reali(cid:173)
`zation of
`sub micron design rules set new demands
`tor
`process development. However to obtain a chip size of less
`than
`100
`mm 2
`further
`innovations
`are
`necessary.
`In this paper we
`report a
`tre nch capacitor cell with self
`aligned, fu lly overlapping bitline contact (FOBIC). The cell
`design allows
`the contact hole ~o overlap gate and field
`oxide; the contact area
`is
`independant of
`lithographic
`alignment tolerances. The registration tolerance for bitl ine
`contacts is eliminated {see fig. 1). Thus the cell area can
`be shrunk by 25 % compared
`to
`a
`conventional contact
`technique.
`The proposed process is different from previous concepts for
`self aligned contacts (2 -5 )
`in which
`t he thermal oxide of
`gate polysilicon
`is used as an interlevel insulator between
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`the
`to match
`interconnections. The process has
`gates and
`requirements of reliable submicron LDD transistors, wh ic h
`are deteriorated by a
`strong reoxidation of gate po l y(cid:173)
`silicon.
`recent self aligned contact technology
`In contrast with a
`(6) which uses nitride LDD spacers and gate encapsulation,
`an oxide spacer technique is used because of LDD transistor
`reliability.
`A new
`technique for etching the dielectric underneath the
`bitline is used to ensure a
`good insulation of bitline to
`polysilicon gates
`(wordline) and substrate for
`the over(cid:173)
`lapping contacts. The FOBIC contact process
`is integra ted
`i nto the 4 Mbit process flow without additional masks.
`
`2. Process flow
`
`is fabricated with a 0.9 pm twin well pro(cid:173)
`The 4 Mbit dRAM
`cess. After
`trench capacitor and LDD transistor formation a
`lew resis tivity polycide (poly Si/TaSi:;,) layer is used for
`bit l ines and
`local peripheral
`inte rconnects. The
`second
`interconnect level consists of Ti/TiN/AlSi metallization.
`For contacts connecting the polycide bitline to n+ diffusion
`transfer gates) the FOBIC process (fig. 2)
`(source/drain of
`is employed.
`
`2.1 Oxide encapsulation of the gate
`(0.3 ~
`After patterning
`a double
`layer of poly Si/oxide
`TEOS) an oxide spacer
`is formed by oxide deposition (TEOS)
`(0.2 pro)
`and RIE etching (CHF3/02). The spacer width
`~s
`determined by LDD transistor optimization. The poly gate is
`insulated by at least 0.15 ~m oxide. A vertical etch profile
`of poly Si/oxide which can be achieved by sequential oxide
`etch (CHF3/02)
`and poly Si etch
`(Cl2/He)
`is essential.
`The same
`technique for oxide encapsulation of the gate has
`also been applied to
`a polycide gate with an oxide spacer
`covering the sidewalls of
`a trip le layer of poly Si/TaSi:;,/
`oxide.
`
`2.2.1 Contact hole etch
`The dielectr~c under the bitli ne consists of a tri~le layer
`of thin oxide/nitride/oxide. For
`the top oxide
`a
`reflow
`technique (PH 3-diffusion and backetch of the doped oxide) is
`employed, with a final thickness of 0.2/um.
`The triple
`layer dielectric allows a
`contact hole etch,
`which does not significantly affect the field oxide and the
`oxide insulation of the gate (see fig. 2). After patterning
`the contact hole mask
`the top oxide is etched using
`the
`nitride as an etch stop. The oxide etch can be performed
`a) by dry etching, b) by wet etching, or a combination of
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`a CHF3 plasma with a selectivity of 4:1
`a) For dry etching
`with respect
`to the nitride is used (f i g. 3a). Duri ng
`overetch the nitride etch rate reduces due to an enhanced
`development of
`a C rich polymer film on the nitride. The
`(> 70 %) to remove
`overetch time has to be sufficient
`oxide spacers on the nitride. Therefore a nitride thick(cid:173)
`70 nm is required as an etch stop. After removing
`ness >
`the polymer
`film by Ar p l asma,
`the contact hole etch
`continues with etching the nitride (S F6 Plasma , fig. 3b)
`selecti-vely to
`the underlying oxide(= 50 nm). To avoid
`any nitri de spacers along
`the gates an overet~h of 70 %
`is necessary. The remaining
`t h in oxide
`is removed by a
`short dry etch s t ep (CHF3/02).
`b) If the top oxide i s wet etched (NH4F/HF), a nitride l ayer
`of >
`10nm is sufficient for
`the etch stop. The
`thin
`nitride and
`the thin oxide (= 50 nm) underneath are
`etched by
`the same CHF3/02 dry etch step
`(fig . 4a).
`The use of a rather th in nitride as an etch stop is also
`possible if combining
`a dry etch of
`the
`top oxide
`(without long overetch) and
`a wet etch to remove oxide
`spacers on
`the nitride. The use of a wet etch step seems
`also preferable because of a tapering of the contact hole
`edge. If any conventional contacts are patterned by the
`same mask and technique,
`the contact hole size
`is not
`affected by
`a wet etch step
`for the
`top oxide as the
`underlying nitride/oxide i s ~tched anisotropically.
`After completing
`the process
`(see fig.
`3c ,4b,4c) an oxide
`insulation of the gate > 120 nm is obtained, the field o xide
`thinning ~n the contact h ole is at most 50 nm. The contact
`area of the FOBIC contact is defined by gate and field oxide
`edges. The distance of
`the contact
`to the gate
`is only
`0.2 )..liD.
`2.2.2 Contact hole etch-alternative process
`The essential
`feature of
`the contact hole etch proposed in
`2.2.1 is
`the use of an etch stop layer for the top oxide.
`Only a
`t hin dielectric
`is l e f t
`for the final e~~h step .by
`which the oxide insulation of the gate and the fie ld oxide
`can be
`t h inned . Because
`in the case of a pure dry etch of
`top oxide
`the required nitride thickness
`is >
`70 nm,
`an
`alternative process allowing the use of
`a thinner nitride
`even for
`a pure dry etch process has been
`i nvestigated.
`Instead of nitride a double layer of nitride
`(20 nm) and
`poly-Si (30
`nm) is used. Poly Si is a ver y efficient etch
`stop for etching oxide
`in a CHF3/02 plasma (selectivity >
`20 :1). However,
`a continous
`layer of poly Si can cause
`shorts or problems when etching contact holes
`from
`the
`second metallization
`level to source/drain areas. Therefore
`-after top oxide etch, poly Si etch (wet or Cl2/He plasma),
`and resist stripping -
`the poly Si is changed into o~ide by
`wet oxidation
`(900°C,20 min). The poly Si can be oxidized
`although buried under the
`top oxide because the top oxide
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`than thermal oxide. During oxidation
`less dense
`(TEOS) is
`the nitride
`is protecting
`the active arcac. A
`final etch
`step (CHF3/02 plasma) removes
`the nitride and underlying
`thin oxide, leading to the result shown in fig. 5.
`
`2.3 Polycide interconnect level
`formed by TaSi2
`After contact hol e etch
`the bitline is
`(200nm) on top of poly Si (lOOnm). Poly S i is doped by As or
`P Implantation. As shown by SIMS analysis Phosphorous out(cid:173)
`diffusion during subseque~t annealing steps
`(BPSG
`reflow
`900oc, 40 min) is changi~g the vertical doping profile of
`the As doped source/drain areas. Therefore the effect on the
`lightly doped drain r e gions of th e transistors adjac ent to
`the self aligned contact has
`to be checked
`(see 4.2).
`The contact resi stance poly Si
`to n+-diffusion
`c an be
`influenced by
`a thin native oxide at this
`interface. To
`break this oxide ion mixing (7) is applied: Part of the P or
`As dose
`is implanted into the i nterface between the poly Si
`and n~-diffusion. Fig . 6
`shows the geometry dependence of
`contact resLstance with and without Lon mixLng
`for As
`implantation into poly Si. For an effective bitline contact
`width of 0.9 pro less than SO Q are obtained.
`
`3. Device characteri zation
`
`3.1 Isolation of bitline to transfer gate and substrate
`~ig. 7
`shows a wordline to bitline leakage current distri(cid:173)
`bution for DRAM cell arrays with and without FOBIC contact.
`No yield
`reduction due
`t8 FOBIC contacts is observed, and
`is caused by gate oxide failure. To
`isolation breakdown
`suppress the
`leakage current path across
`the gate oxide
`special
`test-structures
`on
`field oxide were evaluated
`(fig. 8). Below 20 V the leakage current is below d etec tion
`limit , breakdown of the oxide i nsulation occurs only at
`voltages higher than 60 V.
`t h e
`Another conce rn about the FOBIC contact process was
`influence of field oxide thinning (max. SOnm) in the contact
`hole on diode properties. Experiments with different over(cid:173)
`etch show no effect on p-n
`junctions as long as the field
`oxide thinning is less than 80nm.
`
`3.2 Transistor properties
`Current-voltage characteristics (fig. 9) of transistors with
`and without FOBIC contact show no difference. No effect of P
`doped poly Si(bitline) on transistor behaviour was observed,
`although lateral diffusion of P i nto LDD regions was one of
`the concerns. Short time DC stress results of transistors
`with and wi thout FOBIC contact also exhi bit no difference.
`Because of the higher gate stack the shadowing effect of the
`LDD Implantation (8,9) becomes more pronounced. However, the
`LDD implant
`shadowing effect
`is effectively ·reduced by
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`implantation (see 9). The L DD
`rotating the waf ers dur i n g
`dose is divided into 4 equal dose s, the waf er is rotated by
`90 degrees after each implanta tion.
`
`3.3 Nitride effect on device
`The introduction
`o f a
`n i tride layer, whi c h is n ot removed
`from the wa fer during
`t he process
`flow, ha s been investi(cid:173)
`ga ted very careful ly. For nitride th ickness of > 100nm an
`enhanced gated diode l eakage
`c urrent is observed for la rge
`transistor arrays
`(no ov erlapping contact) . As shown by TEM
`(fig. 10) a nd def ect analysis, ge neration of 6efects (dislo(cid:173)
`ca tions, point defect clus ter s) appears at t he edge o f the
`gate's oxide
`s pacer , whe re
`the nitride
`layer
`i s
`bend i ng
`upwards . At
`this pa rt icula r
`site the nitride can cause an
`enhanced stress. For n itride thickness of 50nm deteriorat ion
`of gated diode leakage
`curren t occurs
`for high
`reverse
`v oltage (9V) depending on ni t ride deposition parameters
`(enhanced leakage current is observed for l o wer deposition
`t emperatures
`(750 ° C )) . To avoi d
`any effect o n
`leakage
`current (for al l CVD nitride deposition parameters )
`the
`nitride thickness has to be reduc ed
`to
`JOnm
`favoring
`a
`contact h ole etch proce ss
`inc luding a wet etch
`step
`( see
`2.2 . 1) or t h e process outlined in 2 . 2.2.
`Investigation of hot electron degrada tion (fig . 1 1 ) shows a
`r educ~i on i n
`lifetime by
`a fa c tor of five
`for a nitride
`laye r thi ckn e ss of 130
`nm compared
`to devi ces without
`a
`.s 50
`nm ni tr ide
`n itride layer, whi le for
`no effect
`on
`lifetime is observed .
`
`Acknowledgement
`to B.Hasler, W. Meyberg, H .Benzin(cid:173)
`The authors are grateful
`ger, f or their collaboration in this work , to H.Oppol zer for
`TEM ana lysis,
`to H.Haude k, H . Demm f or SEM analysi s . This
`work was supported by the Federal Department of Res ea rch and
`Tec hnology (sign. NT 26 96) .
`REFERENCES
`IEOM Tech. Dig. 19 85, p.69 4
`( 1 ) H.Sunami ,
`(2) S .Muramot o, T . Hos o ya, S . Matsuo, IEDM Tech. Dig.
`197 8, p.185
`(3) Y . Tanigaki, S.Iwamatsu, K.Hirobe, J. Electroche m.
`soc . 19 7 8 , p . 4 7 1
`(4) M.Sakamoto, K.Hamano, IEDM Tech. Dig . 1980 , p.136
`(5)
`J . S.de Zaldivar, NTG-Fachberich te Bd. 77 (1981), p.22
`(6) A.Sh inohara, M.Fukumo to, G. Fuse, S.Odanaka,
`M.Sasago, T.Ohzone, T.Ishihar a, 17thSSDM Tokyo,
`Extended Abstrac ts, p .29
`(7) D.K.Brice, J.Appl.Phys. 46 (1 97 5), p.3385
`(8) T.Mizu no , Y.Matsumoto, S . Sawada, S.Shinozaki,
`O.Ozawa, IEDM Techn. Dig. 1985, p. 2 50
`(9) H.M.Mlihlhoff, P.Murkin, K.H.Klisters , M.Orlowski ,
`W.Mli ller, this confe rence
`
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`
`dKG
`Fig.l: Layout pattern f or bitline contact a) wit hout and
`b) with FOBIC (dxG 1 dxL regi~tration tolerances)
`
`1) Poly Si-Gate With o~1de encapsulation
`
`Resist
`
`o~ide
`
`Nitride
`
`Fig .2:
`Process for FOBIC
`contact(wet etch of
`top oxide as des(cid:173)
`cibed in 2.2.1, b)
`
`cross section of
`bitline contact
`
`2) direct contact mask. oxide etch stopped by mtride layer
`
`3) Nitride/thin. oxide etch
`
`4) Poly Si depositioo Poly Si doping (As Implantation) TaSi sputtering
`
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`Case No. IPR2016-00782
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`
`Fig.3: FOBIC process, using
`dry etch for top oxide
`
`3a:first step of contact
`hole etch: oxide is
`etched selectively to
`underlying nitride
`
`3b:after complete contact
`hole etch process
`
`3c:cross section of 4Mbit dRAM with fully overlapping
`bitline contact (dry etch of top oxide)
`
`646
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`Case No. IPR2016-00782
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`
`Fig.4a:
`After complete
`contact hole
`etch process
`(wet etch of
`top oxide)
`
`Fig.4b, c:
`cross sections of 4Mbit dRAM
`(wet etch of top oxide)
`
`Fig.S:
`Process using a thin poly Si (20 nm) on top of nitride
`(30 nm) as etch stop for etching the top oxide (see 2.2.2)
`Poly Si is changed into oxide by wet oxidation (o~
`a) after contact hole etch
`b) after complete process
`
`O.SJ.Im
`
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`Case No. IPR2016-00782
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`
`As-*' . . . .. :
`~&-UJ--=~--+--~--+----+( 100 rwn Poly Si) --
`
`1
`Fi g.6:
`~~----~~-----4~--~~--~----~
`Geometry dependance
`o f cont act resistance
`n+- pol y/n+- d i ffus i on.
`Lower curve shows
`r ed uc t ion due t o ion
`mixing
`
`10
`
`2
`
`3
`
`4
`
`~\
`I I
`
`"' T ( a)
`
`: I "
`" t
`l .. ~
`" f ,, ~
`"'
`
`,. I
`
`H
`
`1E-9
`
`1E-12
`
`I [AI
`
`Fig . ?:
`(U=lOV) distri bution
`Wordline to bitl ine l e akage current
`for DRAM cell arrays with (a ) and without (b) FOBI C c ontact .
`
`I gate
`[A]
`
`Fig.8:
`Le akage curren t
`acros s wordline
`t o bitl i ne iso(cid:173)
`lation (FOBIC
`techno l ogy) for
`test structure
`on field oxi de
`
`~t~~·~r-t
`I ;-t2l .... L-+--<--+--+--+--~-· +--+---+--1---+---l
`
`- rea
`
`-a0
`
`-00
`
`- 40
`
`- 20
`
`0
`
`648
`
`2 0
`
`4!1
`
`Vgate (V]
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`Case No. IPR2016-00782
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`
`Fig.9:
`Current-Volta ge
`characte r i stics
`of cell transistor s
`wi th FOBIC c o ntact
`
`t s. r-~~~~~~
`ld
`[rnA]
`
`0
`
`3V
`
`Vd [V]
`
`F i g.lO:
`Defects at spacer edge (nit ride
`thicknes s 130 nm)
`(TEM result)
`
`Fig.l l : Shor t time DC stress results for wafers with 130 rum
`nitride 1 50 rum nitride 1 without nitride
`
`ill
`T
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`Case No. IPR2016-00782
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