Paper No. __
`Filed: March 17, 2016
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`____________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`____________________
`
`SAMSUNG ELECTRONICS CO., LTD.;
`MICRON TECHNOLOGY, INC.; and
`SK HYNIX INC.
`Petitioner
`
`v.
`
`ELM 3DS INNOVATIONS, LLC
`Patent Owner
`
`____________________
`
`Patent No. 8,907,499
`____________________
`
`PETITION FOR INTER PARTES REVIEW
`OF CLAIMS 12, 13, 24, 36, 37, 38, 53, 83, 86, 87, AND 132
`OF U.S. PATENT NO. 8,907,499
`
`
`
`
`
`

`
`Petition for Inter Partes Review
`Patent No. 8,907,499
`
`TABLE OF CONTENTS
`
`I.
`
`INTRODUCTION ........................................................................................... 1
`
`II. MANDATORY NOTICES UNDER 37 C.F.R. § 42.8 ................................... 1
`
`III. PAYMENT OF FEES UNDER 37 C.F.R. § 42.15(a) .................................... 3
`
`IV. GROUNDS FOR STANDING ........................................................................ 3
`
`V.
`
`PRECISE RELIEF REQUESTED .................................................................. 3
`
`VI. THE ’499 PATENT ......................................................................................... 5
`
`A.
`
`Technical Background ........................................................................... 5
`
`B. Overview of the ’499 Patent .................................................................. 6
`
`C.
`
`Level of Ordinary Skill in the Art ......................................................... 7
`
`VII. CLAIM CONSTRUCTION ............................................................................ 7
`
`A.
`
`B.
`
`“Substantially flexible . . . semiconductor substrate” (Claim
`132) / “substantially flexible… semiconductor layer” (Claims
`24, 53, 83) .............................................................................................. 8
`
`“substantially flexible circuit” (claims 12, 13 ) / “substantially
`flexible integrated circuit” (claims 24, 36, 37, 38, 83, 86, 87),
`“substantially flexible integrated circuit layer” (claim 132) /
`“substantially flexible structure” (claim 53) .......................................12
`
`VIII. DETAILED EXPLANATION OF GROUNDS UNDER THE
`BROADEST REASONABLE CONSTRUCTIONS ....................................15
`
`A. Overview of the Prior Art References .................................................15
`
`1.
`
`2.
`
`3.
`
`4.
`
`Hsu ............................................................................................15
`
`Bertin .........................................................................................16
`
`Poole .........................................................................................16
`
`Leedy ’695 .................................................................................17
`
`i
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`

`
`Petition for Inter Partes Review
`Patent No. 8,907,499
`Kowa .........................................................................................19
`
`5.
`
`B. Ground 1: Hsu and Leedy ’695 Render Obvious the Challenged
`Claims ..................................................................................................19
`
`1.
`
`2.
`
`3.
`
`4.
`
`5.
`
`6.
`
`7.
`
`8.
`
`9.
`
`Overview of Combination and Reasons to Combine ...............19
`
`Claim 12 ....................................................................................23
`
`Claim 13 ....................................................................................26
`
`Claim 24 ....................................................................................27
`
`Claim 36. The thin and substantially flexible integrated
`circuit of claim 24, wherein the thin semiconductor layer
`comprises monocystalline [sic] silicon. ....................................29
`
`Claim 37. The thin and substantially flexible integrated
`circuit of claim 24, wherein the thin semiconductor layer
`is formed from a semiconductor wafer. ....................................29
`
`Claim 38. The thin and substantially flexible integrated
`circuit of claim 24, wherein the thin semiconductor layer
`has a thickness of 50 microns or less. .......................................29
`
`Claim 53 ....................................................................................30
`
`Claim 83 ....................................................................................31
`
`10. Claim 86. The thin and substantially flexible integrated
`circuit of claim 83, further comprising a plurality of
`memory cell layers with at least one low stress silicon-
`based dielectric layer with a stress of less than 5×108
`dynes/cm2 tensile deposited on each of said memory cell
`layers in a stacked relationship to the thinned
`semiconductor layer. .................................................................32
`
`11. Claim 87. The thin and substantially flexible integrated
`circuit of claim 83, further comprising a plurality of
`integrated circuits in a stacked relationship to the thinned
`semiconductor layer, wherein each of said plurality of
`integrated circuits comprising an array of memory cells
`
`ii
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`

`
`Petition for Inter Partes Review
`Patent No. 8,907,499
`and at least one low stress silicon-based dielectric layer
`with a stress of less than 5×108 dynes/cm2 tensile. ...................33
`12. Claim 132. .................................................................................34
`
`C. Ground 2: Bertin, Poole, and Leedy ’695 Render the
`Challenged Claims Obvious ................................................................35
`
`1.
`
`2.
`
`3.
`
`4.
`
`5.
`
`6.
`
`7.
`
`8.
`
`9.
`
`Overview of Combination and Reasons to Combine ...............35
`
`Claim 12 ....................................................................................41
`
`Claim 13 ....................................................................................46
`
`Claim 24 ....................................................................................49
`
`Claim 36 ....................................................................................50
`
`Claim 37 ....................................................................................50
`
`Claim 38 ....................................................................................51
`
`Claim 53 ....................................................................................51
`
`Claim 83 ....................................................................................52
`
`10. Claim 86 ....................................................................................52
`
`11. Claim 87 ....................................................................................53
`
`12. Claim 132 ..................................................................................54
`
`IX. GROUNDS UNDER ALTERNATIVE CONSTRUCTIONS ......................56
`
`A. Ground 3 (Low Stress Dielectrics Terms): Hsu and Kowa
`Render Obvious the Challenged Claims .............................................56
`
`B. Ground 4 (Substantially Flexible Terms): Bertin and Leedy
`’695 Render Obvious the Challenged Claims .....................................58
`
`X.
`
`THE PROPOSED GROUNDS AND CONCURRENT PETITIONS
`ARE NOT REDUNDANT ............................................................................59
`
`XI. CONCLUSION ..............................................................................................60
`
`iii
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`

`
`
`
`Petition for Inter Partes Review
`Patent No. 8,907,499
`
`LIST OF EXHIBITS1
`Ex. 1001 U.S. Patent No. 8,907,499
`Ex. 1002 Declaration of Dr. Paul D. Franzon
`Ex. 1003
`Curriculum Vitae of Dr. Paul D. Franzon
`Ex. 1004 U.S. Patent No. 5,202,754 to Bertin et al., issued April 13, 1993
`Ex. 1005 U.S. Patent No. 5,162,251 to Poole et al., issued November 10, 1992
`Ex. 1006 U.S. Patent No. 5,354,695 to Leedy, issued October 11, 1994
`Ex. 1007
`Japanese Patent Publication No. 3-151337 to Kowa including
`Japanese-language version, English-language translation, and
`translation certification
`Ex. 1008 U.S. Patent No. 5,627,106 to Hsu, issued May 6, 1997
`RESERVED
`Ex. 1009
`RESERVED
`Ex. 1010
`Ex. 1011 U.S. Patent No. 5,426,072 to Finnila, Issued June 20, 1995
`RESERVED
`Ex. 1012
`RESERVED
`Ex. 1013
`RESERVED
`Ex. 1014
`RESERVED
`Ex. 1015
`Lim et al., The Impact of Wafer Back Surface Finish on Chip
`Ex. 1016
`Strength, 27th Annual Proceedings of Reliability Physics, April 11-
`13, 1989
`RESERVED
`Prosecution History of U.S. Patent No. 8,907,499 - Office Action
`dated May 29, 2013
`Prosecution History of U.S. Patent No. 8,907,499 - Response to
`Office Action dated June 20, 2013
`Prosecution History of U.S. Patent No. 8,907,499 - As-Filed Patent
`Application
`Prosecution History of U.S. Patent No. 12/497,652 - Response to
`Office Action dated September 26, 2013
`Prosecution History of U.S. Patent No. 12/497,653 - Response to
`
`Ex. 1017
`Ex. 1018
`
`Ex. 1019
`
`Ex. 1020
`
`Ex. 1021
`
`Ex. 1022
`
`
`
` 1
`
` Citations to non-patent publications are to the original page numbers of the
`
`publication, and citations to U.S. patents are to column:line number of the patents.
`
`iv
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`

`
`Petition for Inter Partes Review
`Patent No. 8,907,499
`
`Ex. 1023
`
`Ex. 1024
`
`Ex. 1025
`
`Ex. 1026
`
`Ex. 1029
`
`Ex. 1030
`
`Ex. 1031
`
`Ex. 1027
`Ex. 1028
`
`Office Action dated October 24, 2013
`Prosecution History of U.S. Patent App. No. 12/497,652 - Response
`to Office Action dated 4/5/13
`Prosecution History of U.S. Patent No. 5,915,167 - Response to
`Office Action dated April 28, 1998
`Prosecution History of U.S. Patent No. 5,915,167 - Response to
`Office Action dated September 8, 1998
`Prosecution History of U.S. Patent No. 8,629,542 - Response to
`Office Action dated July 30, 2012
`RESERVED
`Prosecution History of U.S. Patent No. 7,705,466 - Response to
`Office Action dated February 16, 2009
`Prosecution History of U.S. Patent No. 7,705,466 - Response to
`Office Action dated June 25, 2009
`Prosecution History of U.S. Patent No. 8,928,119 - Response to
`Office Action dated September 4, 2012
`Prosecution History of U.S. Patent No. 8,928,119 - Appeal Brief
`dated June 3, 2013
`Prosecution History of U.S. Patent No. 8,410,617 - Response to
`Office Action dated December 14, 2010
`Prosecution History of U.S. Patent Application no. 12/497,652 - Final
`Office Action dated June 3, 2013
`Prosecution History of U.S. Patent Application No. 12/497,652 -
`Express Abandonment dated November 20, 2014
`Prosecution History of U.S. Patent Application No. 12/497,653 -
`Advisory Action dated August 27, 2014
`Prosecution History of U.S. Patent Application No. 12/497,653 -
`Express Abandonment dated November 25, 2014
`RESERVED
`Ex. 1037
`RESERVED
`Ex. 1038
`Concept One CVD System Process Specifications from Novellus
`Ex. 1039
`Ex. 1040 Wolf et al., Processing for the VLSI Era, Volume 1 - Process
`Technology (1986).
`Ex. 1041 U.S. Patent No. 3,508,980 to Jackson et al., issued April 28, 1970
`Ex. 1042 U.S. Patent No. 3,044,909 to Shockley, issued July 17, 1962
`Fahey et al., Stress-induced dislocations in silicon integrated circuits,
`Ex. 1043
`IBM J. Res. Develop. Vol. 36, No. 2, March 1992
`Ex. 1044 Hass et al., Physics of Thin Films: Advances in Research and
`Development (1966)
`
`Ex. 1032
`
`Ex. 1033
`
`Ex. 1034
`
`Ex. 1035
`
`Ex. 1036
`
`v
`
`

`
`Ex. 1045
`
`Ex. 1048
`
`Petition for Inter Partes Review
`Patent No. 8,907,499
`EerNisse, E.P., Stress in thermal SiO2 during growth, Appl. Phys.
`Lett. 35(1), July 1, 1979
`Ex. 1046 Klokholm, Erik, Delamination and fracture of thin films, IBM J. Res.
`Develop., Vol. 31, No. 5, September 1987
`Ex. 1047 U.S. Patent No. 4,948,482 to Kobayashi et al., issued August 14,
`1990
`Isobe et al., Dielectric Film Influence on Stress-Migration, June 12-
`13 IEEE VMIC Conference (1990)
`Ex. 1049 Van de Ven, et al., Advantages of Dual Frequency PECVD for
`Deposition of ILD and Passivation Films, June 12-13 IEEE VMIC
`Conference (1990)
`Ex. 1050 U.S. Patent No. 5,160,998 to Itoh et al., issued November 3, 1992
`Ex. 1051 Garrou, Philip, Polymer Dielectrics for Multichip Module Packaging,
`Proceedings of the IEEE, Vol. 80, No. 12, December 12, 1992
`Ex. 1052 Grief et al., Warpage and Mechanical Strength Studies of Ultra Thin
`150MM Wafers, IEEE/CPMT Int’l Electronics Manufacturing
`Technology Symposium (1996)
`Tatsuno, Sheridan, Japan’s Push into Creative Semiconductor
`Research: 3-Dimensional ICs, Solid State Technology, March 1987
`Ex. 1054 Akasaka, Yoichi, Three-Dimensional IC Trends, Proceedings of the
`IEEE, Vol. 74, No. 12, December 1986
`Ex. 1055 Hayashi, Yoshihiro, Evaluation of Cubic (Cumulatively Bonded IC)
`Devices, 9th Symposium on Future Electron Devices, November 14-
`15, 1990
`Ex. 1056 Williams et al., Future WSI Technology: Stacked Monolithic WSI,
`IEEE Transactions on Components, Hybrids, and Manufacturing
`Technology, Vol. 16, No. 7, November 1993
`Crowley et al., 3-D Multichip Packaging for Memory Modules, MCM
`’94 Proceedings, 1994
`Ex. 1058 Malinak, David, Memory-Chip Stacks Send Density Skyward,
`Electronic Design, August 22, 1994
`Ex. 1059 Kuhn et al., Interconnect Capacitances, Crosstalk, and Signal Delay
`in Vertically Integrated Circuits, IEEE 1995
`RESERVED
`RESERVED
`RESERVED
`RESERVED
`RESERVED
`
`Ex. 1060
`Ex. 1061
`Ex. 1062
`Ex. 1063
`Ex. 1064
`
`Ex. 1053
`
`Ex. 1057
`
`vi
`
`

`
`Petition for Inter Partes Review
`Patent No. 8,907,499
`
`I.
`
`INTRODUCTION
`
`Samsung Electronics Co., Ltd.; Micron Technology, Inc.; and SK hynix Inc.
`
`(collectively, “Petitioner”) request inter partes review (“IPR”) of claims 12, 13, 24,
`
`36, 37, 38, 53, 83, 86, 87, and 132 (“Challenged Claims”) of U.S. Patent No.
`
`8,907,499 (“the ’499 patent”) (Ex. 1001), which, on its face, is assigned to Elm
`
`3DS Innovations, LLC (“Patent Owner”). This Petition presents several non-
`
`cumulative grounds of invalidity that the U.S. Patent and Trademark Office
`
`(“PTO”) did not consider during prosecution. These grounds are each reasonably
`
`likely to prevail, and this Petition, accordingly, should be granted on all grounds
`
`and the Challenged Claims should be cancelled.
`
`II. MANDATORY NOTICES UNDER 37 C.F.R. § 42.8
`
`Real Parties-in-Interest: The real parties in interest are: Samsung
`
`Electronics Co., Ltd.; Samsung Semiconductor, Inc.; Samsung Electronics
`
`America, Inc.; Samsung Austin Semiconductor, LLC; Micron Technology, Inc.;
`
`Micron Semiconductor Products, Inc.; Micron Consumer Products Group, Inc.; SK
`
`hynix Inc.; SK hynix America, Inc.; Hynix Semiconductor Manufacturing
`
`America, Inc.; and SK hynix Memory Solutions, Inc.
`
`Related Matters: Patent Owner has asserted the ’499 patent against
`
`Petitioner in Elm 3DS Innovations, LLC v. Samsung Elecs. Co., No. 1:14-cv-01430
`
`(D. Del.); Elm 3DS Innovations, LLC v. Micron Tech., Inc., No. 1:14-cv-01431 (D.
`
`1
`
`

`
`Petition for Inter Partes Review
`Patent No. 8,907,499
`Del.); and Elm 3DS Innovations, LLC v. SK hynix Inc., No. 1:14-cv-01432 (D.
`
`Del.). Patent Owner has also asserted related U.S. Patent Nos. 7,193,239;
`
`7,474,004; 7,504,732; 8,035,233; 8,410,617; 8,653,672; 8,791,581; 8,629,542;
`
`8,841,778; 8,496,862; 8,928,119; and 8,933,570 in one or more of these actions.
`
`Petitioner has already requested inter partes review of the following patents:
`
`7,193,239 (IPR2016-00388 and IPR2016-00393); 7,504, 732 (IPR2016-00395);
`
`8,629,542 (IPR2016-00390); 8,035,233 (IPR2016-00389); 8,410,617 (IPR2016-
`
`00394); 8,653,672 (IPR2016-00386); 8,796,862 (IPR2016-00391); 8,841,778
`
`(IPR2016-00387); 8,928,119 (IPR2016-00687); and 7,474,004 (IPR2016-00691).
`
`And Micron Technology, Inc. and SK hynix Inc. have already requested inter
`
`partes review of U.S. Patent No. 8,791,581 (IPR2016-00706 and IPR2016-00706).
`
`Petitioner is also concurrently filing another IPR petition on claims 1 and 49 of the
`
`‘499 patent.
`
`Counsel and Service Information: Lead counsel is John Kappos (Reg. No.
`
`37,861), O’Melveny & Myers LLP, 610 Newport Center Drive, 17th Floor,
`
`Newport Beach, California 92660, Tel.: 949.823.6900, Fax: 949.823.6994, email:
`
`PTABMICRONELM@omm.com; and backup counsel is Naveen Modi (Reg. No.
`
`46,224), PaulHastings LLP, 875 15th St. N.W., Washington, D.C., 20005, Tel.:
`
`202.551.1700, Fax: 202.551.1705, email: PH-Samsung-ELM-
`
`IPR@paulhastings.com; and Jason Engel (Reg. No. 51,654), K&L Gates LLP, 70
`
`2
`
`

`
`Petition for Inter Partes Review
`Patent No. 8,907,499
`W. Madison St., Suite 3100, Chicago, IL 60602, Tel.: 312.807.4236, Fax:
`
`312.827.8145, E-mail: jason.engel.PTAB@klgates.com. Petitioner consents to
`
`electronic service.
`
`III. PAYMENT OF FEES UNDER 37 C.F.R. § 42.15(a)
`
`The PTO is authorized to charge all fees due at any time during this
`
`proceeding, including filing fees, to Deposit Account No. 50-2862.
`
`IV. GROUNDS FOR STANDING
`
`Petitioner certifies that, under 37 C.F.R. § 42.104(a), the ’499 patent is
`
`available for IPR, and that Petitioner is not barred or estopped from requesting IPR
`
`of the ’499 patent on the grounds identified.
`
`V.
`
`PRECISE RELIEF REQUESTED
`
`Petitioner respectfully requests review and cancellation of the Challenged
`
`Claims as obvious in view of the grounds listed below.
`
`Part VII explains how certain claim terms should be construed. Part VIII
`
`explains in detail the following grounds, which show how the prior art teaches or
`
`suggests every feature of the Challenged Claims, as construed by Petitioner:
`
`Ground 1: U.S. Patent No. 5,627,106 (“Hsu”), in combination with U.S. Patent
`
`No. 5,354,695 (“Leedy ’695”), renders obvious the Challenged Claims under 35
`
`U.S.C. § 103; Ground 2: U.S. Patent No. 5,202,754 (“Bertin”), in combination
`
`3
`
`

`
`Petition for Inter Partes Review
`Patent No. 8,907,499
`with U.S. Patent No. 5,162,251 (“Poole”), and Leedy ’695 renders obvious the
`
`Challenged Claims under 35 U.S.C. § 103.
`
`In the event the Board adopts certain alternative constructions discussed
`
`below in Parts VII and IX, Petitioner submits the following additional grounds:
`
`Ground 3: Hsu, in combination with Japan Patent Pub. H3-151637 (“Kowa”) (Ex.
`
`1007)2, renders obvious the Challenged Claims under 35 U.S.C. § 103; and
`
`Ground 4: Bertin, in combination with Leedy ’695, renders obvious the
`
`Challenged Claims under 35 U.S.C. § 103.
`
`On its face, the ’499 patent claims a priority date of April 4, 1997.
`
`Therefore, for purposes of this proceeding, and without conceding that the claims
`
`are in fact entitled to this date, Petitioner has assumed a priority date of April 4,
`
`1997. Bertin issued on April 13, 1993, Poole issued on November 10, 1992, Leedy
`
`’695 issued on October 11, 1994, and Kowa published on June 27, 1991.
`
`Therefore, these references are prior art at least under 35 U.S.C. § 102(b). Hsu
`
`was filed on May 6, 1994, and issued on May 6, 1997, and is therefore prior art at
`
`least under 35 U.S.C. § 102(e).
`
`
`
` 2
`
` Ex. 1007 includes the Japanese version of Kowa (id. at 1-5), an English
`
`translation (id. at 6-12), and an affidavit required by 37 C.F.R. §42.63(b).
`
`4
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`

`
`Petition for Inter Partes Review
`Patent No. 8,907,499
`
`VI. THE ’499 PATENT
`
`A. Technical Background
`
`ICs are typically fabricated on a thin slice of silicon (a wafer) and
`
`“singulated” into individual devices (dice). Ex. 1002 at ¶17-19. A basic two-
`
`dimensional (“2D”) IC has a single, active circuit layer mounted in a package in a
`
`single plane. Id. Since the IC’s creation in 1958, designers have worked to
`
`improve computing power and efficiency of electronic structures. Id. at ¶20.
`
`IC designers have long thinned and polished substrates to create thin
`
`electronic circuits that could fit in ever-smaller devices. Id. at ¶21. Designers have
`
`also long relied on vertical interconnections to connect different vertical levels
`
`within an IC. Id. at ¶22. While reliability has always been a concern, many of the
`
`processes used in the fabrication of silicon ICs impose stress on silicon substrates
`
`that unacceptably affect the yield. Id. at ¶23. Consequently, substantial efforts
`
`have been made to study and improve stress management, including the use of low
`
`tensile stress materials and stress balancing. Id. at ¶¶24-37. By 1996, it was well
`
`known to thin and polish wafers, use TSVs to electrically connect layers in an IC,
`
`and to manage stress. Id. at ¶38; see also id. at ¶¶21-37.
`
`As performance enhancement through miniaturization became more
`
`challenging, three-dimensional (“3D”) IC development became one way to
`
`improve efficiency. Id. at ¶39. The benefits of 3D ICs have been known for over
`
`5
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`
`Petition for Inter Partes Review
`Patent No. 8,907,499
`30 years. Id. at ¶¶40-44. Not surprisingly, IC designers carried 2D techniques into
`
`3D designs—these techniques included thinning and polishing (id. at ¶¶45-46),
`
`TSVs to connect active device layers (id. at ¶¶44, 47-51), and stress management
`
`(id. at ¶¶44, 51).
`
`B. Overview of the ’499 Patent
`
`The ’499 patent generally describes “stacked integrated circuit memory,” but
`
`includes claims that are not explicitly limited to memory. Ex. 1001 at 1:7-8, 3:3-
`
`16. The ’499 patent describes “two principal fabrication methods,” which
`
`generally include the steps of thinning substrates, bonding substrates to form a
`
`vertical stack, and forming vertical interconnections passing through the substrates.
`
`Id. at 7:26-11:5. According to the ’499 patent, a semiconductor substrate is
`
`thinned by a grinding and polishing (or smoothing) process to a thickness of less
`
`than 50 µm, but explains that other well-known thinning techniques can instead be
`
`used. Id. at 9:12-41, 10:49. Additionally, the specification and claims of the ’499
`
`patent recite the use of low tensile stress dielectrics, which the specification
`
`acknowledges was described years before the earliest alleged priority date of the
`
`’499 patent by the named inventor in Leedy ’695. See, e.g., id. at 8:54-9:4, Claim
`
`4. Ex. 1002 at ¶¶ 54-68.
`
`6
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`

`
`Petition for Inter Partes Review
`Patent No. 8,907,499
`
`C. Level of Ordinary Skill in the Art
`
`One of ordinary skill in the art the time of the alleged invention of the ’499
`
`patent would have had at least a B.S. degree in electrical engineering, material
`
`science, or equivalent thereof, and at least 3-5 years of experience in the relevant
`
`field, e.g., semiconductor processing.3 Ex. 1002 at ¶¶15, 52.
`
`VII. CLAIM CONSTRUCTION
`
`An unexpired claim subject to IPR receives the “broadest reasonable
`
`construction in light of the specification of the patent in which it appears.” 42
`
`C.F.R. § 42.100(b).4 The Board may consider prosecution histories when
`
`determining the broadest reasonable construction of a claim. See, e.g., Microsoft
`
`Corp. v. Proxyconn, Inc., 789 F.3d 1292, 1298 (Fed. Cir. 2015). For purposes of
`
`this proceeding, Petitioner proposes constructions for the term(s) identified below.
`
`
`
` 3
`
` Petitioner submits the declaration of Dr. Paul D. Franzon (Ex. 1002), an expert in
`
`the field of the ’499 Patent (Ex. 1002 at ¶¶1-14), and Dr. Franzon’s CV (Ex. 1003)
`
`herewith.
`
`4 The ’499 patent may expire during this proceeding. After expiration, the claims
`
`should be construed according to the Phillips v. AWH Corp. standard applicable in
`
`district court. 415 3d 1303 (Fed. Cir. 2005). Under the Phillips standard, the
`
`Challenged Claims are unpatentable for the same reasons set forth herein.
`
`7
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`

`
`Petition for Inter Partes Review
`Patent No. 8,907,499
`Any remaining terms should be given their plain and ordinary meaning according
`
`to the “broadest reasonable construction” standard. Because the claim construction
`
`standard in this proceeding differs from the standard applicable to a district court
`
`litigation, Petitioner expressly reserves the right to argue in district court for a
`
`different construction for any claim term in the ’499 patent.
`
`A.
`
`“Substantially flexible . . . semiconductor substrate” (Claim 132) /
`“substantially flexible… semiconductor layer” (Claims 24, 53, 83)
`
`In light of the specification and intrinsic record of the ’499 patent, the
`
`broadest reasonable construction of “substantially flexible” when used to modify
`
`“semiconductor substrate” or “semiconductor layer” is “a semiconductor substrate
`
`[layer] that has been thinned to a thickness of less than 50 μm and subsequently
`
`polished or smoothed.”
`
`Acting as his own lexicographer, the Applicant defined “substantially
`
`flexible” when used to modify semiconductor substrate in the specification, which
`
`states: “Grind the backside or exposed surface of the second circuit substrate to a
`
`thickness of less than 50 μm and then polish or smooth the surface. The thinned
`
`substrate is now a substantially flexible substrate.” Ex. 1001 at 9:16-19; see also
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`id. at 3:18-21, 4:35-37.
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`The Applicant confirmed this definition during prosecution of the ’499
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`patent. The Examiner objected to certain claims for including the term
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`8
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`Petition for Inter Partes Review
`Patent No. 8,907,499
`“substantially flexible” as indefinite for failing to “clearly set for[th] the metes and
`
`bounds of the patent protection desired.”5 Ex. 1018 at 4. The Applicant overcame
`
`the objection by arguing that “substantially flexible” is unambiguous because it is
`
`“clearly explained in the specification”:
`
`With respect to the language “substantially flexible,” the meaning of
`this phrase as used in the claims is clearly explained in the
`specification including, for example, at page 18, lines 1-3. As
`described in this passage, a semiconductor substrate is caused to be
`substantially flexible by thinning it to 50 microns or less and polishing
`or smoothing the thinned semiconductor substrate to relieve stress.
`The phrase “substantially flexible” is used in the claims consistent
`with this description, which is unambiguous.
`
`Ex. 1019 at 9; Ex. 1020 at 18:1-3.
`
`Similarly, during prosecution of related U.S. Patent Application Nos.
`
`12/497,652 and 12/497,653, which also share the same specification as the ’499
`
`patent, the Applicant attempted to distinguish prior art by representing to the PTO
`
`that “[a] substantially flexible semiconductor substrate may be achieved by
`
`
`
` 5
`
` Petitioner reserves the right to challenge the validity of the claims under 35
`
`U.S.C. § 112 as indefinite for “failing to inform, with reasonable certainty, those
`
`skilled in the art about the scope of the invention.” Nautilus, Inc. v. Biosig Instr.,
`
`Inc., 134 S.Ct. 2120, 2124 (2014).
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`9
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`

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`Petition for Inter Partes Review
`Patent No. 8,907,499
`grinding until considerably thin, for example to a thickness of less than 50 microns,
`
`and polishing the resulting surface.” Ex. 1021 at 2; Ex. 1022 at 2.
`
`Accordingly, the Applicant clearly and unmistakably set forth a definition of
`
`the term “substantially flexible” when used to modify semiconductor substrate and
`
`expressed an intent to define the term. See Tempo Lighting, Inc. v. Tivoli, LLC,
`
`742 F.3d 973, 977-78 (Fed. Cir. 2014). Similarly, these clear and unmistakable
`
`statements by the Applicant limit the scope of the term. See In re Katz Interactive
`
`Call Processing Patent Litigation, 639 F.3d 1303, 1324 (Fed. Cir. 2011).
`
`Therefore, the proper construction of this term, when used to modify substrate or
`
`layer, under the broadest reasonable construction, is “a semiconductor substrate
`
`[layer] that has been thinned to a thickness of less than 50 μm and subsequently
`
`polished or smoothed.”6
`
`Moreover, “substantially flexible” is a term of degree that must be construed
`
`to have an objective standard of measurement—the term would otherwise be
`
`
`
` 6
`
` Any argument that Petitioner’s proposed constructions for the “substantially
`
`flexible” terms ignore the doctrine of claim differentiation should be rejected
`
`because the doctrine cannot overcome the Applicant’s unambiguous statements
`
`made during prosecution. See Seachange Int’l, Inc. v. C-COR, Inc., 413 F.3d
`
`1361, 1369 (Fed. Cir. 2005).
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`10
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`Petition for Inter Partes Review
`Patent No. 8,907,499
`indefinite, as the Examiner found during prosecution of the ’499 patent. See Ex.
`
`1018 at 4; Ex. 1002 at ¶¶71, 76. The Board has consistently found similar claim
`
`language to be terms of degree. See, e.g., MedShape Inc. v. Cayenne Med., Inc.,
`
`IPR2015-00848, 2015 WL 5453171, *5 (P.T.A.B. September 14, 2015)
`
`(“substantially different”). Claims that recite a term of degree are indefinite unless
`
`the patent specification “provide[s] ‘some standard for measuring that degree.’”
`
`MedShape Inc. v. Cayenne Medical, Inc., 2015 WL 5453171 at *5 (citing Seattle
`
`Box Co. v. Industrial Crate & Packing, Inc., 731 F.2d 818 (Fed. Cir. 1984)). Here,
`
`the intrinsic record provides only a single standard for determining whether a
`
`substrate is “substantially flexible”—whether the thickness of the substrate after
`
`thinning is less than 50 µm and then polished or smoothed. See Ex. 1001 at 9:16-
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`19, 3:18-21, and 4:35-37; Ex. 1019 at 9. Accordingly, under the applicable claim
`
`construction standard, Petitioner’s proposed construction should be adopted
`
`because it sets forth the only reasonable standard for measuring a term of degree
`
`that would otherwise render the claims indefinite.
`
`Petitioner believes Patent Owner may propose an unreasonably broad
`
`construction of this term, such as (i) “a semiconductor substrate that has been
`
`thinned to a thickness of less than 50 μm,” or (ii) “a semiconductor substrate that
`
`has been thinned to a thickness of 150 μm or less.” Under either of these
`
`constructions, the Challenged Claims would still be unpatentable in view of the
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`11
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`Petition for Inter Partes Review
`Patent No. 8,907,499
`prior art discussed herein because it teaches or suggests thinning semiconductor
`
`substrates to a thickness of less than 50 µm. See infra Part VIII.
`
`B.
`
`“substantially flexible circuit” (claims 12, 13 ) / “substantially
`flexible integrated circuit” (claims 24, 36, 37, 38, 83, 86, 87),
`“substantially flexible integrated circuit layer” (claim 132) /
`“substantially flexible structure” (claim 53)
`
`The broadest reasonable construction of “substantially flexible” when used
`
`to modify “circuit,” an “integrated circuit,” an “integrated circuit layer,” or a
`
`“structure” is “a [an] circuit [integrated circuit] [integrated circuit layer] [structure]
`
`having a semiconductor substrate that has been thinned to a thickness of less than
`
`50 μm and subsequently polished or smoothed, and where the dielectric material
`
`used in processing the semiconductor substrate must have a stress of 5×108
`
`dynes/cm2 tensile or less.”
`
`For example, the specification explains that each “circuit layer is a thinned
`
`and substantially flexible circuit with net low stress, less than 50 μm and typically
`
`less than 10 μm in thickness” (Ex. 1001 at 4:30-33), and that “[t]he thinned
`
`(substantially flexible) substrate circuit layers are preferably made with dielectrics
`
`in low stress (less than 5×108 dynes/cm2).” Id. at 8:54-56.
`
`During prosecution of related applications, the Applicant elaborated further
`
`to distinguish prior art. For example, during prosecution of U.S. Patent
`
`Application Nos. 12/497,652 and 12/497,653, which share the same specification
`
`12
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`

`
`Petition for Inter Partes Review
`Patent No. 8,907,499
`as the ’499 patent, the Applicant stated that “substantially flexible” when used to
`
`modify integrated circuit layer requires two features: (i) “the semiconductor
`
`material must be sufficiently thin, e.g., 50 microns or less,” and (ii) “the dielectric
`
`material used in processing the semiconductor material must be sufficiently low
`
`stress,” which, “[a]s set forth in the present specification, stress of 5 x 108
`
`dynes/cm2 or less has been demonstrated to satisfy this requirement.” Ex. 1023 at
`
`28.
`
`The Applicant confirmed this definition in a September 26, 2013 Response,
`
`stating that “a substantially flexible semiconductor substrate is a necessary but not
`
`a sufficient condition for a substantially flexible circuit layer,” because, “[f]or a
`
`circuit layer to be substantially flexible, Applicant has found that the dielectric
`
`material must have low tensile stress, for example, 5 x 108 dynes/cm2 tensile.” Ex.
`
`1021 at 2-3. See also Ex. 1019 at 9; infra Part VII.A.
`
`Accordingly, the Applicant clearly and unmistakably set forth a definition of
`
`the term “substantially flexible” when used to modify integrated circuit layer and
`
`expressed an intent to define the term. See Tempo, 742 F.3d at