United States Patent [191
`Toke et al.
`
`[54] NIJMIERICAL CONTROL SYSTEM WITH
`DOWNLOADING CAPABIIJTV
`
`[75]
`
`Inventors: Ronald J. Toke. Bratenahl Village;
`William A. Donne, Mentor, both of
`Ohio
`
`glen-Bradley Coupuy. Milwaukee,
`[73] Assignee:
`13.
`[21] Appl. No.: 350,927
`
`[22] Filed:
`
`Nov. 14, I977
`
`Int. Cl} ......................... GGIEF 3/02'. G06F I3/00
`[51]
`[52] us. cl. .................................................. .. 354/200
`[58] Field of Search
`364/200 MS File. 960 MS File
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`3,626,385
`3.14-4.03l
`3.810.104
`
`Bournnn ............................. .. 364/2111
`12/19?]
`7/1913 Avery et al.
`.
`366/2|!)
`
`5/1914 Merkley
`3602!!)
`OTHER PUBLICATIONS
`
`[1 11
`
`[45]
`
`4,138,718
`
`Feb. 6, 1979
`
`Bensaude et al.—"Host Processor Control of Satellite
`
`Disk Storage".
`
`Primary £.'xam:'ner—I-(srvey E. Springborn
`Attorney. Agent, orFt‘nn—-Queries dt Brady
`
`[57]
`
`ABSTRACT
`
`A numerical control system which employs a pro-
`grammed numerical control processor to perform the
`numerical control functions is coupled to a bulk storage
`device by s host computer. The bulk storage device
`stores a download library which includes not only part
`programs, but also system software programs and diag-
`nostic programs which may be downloaded to the nu-
`merical control system upon request. By downloading a
`system software program the numerical control capabil-
`ities of the system can be completely reconfigured to. in
`essence, provide I new mnchine.
`
`IBM TDB—voI. 14. No. II, Apr. 1972, pp. 34l8-3419-
`
`9Cl.|lns,22Ih-urln¢Fisures
`
`
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00755
`Page 1
`
`

`
`U.S. Patent
`
`Feb. 5, 1979
`
`Sheet 1 of 21
`
`4,138,718
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00755
`Page 2
`
`

`
`U.S. Patent
`
`Feb. 6, 1979
`
`Sheet 2 of 21
`
`4,138,718
`
`‘S43. 2
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00755
`Page 3
`
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`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00755
`Page 4
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`
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`PMC Exhibit 2075
`
`Apple v PMC
`|PR2016-00755
`
`Page 5
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00755
`Page 5
`
`
`
`
`

`
`U.S. Patent
`
`Feb. 6, 1979
`
`Sheet 5 of 21
`
`4,138,718
`
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`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00755
`Page 6
`
`
`
`
`
`
`
`

`
`U.S. Patent
`
`Feb. 6. 1979
`
`Sheet 5 of 21
`
`4,138,718
`
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`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00755
`Page 7
`
`
`
`
`
`
`
`

`
`U.S. Patent
`
`Feb. 6. 1979
`
`Sheet 7 of 21
`
`4,138,718
`
`IUT/OPU DATA _ BUS
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00755
`Page 8
`
`

`
`U.S. Patent
`
`Feb. 5, 1979
`
`Sheet 3 of2l
`
`4,138,718
`
`I29
`
`M0
`
`JG
`
`
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`BINARY
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`1:5.7
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`i
`
`I28
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00755
`Page 9
`
`

`
`U.S. Patent
`
`Feb. 6. 1979
`
`Sheet 9 of 21
`
`4,138,718
`
`FROM
`
`ST RT
`
`'-S-iig. BA
`
`DISABLE
`INTEFIRUPTS &
`TURN-OFF
`OUTPUTS
`
`F ETC H DOWN-
`LOAD REQUEST
`wono aauup
`T0 TRANSMIT
`SU BHOUTINE
`
`
`
`FETCH VERSION
`1.0. CHARACTER&
`JUMP TO
`TRANSMIT
`SUBROUTINE
`
`
`
`5”
`
`535
`
`526
`
`5
`
`27
`
`JUMP TO
`RECEIVE
`SUBROUTINE
`
`NEGATEG
`STORE RECORD
`SIZE AT
`"counr"
`
` lN|T1AL|ZE
`CHECKSUM
`
`IN
`B REGISTER
`
`
`
`
`
`
`52?
`
`5.30
`
`535
`
`JUMP TO
`RECEIVE
`suanourunc
`
`T0
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00755
`Page 10
`
`

`
`U.S. Patent
`
`Feb. 6. 1979
`
`Sheet no of 21
`
`4,138,718
`
` "3‘~ig. SB
`
`55l
`
`
`
`
`
`STORESTAHHNG
`ADDRESS or
`DOWNLOADED
`necono AT
`“ADDR"
`
`
`
`
`
` CHECK “ADDR"
`TO DETERMINE
`
`IF WITHIN
`
`COM MUNICATIONS
`PROGRAM
`
`
` INDICATE
`
`
`
`"ADDRESS ERROR"
`ON CRT 9
`
` JUMP TO
`
`RECEIVE
`
`SUBROUTINE
`
`
`
`STORE
`
`INSTRUCTION m
`
`
`MEMORY so
`
`AT LOCATION
`mnzcarco av
`“ADDR"
`
`
`
`535
`INCRE ME NT
`
`
`"A DDR" G"COUNT"
`
`£- UPDATE
`
`CHECKSUM
`AC CUMMULATOR
`
` 536
`
`PMC Exhibit 2075
`
`Apple v. PMC
`|PR2016-00755
`
`Page 11
`
`
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00755
`Page 11
`
`

`
`U.S. Patent
`
`Feb. 6, 1979
`
`Sheet 11 of 21
`
`4,138,718
`
`
`
`INDICATE
`"CHECKSUM
`
`ERROR"
`
`ON CRT 9
`
`
`
`
`
`‘Fig. 8c
`
`JUMP TO
`
`REC EIVE
`SUBROUTINE
`
`COMPARE
`
`CHECKSUM WORD
`WITH
`CHECKSUM
`ACCUMMULATOR
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00755
`Page 12
`
`

`
`U.S. Patent
`
`Feb. 6, 1979
`
`Sheet 12 or 21
`
`4,138,718
`
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`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00755
`Page 13
`
`
`
`
`
`
`
`

`
`
`
`US. Patent
`
`Feb. 6, 1979
`
`Sheet 13 of 21
`
`4,138,718
`
`‘$13. 10
`
`
`
`INITIALIZE
`FOR NEW
`PROGRAHI
`
`
`
`
`
`MODE
`
`?
`
`MRNUAL
`
`UPDATE
`
`CRT
`
`DISPLAY
`
`PMC Exhibit 2075
`
`
`
`EXECUTE
`ROUTINE
`
`
`CALL BLOCK
`
`
`
`DECODE
`
`AND SET UP
`
`
`
`
`
`
`
`Apple v. PMC
`|PR2016-00755
`
`Page 14
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00755
`Page 14
`
`

`
`US. Patent
`
`Feb-. 6, 1979
`
`Sheet 14 of21
`
`4,138,718
`
`
`
`
`
` BLOCK
`EXECUTE
`
`ROUTINE
`
`SET UP
`BLOCK
`EXECUTION
`FLAGS
`
`YES
`
`
`
`INITIAUZ
`
`#56 II DATA
`
`BUFFERS
`
`BLOCK
`‘DELETE
`
`?
`
`R ES ET
`
`EXCHANGE
`
`STATE OF
`pggwoug
`amcx
`
`
`
`-ICTIVE AND
`TEMPORARY
`BUFFER POINT =‘
`
`
`
`
`
`PMC Exhibit 2075
`
`Apple v. PMC
`|PR2016-00755
`
`Page 15
`
`‘5~1'c5. HA
`
`
`
`#436 II DATA
`
`BLOCK
`
`RELEASE
`
`
`
`
`
`
`
`
`
`
`EXECUTE
`PRELUDE
`Fuucnous AND
`flA|(E BLOCK
`ACTIVE
`
`
`
`UPDATE
`POINTERS
`TO NEXT
`BLOCK
`
`ENABLE
`INTERPOLATION
`
`SET UP
`
`NEXT
`
`BLOCK
`
`
`
` INITIATE
`TAPE REQDER
`IF STORAGE
`AVAILABLE
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00755
`Page 15
`
`

`
`U.S. Patent
`
`Feb. 6, 1979
`
`Sheet 15 of 21
`
`4,138,718
`
`@
`
`%Ic_-5. 11B
`
`
`
`UPDATE
`
`CRT
`CRT
`
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`DISPLAY
`
`
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`
`
`
`BLOCK END
`POINT
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`
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`MODE
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`
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`
`
`
`E X EC UTE
`
`POST LU DE
`
`
`
`FUNCTIONS
`
`
`OFFSETS
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00755
`Page 16
`
`

`
`US. Patent
`
`Feb. 6, 1979
`
`Sheet 16 of 21
`
`4,138,718
`
`
`
`|O.24
`MSEC.
`INTERRUPT
`
`
`'5-2.5. 12A
`
`SAVE
`
`ALL
`
`INTERRUPT
`
`'
`
`I
`
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`
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` IO IISE
`
`NO
`
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`PRELUDE B
`POSTLUDE
`FLAGS
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`
`
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`
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`
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`I56
`FLAG S EXECUTE
`
`STATUS OF
`SENSING
`DEVICES
`
`
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`VARIOUS
`BLOCK DATA
`
`IE7
`
`MACHINE
`DEPENDQNT
`SOFTWARE
`ROUTINE
`
`INTERPOLATION
`
`
` OUTPUT
`
`STATUS OF
`OPERATING
`DEVICES
`
`
`
`I94
`
`
`
`PMC Exhibit 2075
`
`Apple v. PMC
`|PR2016-00755
`
`Page 17
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00755
`Page 17
`
`

`
`U.S. Patent
`
`Feb. 6, 1979
`
`Sheet 17 of 21
`
`4,138,718
`
`@
`
`‘Sig. 123
`
`END
`OF B;.OCK
`
`"0
`
`'55
`
`
`
`RESET
`POSTLUDE
`FL$
`
`ANY
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`CODES
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`
`REQUEST
`
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`
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`
`V53
`
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`
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`
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`
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`
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` EMERGENCY
`STOP
`PROC ESSOR
`
`
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`
`Eon
`STOP
`
`?
`
`SUBROUTINE
`
`EXIT REGISTERS
`
`SET TIMED
`INTERRUPT
`FLAG T0
`NOT BUSY
`
`RESTORE
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00755
`Page 18
`
`

`
`U.S. Patent
`
`Feb. 6, 1979
`
`Sheet 18 of 21
`
`4,138,718
`
`‘Sig. ISA
`
`5|B
`
`5L5
`
`514
`
`5'2-
`
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`
`
`
`ab
`
`DISSABLE
`INTERRUPTS
`TUFIN OF
`OUT PUT DEV ICES
`
`
`
`
`
`
`
` RECEIVE
`
`REPLY FROM
`HOST COMPUTER
`AND DISPLAY ON
`CRT 9
`
`
`
`DISPLAY
`“READY”
`
`ON CRT 9
`
`
`
`INPUT COMMAND
`TRANSMIT
`'
`FROM
`COMMAND
`KEYBOARD 7
`TO HOST
`
`COM PUTER
`
`
`
`
`
`
`
` "suauon"
`COMMAND?
`
`5|?’
`
`
`
`
`'mGNoFF"
`COMMAND?
`
`
`
`
`
`DISPLAY
`
` DOW NLOAD
`COMMAND 7.’
`
` ON CRT 9
`
`YES
`
`PMC Exhibit 2075
`
`Apple v. PMC
`|PR2016-00755
`
`Page 19
`
`
`
`SZI
`
`TRANSMIT
`DOWNLOAD
`COMMAND TO
`
`HOST COMPUT ER
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00755
`Page 19
`
`

`
`U.S. Patent
`
`Feb. 5, 1979
`
`Sheet 19 of 21
`
`4,138,718
`
`REPLY FROM
`
`HOST COMPUTER
`AND DISPLAY
`
`
`
` RECBVE
` 522.
`
`
`IT ON CRT9
`
`
`
`'5."-‘.3
`
`
`
`
`
`TYPE "1"
`
`
`
`CODE
`
`REPLY
`
`
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`
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`‘1oAo2" OF
`
`RESIDENT
`
`?
`
`
`
`
`
`commumcnrnous
`PROGRAM
`
`"5~I<5. 13B
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00755
`Page 20
`
`

`
`U.S. Patent
`
`Feb. 6, 1979
`
`Sheet 20 of 21
`
`4,138,718
`
`‘$13. 14-
`
`REQUEST
`FROM NC
`ACHINE
`
`
`
`
`
`REC EIVE AND
`
`STORE MACHINE
`
`
`IDENTIFICATION
`
`
`
`
`TRANSMIT
`
`
`"BUSV"
`nscawg AND
`
`'*"555“‘5E
`STORE FILE
`
`T0 NC
`N
`no TYPE
`
`AME A
`MACHINE
`
`
`
`
`
`
`
` TRANSMIT
`
`ANY
`
`SECURITY
`ERROR
`REQUEST
`FROM NC
`CLE)?\FIED
`MESSAGE TO
`
`MACHINE
`NC MACHINE
`
`
`
`
`
`
`
`TRANSMIT
`
`
`
`
`READ DATA
`DATA RECORD
`RECORD FROM
`TO NC
`DOWNLOAD
`MACHINE
`
`LIBRARY
`
`
`
`CONV ERT
`
`DATA RECORD
`
`
`TO ASCII
`
`C HARAC T ERS
`
`554-
`
`550
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00755
`Page 21
`
`

`
`U.S. Patent
`
`Feb. 6, 1979
`
`Sheet 21 of 21
`
`4,138,718
`
`.
`$13‘ 15
`
`RESHDENT
`COMMUNICATIONS
`PROGRAM (I28 LINES}
`
`HIGHEST 4K MEMORY ADDRESS
`
`00000
`
`551
`
`
`
`READ/WRITE
`
`MEMORY
`
`G-lg. 16
`
`PMC Exhibit 2075
`
`Apple v. PMC
`|PR2016-00755
`
`Page 22
`
`
`
`PMC Exhibit 2075
`Apple v. PMC
`IPR2016-00755
`Page 22
`
`

`
`1
`
`4,133,718
`
`NIJMERICAL CONTROL SYSTEIVI WITH
`DOWNLOADING CAPABILITY
`
`BACKGROUND OF 'I'I-[E INVENTION
`
`The field of the invention is numerical control sys-
`tems, and particularly. numerical control systems of the
`type which employ programmed processors as the
`means for carrying out the numerical control functions.
`Such a numerical control system is known in the art
`as a computer numerical control or "CNC" and they
`are characterized generally by their use of a pro-
`grammed minicomputer or microprocessor in lieu of
`hardwired logic circuitry. Such a system which em-
`ploys a programmed processor is disclosed in U.S. Pat.
`No. 4,038,533 which issued on July 26, 1977 and is
`entitled "Industrial Control Processor System." Al-
`though CNC systems are programmable and do there-
`fore otter a certain amount of flexibility, as a practical
`matter the system program which determines the basic
`operational characteristics of the system is seldom ai-
`tered once the system is attached to a specific ma.cl1i.ne
`tool. For example,
`the CNC system may be pro-
`grammed to provide full contouring for a three-axis
`milling machine without automatic tool changer and
`with certain "canned cycles." That software system is
`usually not altered during the life of the machine despite
`the fact that for much of the time the machine tool may
`not require contouring capability and could make better
`use of the memory space occupied by the circular and
`linear interpolation programs.
`The flexibility afforded by the use ofa programmable
`processor in a numerical control system has thus never
`been fully realized in prior systems.
`SUMMARY OF THE INVENTION
`
`The present invention relates to a numerical control
`system in which a system program may be readily
`downloaded from a library stored in a bull: storage
`device. More specifically. the invented numerical con-
`trol system includes a main memory. a processor, a
`read-only memory which stores a resident communica-
`tion program. means for transferring the resident com-
`munications program from the read-only memory to the
`main memory and for initiating the execution of said
`program by the numerical control system processor. a
`storage device for storing a plurality of programs in-
`cluding a system program for the numerical control
`system, and a host processor coupled to said storage
`device and said numerical control system processor and
`being responsive to a download command generated by
`said numerical control system processor during its exe-
`cution of the resident communications program to
`download said system program to the main memory,
`wherein the numerical control system processor jumps
`from the resident communications program to said
`downloaded system program after the download has
`been completed.
`A general object of the invention is to download a
`system program to the memory of a CNC system. If the
`main memory is completely empty. as for example, after
`a prolonged power failure or a malfunction which
`erases part or all of the system program, a new system
`program can be downloaded from the download library
`in the storage device by initiating the execution of the
`resident communications program.
`Another object of the invention is to enable the oper-
`ator to select a system program from the download
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`library. A manual data entry means such as a keyboard
`is associated with the numerical control processor and
`the download command is selected by the operator to
`identify a specific program in the download library. In
`this manner different system programs may be down-
`loaded to alter the capabilities of the numerical control
`system to meet the requirements of the machine tool to
`which it is attached and the part being machined.
`The foregoing and other objects and advantagw of
`the invention will appear from the following descrip-
`tion. In the description reference is made to the accom-
`panying drawings which form a part hereof. and in
`which there is shown by way of illustration :1 preferred
`embodiment of the invention. Such embodiment does
`not necessarily represent the full scope of the invention,
`however, and reference is made to the claims herein for
`interpreting the breadth of the invention.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. I is a perspective View of the system of the
`present invention connected to a machine tool;
`FIG. 2 is a perspective view of the numerical control
`system which forms part of the system of FIG. 1 with
`the enclosure door open;
`FIG. 3 is a block diagram of the system of FIG. 1;
`FIGS". 4a and 4b are a block diagram of the industrial
`control processor which forms part of the system of
`FIG. 3;
`FIG. 5 is a block diagram of the arithmetic and logic
`processor which forms part of the industrial control
`processor of FIG. 46;
`FIG. 6 is a block diagram of the input/output cir-
`cuitry which forms a part of the industrial control pro-
`cessor of FIG. -to;
`FIG. 7 is a schematic diagram of the priority encoder
`circuit which forms part of the industrial control pro-
`cessor of FIG. 40;
`FIGS. 811-: are a flow chart of the resident communi-
`cations program which forms part of the industrial con-
`trol processor of FIG. 4;
`FIG. 9 is a flow chart of a system program which
`may be stored in the numerical control processor mem-
`0173
`FIG. II] is a flow chart of the main controller routine
`which forms part of the software system of FIG. 9;
`FIGS. 11a and uh is a flow chart of the block exe-
`cute routine which forms part of the software system of
`FIG. 9,
`FIGS. 12:! and 12b is a flow chart of the ten millisec-
`ond timed interrupt routine which forms pa.rt of the
`software system of FIG. 9;
`FIGS. 13:: and 13b is a flow chart of a program called
`COMPAC which is stored in the download library;
`FIG. 14 is a flow chart of the download program
`(DNLDNC) stored in the host computer memory of
`FIG. 3;
`FIG. 15 is a representation of the contents of the
`numerical control system memory at one stage of the
`download procedure; and
`FIG. 16 is a block diagram of the host computer of
`FIG. 1.
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENT
`
`Referring to FIG. 1, a numerical control system is
`housed in a cabinet 1 and connected through a cable 2 to
`s multi-function machine tool with automatic tool
`changer 3. The numerical control system controls the
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`motion of a cutting tool 4 along two or more sites of
`motion in response to a part program which is read
`from a tape reader 5. In addition, the numerical control
`system operates in response to commands read from the
`tape reader 5 to control auxiliary functions on the ma-
`chine tool 3, such as automatic tool selection and chang-
`ing from a tool magazine 6, pallet selection and chang-
`ing, spindle speed and coolant operation. The imple-
`mentation of such auxiliary functions involves the sens-
`ing of one-bit signals generated by numerous input de-
`vices such as limit switches, selector switches. and
`photo-electric cells. which are mounted to the machine
`tool 3, and the operation of numerous output devices
`such as solenoids. lights. relays and motor starters. The
`numbers and types of such input and output devices. as
`well as the manner in which they are operated. will
`vary considerably from machine to machine.
`The numerical control system includes a programma-
`ble interface which allows it to be easily interfaced with
`machine tools of any make and model. This interface is
`accomplished by entering a control program comprised
`of programmable controller-type instnictions through a
`keyboard 7. When this control program is executed the
`systeln operates as a programmable controller to selec-
`tively sense the status of the particular input device on
`the machine tool to be controlled and to selectively
`operate the output devices thereon to provide the de-
`sired manner of operation.
`Mounted to the door of the cabinet 1 immediately
`above the keyboard 7 is an amociatcd cathode ray tube
`(CRT) display 9. Mounted to the right of the keyboard
`7 and CRT display 9 is a main control panel 10 which
`includes a variety of pushbuttons and selector switches
`for providing standard operator controls such as mode
`selection. feedrate override. spindle speed override. jog
`select. axis select, etc. One of the pushhuttons enables
`the keyboard 7 to enter data.
`Referring particularly to FIGS. 2 and 3. the elements
`of the numerical control system are mounted within the
`cabinet 1 to allow easy access for inspection, testing and
`maint-enance.Thckcyboard7ismountcdtothecabinet
`door 11 along with the tape reader 5. CRT display 9 and
`main control panel 10. A secondary control panel 12
`mounts inmtcdiately above the tape reader 5 and all of
`these system I./0 devices are connected to a numerical -15
`control processor 13 which is housed at the bottom of
`the cabinet I. More specifically. the tape reader 5 con-
`nects through a cable 14. the secondary control panel 12
`connects through a cable 15, the keyboard 7 connects
`through a cable 25. the CRT display 9 connects through
`a cable 1'1, and the main control panel 10 connects
`through a cable 18 to a wire harness 19 which leads to
`the processor 13. A processor front panel 26 provides a
`number of manually operable pusltbuttons and visual
`indicators which relate to the operation ofthe procmor
`I3 and which are connected thereto through a bus 21.
`Two input/output (l/O) interface racks 20 and 21 are
`mounted in the cabinet 1 above the processor 13 and are
`oonncctcd thereto by a wiring harn 22 which extends
`upward along their left-hand side. A main power supply
`23 mounts above the 1/0 interface rack 21 and a mem-
`
`ory power supply 24 mounts on the left side wall of the
`cabinet 1.
`The 1/0 interface racks 20 and 21 mount a variety of
`input circuits and output circuits on closely spaced,
`vertically disposed printed circuit boards (not shown in
`the drawings}. These input and output circuits serve to
`couple the industrial control processor 13 with the
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`cable 2 that leads to the machine tool 3 and may include
`input circuits for sensing the status of limit. selector and
`pushbutton switches such as that disclosed in U.S. Pat.
`No. 3,643,115 entitled "Interface Circuit for Industrial
`Control Systems.” and output circuits for driving sole-
`noids and motors such as that disclosed in U.S. Pat. No.
`3,745,546 entitled "Controller Output Circuit." The
`input circuits also include position feedback accumula-
`tors which receive fcedback data from the position
`transducers on the machine tool 3 and the output cir-
`cuits include registers for providing axis motion com-
`mand words to the machine tool servo mechanisms.
`Referring particularly to FIGS. 1-3, the numerical
`control system 1 is connected to a host computer 500
`through a cable 501 in what is known in the art as a
`DNC configuration. The cable 50] connects to a uni-
`versal asynchronous receiver/transmitter (UAR/T) 8
`which is mounted within the numerical control proces-
`sor housing 13 and it in tum is connected to the numeri-
`cal control processor 13 through the wire harness 19.
`The UAR/T 8 is treated as another input/output device
`by the processor 13 as will be described in more detail
`hereinafter.
`The host computer 500 is a general purpose digital
`computer such as the Model 7/32 manufactured by
`lnterdata. Inc. As will be described in more detail here-
`inafter. it is coupled to the cable 50! by a UAR/'1" 502
`which connects to an I/O port on a computer processor
`550. The processor 550 is coupled to a read.’write mem-
`ory 551 through a bus 552 and a bull: storage device 507
`in the form of a disc couples to the memory 551 and it
`serves to store not only a large number of part pro-
`grams. but also. a variety of numerical control system
`software packages which may be downloaded to the
`numerical control system 1. Programs stored in the host
`computer memory 551 enable the computer to commu-
`nicate with the numerical control system 1 and to man-
`age the library of programs stored in the bulk storage
`507.
`As will be described in more detail hereinafter, an
`operator at the numerical control system 1 can call up a
`particular part program or a particular numerical con-
`trol software system by generating commands through
`the keyboard 7. Referring particularly to FIG. 3. a
`communications package stored in a numerical control
`system memory 34 couples these commands to the host
`computer Sill. which in turn reads the selected part
`program or numerical control system software package
`out of the bulk storage 50'! and downloads it to the
`numerical control system 1. The downloaded program
`is stored in the memory 34 at a location determined by
`the communications package. To better understand the
`nature of a nuinerical control aottware system package
`which can be downloaded from the bulk storage 507 to
`the memory 34, a description of a preferred numerical
`control system — both hardware and software — will
`now be made. This preferred numerical control system
`is sold commercially by the Allen-Bradley Company as
`the Model 7360 B and it is described in detail in U.S.
`Pat. No. 4,038,533.
`Referring particularly to FIGS. Ga and 4b, the numer-
`ical control processor 13 is organized around a sixteen-
`bit bidirectional processor data bus 30. Data is moved
`from one element of the processor to another through
`this data bus 30 in response to the execution of a micro-
`instruction which is held in a 24-bit micro-instruction
`register 31. Each such micro-instruction indicates the
`source of the data to be applied to the data bus 30, the
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`|PR2016-00755
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`destination of the data, and any operations that are to be
`performed on that data. The micro-instructions are
`stored in a micro-program read-only memory 32, and
`one is read out every 200 nano-seconds through a bus 33
`to the micro-instruction register 31. The read-only
`memory 32 stores a large number of separately address-
`able, or selectable, micro-routines. each of which is
`comprised of a set of micro-instructions. To enable the
`processor 13 to perform a desired function, the appro-
`priate micro-routine is stored in the read-only memory
`32 and it is selected for execution by a 16-bit macro-
`instruction which is stored in a read/write main mem-
`ory 34.
`The main memory 34 is comprised -of -1-K by 1 dy-
`namic MOS RAMS which are organized to store up to
`32.000 I6-bit words. Macro-instructions and data are
`read out of and written into the main memory 34
`through a l6-bit memory data register 35 which con-
`nects to the processor data bus 30. The memory words
`are selected, or addressed, through a 15-bit ory
`address register 36 which also connects to the processor
`data bus 30. To write into the main memory 34, an
`address is first loaded into the memory sddras register
`36 by applying a logic high voltage to its clock lead 29.
`The data to be loaded appears on the processor data bus
`3|] and is gated through the memory data register by
`applying a logic high voltage to its data in clock lead 21.
`A logic high voltage is then applied to a read/write
`control line 34’ on the memory 34 to complete the load-
`ing operation. Data or a macro-instruction is read out of
`an addressed line of the main memory 34 when a
`READ micro-instruction is executed. A logic low volt-
`age is applied to the read/write control line 34' and a
`logic high voltage is applied to a data out enable line 28
`on the memory data register 35. The data word is mo-
`mentarily stored in the register 35 and is subsequently
`transferred through the processor data bus 30 to the
`desired destination.
`
`In response to the execution ofa micro-routine called
`FETCH, which includes the READ micro-instruction,
`a macro—in-struction is read from the main memory 34
`and coupled to a 16-bit macro-instruction register 37
`through the data bus 30. The macro-instruction is stored
`in the register 37 by a logic high voltage which is ap-
`plied to a macro-instruction register clock line 37'. Cer-
`tain of the macro-instructions include operation codes
`which are ooupied through an instruction register bus
`39 to a macro-decoder circuit 38, and other instructions
`also include a bit pointer code which is coupled through
`the same instruction register bus 39 to a bit pointer
`circuit 40. The bit pointer circuit 10 is a binary decoder
`having four inputs connected to the least significant
`digit outputs of the macro—instruction register 37 and
`having a set of 16 outputs connected to respective leads
`in the processor data bus 30. In response to the execu-
`tion of a selected micro-instruction (MASK), a logic
`high voltage is applied to a terminal 41. and the bit
`pointer circuit 40 drives a selected one of the sixteen
`leads in the processor data bus 30 to a logic low voltage.
`The bit pointer circuit 40 facilitates the execution of
`certain programmable controller type macro-instruo
`tions.
`In response to an operation code in a macro-instruc-
`tion stored in the register 37, one of the micro-routines
`in the read-only memory 32 is selected. The operation
`code is applied to the macro-decoder circuit 38 which
`enables one of four mapper proms 42-45 and addresses
`a selected line in the enabled mapper prom. Each line of
`
`6
`the mapper proms -62-45 stores a twelve-bit rnicr0-rou-
`tine starting address, which when read out, is coupled
`through a micro-program address bus 46 to preset a
`twelve-bit micro-program sequencer 47. The sequencer
`47 is a presettable counter which includes a load tenni-
`nal 52, an increment terminal 53 and a clock terminal 54.
`The clock terminal 54 is driven by a five-megahertz
`clock signal which is generated by a processor clock
`circuit 85 that is coupled to the sequencer 47 through an
`AND gate I6. Each time a logic high clock pulse is
`applied to the terminal 54 on the micro-program se-
`quencer 47, it is either preset to an address which ap-
`pears on the bus 46 or it is incremented one count. Con-
`currently. the micro-instruction register 31 is clocked
`through a line 8! and AND gate 88' to read and store
`the micro-instruction which is addressed by the micro-
`program sequencer 41'. The AND gates 86 and 88 can
`be disabled in response to selected codes in a micro-
`instruction to decouple the 5 ml-Iz clock. Such decou-
`pling of the clock 85 from the sequencer 47 occurs. for
`example, during input and output operations to allow
`data one micro-second to propagate.
`Each micro-second which is read out of the read-only
`memory 32 to the micro-instruction register 31 is cou-
`pled through a micro-instruction bus 31a to a micro-
`instruction decoder circuit 18 which is also coupled to
`the clock line 88. The micro-instructions are decoded
`and executed before the next clock pulse is fipplied to
`the terminal 54 on the micro-program sequencer 47.
`Each micro-instruction is comprised of a plurality of
`separate codes called micro-orders which are each sepa-
`rately decoded to enable one or the processor elements.
`Each micro-routine stored in the micro-program
`read-only memory 32 is tenninated with a special mi-
`cro-instruction which includes a code, or micro-order,
`identified hereiuafier by the mnemonic BOX or EOXS.
`When coupled to the micro-instruction decoder circuit
`48, this code causes a logic high voltage to be generated
`on an BOX line 49 to a priority mapper prom 50. If the
`industrial control processor 13 is in the RUN mode. the
`starting address of the FETCH micro-routine is read
`from the priority mapper prom 50 and is applied to the
`micro-sequencer 47 through the bus 46. The n1icro-
`instruction decoder circuit 48 also generates a logic
`high voltage on a preset line 51 which connects to the
`load terminal 52 on the micro-program sequencer 47 to
`preset the sequencer 47 to the starting address of the
`FETCH micro-routine.
`As indicated above, the FETCH micro-routine func-
`tions to read the next macro-instruction to be executed
`from the main memory 34, couple it to the macro-
`instruction register 37, and initiate the execution of that
`macro-instruction. The last micro-instruction in the
`FETCH micro-routine includes a code which is identi-
`fied hereinafter by the mnemonic MAP. This micro-
`instruclion code causes the micro-instruction decoder
`circuit 48 to generate a logic high voltage to the macro-
`decoder circuit 38 through a MAP line 52 and to
`thereby initiate decoding of
`the macro-instruction
`which is stored in the macro-instruction register 37. A
`logic high voltage is also generated on the preset line 51
`to load the micro-program sequencer 4'7 with the start-
`ing address of the micro-routine called for by the de-
`coded macro-instruction.
`As shown in FIG. 46, mathematical and logical oper-
`ations are performed by the industrial control processor
`13 in an arithmetic and logic processor 55 which con-
`nects to the processor data bus 30 and to the micro-
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`instruction decoder circuit 48 through a bus 56. Refer-
`ring particularly to FIG. 5. the arithmetic and logic
`processor 55 includes a 16-bit “L“ register 57 which has
`inputs that connect to the leads in the processor data bus
`30 and a corresponding set of outputs which connect
`through a bus 58 to the "13" inputs ofa I6-bit arithmetic
`and logic unit (ALU) 59. Data on the bus 31] is clocked
`into the L register 51 when a logic high is applied to a
`lead 60 and the L register 51' is cleared when a logic
`high is applied to a lead 61. The leads 60 and 61 connect
`to the micro-instruction decoder circuit 48 through the
`bus 56 and are thus controlled by selected micro-
`instructions.
`The ALU 59 is comprised of four commercially
`available arithmetic logic units combined with a com-
`mercially available full carry look-ahead circuit to per-
`form high speed functions such as add, substract. decre-
`ment and straight transfer. The ALU 59 has a set of 16
`“A" inputs which connect directly to the leads in the
`processor data bus 30 and a set of four function-select
`lines 62 which connect to the micro-instruction decoder
`circuit 48 through the bus 56. In response to selected
`micro-instructions. the ALU 59 performs functions on
`data applied to its A and 8 inputs and generates the
`16-bit results to a sliifter circuit 63 through a bus 64.
`Also, the ALU 59 generates signals to an ALU de-
`coder 114 which indicate when the result of a logical or
`arithmetic function is zero. all "ones,” odd, negative or
`when it causes an overflow or a carry. The existence of
`such a condition is separately tested by micro-orders, or
`codes in micro-instructions which enable the ALU de-
`coder 114 through the bus 56. The existence of the
`tested condition results in the generation of a logic high
`on a skip line 115 which connects to the decoder 48.
`The existence of an overflow condition in the ALU
`59 can also be stored in an overflow flip-flop 116 when
`a logic high is applied to its clock temiinal through a
`line 117 by the decoder circuit 48. The Q output on the
`flip-flop 116 connects to the ALU decoder 114 and its
`condition can be tested by an appropriate micro-order.
`A system flag flip-flop 118 connects to the ALU de-
`coder 114 and it can be clocked in response to an appro-
`priate micro-order through a line 119 from the micro-
`