4,390,898
`[11]
`_
`[19]
`United States Patent
`
`
`[45]Bond et al. Jun. 28, 1983
`
`[541
`Us}
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`Ottawa; Leslie J. Crane, Nepean, all
`of Canada
`
`nventors:
`
`[73] Assignee: Northern Telecom Limited, Montreal,
`-
`Canada
`
`OTHER PUBLICATIONS
`NASA Tech Brief, vol. 3, No. 1, MSC—l6843, Spring
`197g_
`Primary Examiner—$. C. Buczinski
`Attorney, Agent, or Fzrm—-—R. Haley Haley
`[57]
`ABSTRAC1.
`A scrambler scrambles a video signal by replacing its
`vertical intervals with dummy video signal lines, and
`1
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`zontal sync. pulses of the scrambled video signal. An
`unsmmbler derives. the. i"f°"“a‘i°" “Om the h°YiZ°'1'
`tal sync. pulses, which 1t regenerates, and decodes the
`information and uses it to generate a vertical interval of
`correct timing to replace the dummy lines of the scram-
`bled video signal, thereby producing an unscrambled
`video signal reproducible on a conventional TV re-
`ceiver. The scrambling is further enhanced by varying
`the number of dummy lines which are used to replace
`different vertical intervals, thereby producing a video
`signal of variable field length, which is not susceptible
`0f ’e¢°’di“8-
`
`16 Claims, 9 Drawing Figures
`
`[21] ADPL N0-3 245,373
`.
`I221
`F11ed=
`Man 23,1981
`[51]
`Int. cm ............................................... H04N 7/15
`52 U.S. Cl. .................................. .. 358/119- 358/120;
`[
`]
`’ 358/123
`[58] Field of Search ................ 358/119, 120, 122, 123
`[55]
`References Cited
`U'S' PATENT DOCUMENTS
`2,972,008
`2/1961 Ridenour etal. ................. .. 358/123
`3,184,S37
`5/1965 C0u1'tet81-
`173/51
`3313330 4/1967 B355 --------
`178/5-1
`3’813’482
`5/1974 Blower '' '‘‘ '
`‘ ' '‘ ' " 178/5'1
`:§';?:':'t‘
`5/1981 Shutterly
`6/1982 McGuire
`7/1982 Payne et al.
`
`
`
`.. 358/120
`358/122
`...................... .. 358/122
`
`4,266,243
`4,333,107
`4,338,628
`
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`
`PMC Exhibit 2021
`
`Apple v. PMC
`|PR2016-00754
`
`Page 1
`
`PMC Exhibit 2021
`Apple v. PMC
`IPR2016-00754
`Page 1
`
`

`

`U.S. Patent
`
`Jun. 28, 1983
`
`‘
`
`Sheet1of6
`
`4,390,898
`
`
`
`PROGRAM
`SOURCE
`
`CHANNEL
`CONVERTER TRANSMITTER
`
`
`
`
`
` SCRAMBLER
`
`SCRAMBLED
`VIDEO
`
`
`
`
`
`UNSCRAMBLER
`ENCRYPTION
`8 PROGRAM
`DATA
`INTERFACE
`
`
` TELEPHONE
`
`
`2/
`
`CONTROL,DATA
`COLLECTMN,
`8 ELUNG
`CENTRE
`
`22
`
`INTERFACE
`
`CENTRAL
`OFHCE
`
`/8
`
`FIG.
`
`I
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`.90
`
` PROGRAM
`
`SOURCE
`
`TO TRANSMWTER
`
`
`
`
`
`
`CONTROL
`8 SYNC.
`GENERATOR
`
`
`
`SELECTOR
`
`SCRAMBLED
`
`
` VIDEO
`BLANKWG
`LEVEL
`
`
`
`PMC Exhibit 2021
`
`Apple v. PMC
`|PR2016-00754
`
`Page 2
`
`
`
`FIG. 9
`
`DATA FROM
`INTERFACE
`
` DATA
`PROCESSOR
`
`PMC Exhibit 2021
`Apple v. PMC
`IPR2016-00754
`Page 2
`
`

`

`U.S. Patent
`
`Jun. 28, 1983
`
`Sheet 2 of6
`
`4,390,898
`
`vmgo
`p
`|N UT
`
`SCRAMBLED
`VIDEO
`OUTPUT
`
`
`FILTER 8:
`
`
`200
`208
`F”'TER
`EQUALIZER
`
`VIDEO
`BUXNKING
`
`LEVEL
`
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`
`206‘ 207
`
`MEMORY
`UMT
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`CONTROL H DATA
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`
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`
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`
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`CIRCUIT
`
`PROCESSOR
`
`205
`DATA FROM
`INTERFACE
`
`FIG. 2
`
`VIDEO
`IN
`
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`
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`0/E
`
`S YNC
`SEPARATOR
`
`
`
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`
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`EXTRACTOR
`
`FREQUENCY
`
`DIVIDERS
` 300
`30/
`
`302
`
`FIG; 3
`
`PMC Exhibit 2021
`
`Apple v. PMC
`|PR2016-00754
`
`Page 3
`
`PMC Exhibit 2021
`Apple v. PMC
`IPR2016-00754
`Page 3
`
`

`

`U.S. Patent
`
`Jun. 28, 1933
`
`Sheet 3 of6
`
`4,390,898
`
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`PMC Exhibit 2021
`
`Apple v. PMC
`|PR2016-00754
`
`Page 4
`
`PMC Exhibit 2021
`Apple v. PMC
`IPR2016-00754
`Page 4
`
`
`
`
`
`
`
`

`

`U.S. Patent
`
`Jun. 28, 1983
`
`Sheet4 of6
`
`4,390,898
`
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`PMC Exhibit 2021
`Apple v. PMC
`IPR2016-00754
`Page 5
`
`
`
`
`

`

`U.S. Patent
`
`Jun.28,1983
`
`Sheet5 of6
`
`4,390,898
`
`66%?
`
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`
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`
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`
`
`
`PMC Exhibit 2021
`
`Apple v. PMC
`|PR2016-00754
`
`Page 6
`
`PMC Exhibit 2021
`Apple v. PMC
`IPR2016-00754
`Page 6
`
`

`

`U.S. Patent
`
`Jun. 28, 1983
`
`Sheet 6 of 6
`
`4,390,898
`
`
`
`M°3”';,@TB°R
`FILTER
`
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`8/9
`
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`
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`
`
`
`PMC Exhibit 2021
`
`Apple v. PMC
`|PR2016-00754
`
`Page 7
`
`PMC Exhibit 2021
`Apple v. PMC
`IPR2016-00754
`Page 7
`
`

`

`1
`
`4,390,898
`
`SCRAMBLING AND UNSCRAMBLING VIDEO
`SIGNALS IN A PAY TV SYSTEM
`
`This invention relates to subscription television (pay
`TV) systems, and is particularly concerned with a
`method of and apparatus for scrambling and unscram-
`bling video signals for use in such systems.
`It is known in the art of pay TV systems to scramble
`a video signal before broadcasting it, with the intent
`that only authorized persons, equipped with an appro-
`priate unscrambler, should be able to unscramble the
`video signal for viewing on a conventional television
`receiver,
`in return for payment of a fee. The video
`signal maybe scrambled in a variety of ways, with or
`without simultaneous scrambling of the accompanying
`, audio signal. For example, Court et al. U.S. Pat. No.
`3,184,537, issued May 18, 1965 discloses a pay TV sys-
`tem in which video signal scrambling is effected by
`suppressing to a constant grey level horizontal and
`vertical synchronizing (sync) signals and blanking inter-
`vals, unscrambling being enabled by composite sync
`pulses which are modulated upon the normal audio
`carrier. Bass U.S. Pat. No. 3,313,880 discloses a pay TV
`system in which the nature of the ordinary sync signals
`is changed, and additional signals having the nature of
`the ordinary sync signals but having a different timing
`are transmitted as part of the video signal to produce
`unsynchronized operation of television receivers not
`equipped with unscramblers. Blonder U.S. Pat. No.
`3,813,482 issued May 28, 1974 discloses a pay TV sys-
`tem in which scrambling of the video signal is effected
`by alternately depressing and not depressing to blanking
`level, at a rate of about 10 Hz, the vertical sync signals
`to produce a shifting, rolling picture on an unauthorized
`television receiver, a keying signal for unscrambling the
`video signal at an authorized receiver being modulated
`on the audio carrier.
`
`Such known pay TV systems have the disadvantage
`that the security of the system exists entirely in the
`scrambling scheme. In other words, anyone acquiring
`or making an appropriate unscrambler can unscramble
`the scrambled signal(s) without payment of any fee. In
`order to provide a more secure pay TV system, which
`makes it more difficult to unscramble the scrambled
`
`signal(s) without payment of fees, it is known to supply
`a code periodically and separately from the broadcast
`video signal to authorized subscribers of the pay TV
`system, which code must be compared with a code
`broadcast with the scrambled video signal in order to
`enable unscrambling. For example the separately sup-
`plied code can be supplied monthly to each authorized
`subscriber by mail in a system as described in Sherman
`U.S. Pat. No. 4,081,832 issued Mar. 28, 1978 or via a
`non-dedicated telephone line in a system as described in
`Block et al. U.S. Pat. No. 4,163,254 issued July 31, 1979.
`The security of such systems exists partly in the coding
`scheme and partly in the scrambling scheme.
`As disclosed in a co-pending application Ser. No.
`251,085 by Y. J. Aminetzah filed on Apr. 6, 1981 and
`entitled “Method of Controlling Scrambling and Un-
`scrambling in a Pay TV System”, the entire disclosure
`of which is hereby incorporated herein by reference,
`the coding scheme used in a pay TV system can be
`made highly secure, so that it is difficult or impossible
`for unauthorized persons to gain access within a reason-
`able time to a proper code to effect unscrambling of the
`scrambled signal(s) in the normal manner. However, the
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`45
`
`50
`
`55
`
`65
`
`
`
`2
`use of such a highly secure coding scheme does not
`alone assure the security of the pay TV system. On the
`contrary, the highly structured nature and information
`redundancy in the scrambled signal(s) of the known
`scrambling schemes discussed above makes it possible
`for unauthorized persons to effect unscrambling di-
`rectly from the scrambled signal(s), by-passing any
`coding scheme which may be used. In this respect, it is
`observed that in the known scrambling schemes there is
`a high correlation from line to line and from field to
`field in the scrambled video signal, which correlation
`may be utilized to facilitate unscrambling by unautho-
`rized persons.
`Accordingly, a need exists to provide a more secure
`video signal scrambling scheme, which is less suscepti-
`ble to direct unscrambling and which can be used in
`conjunction with a secure. coding schemeto facilitate
`provision of a secure pay TV system. An object of this
`invention is to provide a method of and apparatus for
`scrambling a video signal in a pay TV system by means
`of which this need may be fulfilled. Further objects are
`to provide a method of and apparatus for unscrambling
`the scrambled video signal, and to provide a pay TV
`system embodying such scrambling and unscrambling
`apparatus.
`According to one aspect this invention provides a
`method of scrambling a video signal, comprising video
`signal lines and vertical intervals, to produce a scram-
`bled video signal, said method comprising replacing
`each vertical interval by dummy video signal lines and
`separately providing information relating to the timing
`of the replaced vertical intervals of the scrambled video
`signal, wherein different numbers of dummy video sig-
`nal lines are used to replace different vertical intervals,
`whereby the field length of the scrambled video signal
`is varied.
`
`Thus the conventional vertical synchronizing infor-
`mation of the video signal is completely replaced, in the
`scrambled video signal, by dummy video signal lines
`which are indistinguishable by a conventional television
`receiver from the normal video signal lines of the video
`signal. In consequence, without unscrambling, a televi-
`sion receiver supplied with the scrambled video signal
`would produce a vertically unsynchronized and un-
`watchable picture.
`The separately provided information conveniently
`indicates the start of each replaced vertical interval, and
`is conveniently provided as part of the scrambled video
`signal. Preferably the information is modulated onto
`horizontal
`line synchronizing information forming a
`part of each video signal line. In this case the scrambled
`video signal reproduced on a conventional television
`receiver without unscrambling is not only vertically
`unsynchronized but also largely horizontally unsyn-
`chronized, making it even more unwatchable.
`In order to provide further security to a pay TV
`system using this method of scrambling, the information
`is preferably encoded in accordance with an encryption
`key, which can be recurrently changed and provided
`only to authorized subscribers of the pay TV system to
`enable proper unscrambling of the scrambled video
`signal.
`The use of different numbers of dummy video signal
`lines to replace different vertical intervals inhibits unau-
`thorized unscrambling of the scrambled video signal by
`persons using a known form of vertical interval genera-
`tor to synchronize a conventional television receiver to
`receive the scrambled video signal. The scrambled
`PMC Exhibit 2021
`
`Apple v. PMC
`|PR2016-00754
`
`Page 8
`
`PMC Exhibit 2021
`Apple v. PMC
`IPR2016-00754
`Page 8
`
`

`

`4,390,898
`
`3
`video signal consequently has a non-standard and vari-
`able ‘field length, rendering unauthorized unscrambling
`in this manner ineffective in vertically synchronizing
`the resultant picture. A further advantage provided in
`this respect is that the video signal, even after proper,
`authorized, unscrambling, has a variable field length
`which inhibits proper operation of a video signal re-
`corder which may be used to try to record the video
`signal for subsequent use or duplication.
`According to another aspect, the invention provides
`a method of scrambling a video signal, comprising
`video signal lines and vertical intervals, to produce a
`scrambled video signal which comprises said video
`signal lines and dummy video signal lines in place of
`said vertical intervals, said method comprising the steps
`of: storing the video signal lines of the video signal to be
`scrambled sequentially in a memory and reading them
`sequentially from the memory to constitute the video
`signal lines of the scrambled video signal; re-reading
`video signal lines from the memory to produce said
`dummy video signal lines of the scrambled video signal,
`different numbers of video signal lines being re-read
`from the memory to produce dummy video signal lines
`to replace different vertical intervals, whereby the field
`length of the scrambled video signal is varied; and sepa-
`rately providing information relating to the timing of
`the replaced vertical intervals.
`In accordance with another aspect of the invention,
`there is provided apparatus for scrambling a video sig-
`nal, comprising video signal lines and vertical intervals,
`to produce a scrambled video signal, said apparatus
`comprising: a memory unit; means for storing the video
`signal lines sequentially in the memory unit; means for
`providing an indication of the timing of each vertical
`interval relative to the video signal lines stored in the
`memory unit; means for reading the video signal lines
`sequentially from the memory unit, the reading means
`being responsive to said indication to re-read video
`signal lines from the memory unit to produce dummy
`video signal lines in place of each vertical interval, the
`reading means re-reading different numbers of video
`signal lines to replace different vertical intervals, said
`video signal lines sequentially read from the memory
`unit and said dummy video signal lines constituting the
`scrambled video signal; and means for providing infor-
`mation relating to the timing of each replaced vertical
`interval of the scrambled video signal.
`The apparatus preferably includes means for selec-
`tively removing horizontal line synchronizing pulses
`from the video signal lines of the scrambled video signal
`in dependence upon said information.
`According to yet another aspect, the invention pro-
`vides a subscription television system comprising: a
`scrambling apparatus comprising means for replacing
`each vertical
`interval of a video signal, comprising
`video signal lines and vertical intervals, by a plurality of
`dummy video signal lines to produce a scrambled video
`signal, different vertical intervals being replaced by
`different numbers of dummy video signal lines whereby
`the scrambled video signal has a variable field length,
`and means for providing information relating to the
`timing of each replaced vertical interval of the scram-
`bled video signal; means for distributing said scrambled
`video signal and said information to at least one un-
`scrambling apparatus; and at least one said unscram-
`bling apparatus comprising means responsive to said
`information for generating vertical intervals each hav-
`ing a timing coincident with the timing of said dummy
`
`5
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`45
`
`50
`
`55
`
`60
`
`65
`
`4
`video signal lines of the scrambled video signal, and
`means for replacing said dummy video signal lines of
`the scrambled video signal by said vertical intervals to
`produce an unscrambled video signal.
`Preferably,
`said scrambling apparatus comprises
`means for modulating horizontal
`line synchronizing
`pulses of the video signal lines of the scrambled video
`signal with said information, whereby the distributing
`means distributes said information as part of the scram-
`bled video signal with which it is supplied, and said
`unscrambling apparatus comprises means for deriving
`said information from the horizontal line synchronizing
`pulses of the video signal lines of the scrambled video
`signal and for regenerating said horizontal line synchro-
`nizing pulses.
`The invention will be further understood from the
`following description with reference to the accompany-
`ing drawings, in which:
`FIG. 1 illustrates a pay TV system including ‘a scram-
`bler and an unscrambler which operate in accordance
`with this invention;
`FIG. 2 shows a block diagram of the scrambler which
`includes a timing extractor, a memory unit, a control
`circuit, and a data processor;
`FIG. 3 shows a block diagram of the timing extractor;
`FIG. 4 shows a block diagram of the memory unit;
`FIG. 5 shows a block diagram of the control circuit
`and the data processor;
`FIG. 6 is a flow chart illustrating the operation of the
`data processor;
`FIG. 7, which is on the same sheet as FIG. 4, is a
`timing diagram illustrating the format of data which is
`transmitted with the scrambled video signal;
`FIG. 8 shows a block diagram of the unscrambler;
`and
`
`FIG. 9, which is on the same sheet as FIG. 1, shows
`a block diagram of a simplified form of scrambler spe-
`cifically for use where the TV program source is at the
`same location as the scrambler.
`
`Referring to FIG. 1, there is shown therein parts of a
`pay TV system in which video signals from a program
`source 10 are scrambled in a scrambler 11, the resultant
`scrambled video signals and audio signals from the pro-
`gram source being supplied to a transmitter 12 for
`broadcasting to subscribers of the pay TV system. As
`shown, the audio signals are not scrambled, but they
`could also be scrambled in known manner if desired.
`The audio signal path from the program source 10 to
`the transmitter 12 may also include a delay unit, (not
`shown), for example providing a signal delay of 30 ms,
`(the duration of one television field), to keep the timing
`of the transmitted audio signals matched to the average
`timing of the scrambled video signals. The broadcast
`signals are illustratively supplied to a subscriber’s home
`via a cable 13, but they could alternatively be supplied
`by electromagnetic radiation, directly or via a satellite
`link.
`
`The subscriber’s home includes a conventional chan-
`nel converter 14, television receiver 15, and telephone
`16, the latter being connected via a conventional tele-
`phone line 17 to a telephone central office 18. An un-
`scrambler 19 is coupled between the output of the chan-
`nel converter 14 and the input of the television receiver
`15, and is also coupled via an interface circuit 20 to the
`telephone line 17. The interface circuit 20 is preferably
`of the type described in a co-pending patent application
`Ser. No. 247,229, filed on Mar. 25, 1981 by T. H. Murto
`and S. D. Alvey, entitled “Interface Circuits for Con-
`PMC Exhibit 2021
`
`Apple v. PMC
`|PR2016-00754
`
`Page 9
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`PMC Exhibit 2021
`Apple v. PMC
`IPR2016-00754
`Page 9
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`5
`nection to Non-Dedicated Telephone Lines”, the entire
`disclosure of which is hereby incorporated herein by
`reference.
`
`4,390,898
`
`The pay TV system also includes a control, data
`collection, and billing centre 21, which can be located at
`the program source 10, scrambler 11, and transmitter
`12, or at the telephone central office 18, or separately
`from both. In any event the centre 21 is coupled via an
`appropriate interface 22 to the telephone central office
`18 for communicating recurrently with each unscram-
`bler 19 via the relevant telephone line 17, and is cou-
`pled, either permanently or when required via a tele-
`phone or data transmission line, to the scrambler 11 for
`supplying encryption and program data thereto. As an
`alternative, the program data may instead originate in
`the program source 10, and be supplied from there to
`both thescrambler 11 and the centre 21.
`The centre 21 recurrently, for example monthly,
`supplies encryption and program data to the scrambler
`11, which scrambles the video signals supplied to it in
`the manner described below and in dependence upon
`the encryption data, and also inserts the program data
`into the scrambled video signals. In order to enable each
`authorized unscrambler 19 to unscramble the scrambled
`signals when desired, the centre 21 periodically supplies
`thereto, via the interfaces 22 and 20 and via the tele-
`phone central office 18, a code (monthly code) which in
`conjunction with a device code individual to the sub-
`scriber enables proper operation of the unscrambler.
`This coding scheme is described fully in the co-pending
`application by Y. T. Aminetzah already referred to, to
`which reference is directed in this respect.
`FIG. 2 shows a block diagram of the scrambler 11.
`The video input signal from the program source 10 is
`conducted via a 4.2 MHz low-pass anti-aliasing filter
`200 to a timing extractor 201 and to the input of an
`analog-digital (A-D) converter and latch 202. The A-D
`converter samples the analog video signal at a fre-
`quency fs, supplied by the timing extractor 201, and
`equal to four times the video signal color subcarrier
`frequency fb, and linearly converts each sample into an
`8-bit digital value which is stored in the latch. This
`gives 910 digital samples per horizontal line, for an
`NTSC video signal for which the color subcarrier fre-
`quency fb is 3.579545 MHz. These digital samples are
`written into, and subsequently read from, a memory
`unit 203 under the control of a control circuit 204 and a
`data processor 205. A selector 206 is controlled by the
`processor 205 to supply either the digital samples read
`from the memory unit 203 or a digital video blanking
`level to a latch and digital—analog converter 207, which
`operates at the frequency fs to latch the digital values
`supplied thereto and to convert them into an analog
`video signal. This analog video signal is filtered and
`equalized in a 4.2 MHz low-pass filter and a (sin x)/x
`equalizer, shown as a single block 208, whose output
`constitutes the scrambled video output signal. The tim-
`ing extractor 201 supplies various timing signals to the
`units 203, 204, and 205, as well as the signal fs to the
`units 202 and 207. The data processor 205 is supplied
`with the encryption and program data from an interface
`(not shown) which is coupled to the centre 21.
`The timing extractor 201 is shown in greater detail in
`FIG. 3. A color burst extractor 300 extracts the color
`burst from each horizontal line of the incoming video
`signal and supplies it to a color burst phase locked loop
`(PLL) 301, which regenerates the color burst frequency
`fb. This is supplied to a further PLL including an oscil-
`
`10
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`15
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`20
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`25
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`30
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`35
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`40
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`45
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`50
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`55
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`65
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`6
`lator having a frequency 40 fb, whose output is fre-
`quency divided to produce the various frequency sig-
`nals indicated in FIG. 3 and described below. This
`further PLL and the frequency dividers are shown as a
`single block 302. The incoming video signal
`is also
`supplied to a sync separator 303, which derives the
`composite sync signals from the video signal and trig-
`gers a line counter 304 to count the horizontal lines of
`each field. The output signal ff of the line counter 304,
`which is a logic 0 during each vertical interval, is fre-
`quency-div__i“ded by two in a field counter 305 to produce
`a signal O/E which changes state each field, and whose
`state thus corresponds to the phase of the color burst of
`the incoming video signal. The counters 304 and 305 are
`synchronized by a signal f produced in the block 302
`and having ten times the color subcarrier frequency fb.
`The block 302 also produces the signal fs=4 fb already .
`described, a signal fl having a frequency which is one-
`thirteenth the frequency fs, a signal fh having the hori-
`zontal line frequency, and a signal NG also having the
`horizontal line frequency and which is a logic 0 during
`each horizontal line sync pulse of the video signal. Thus
`the various timing signals have the following frequen-
`c1es:
`f= 35.79544 MHz
`fs= 14.31818 MHz
`fl = 1.1014 MHz
`fli=I7I_G=15.734 kHz
`ff= 59.94 Hz
`0/E=29.97 Hz
`FIG. 4 illustrates the memory unit 203 in greater
`detail. This unit comprises 104 TTL 64 kbit RAMs
`(random access memories),
`together with associated
`ECL to TTL and TTL to ECL converters, shown as a
`single block 400. The RAMS are cyclically controlled
`and addressed, by address and control signals supplied
`by the control unit 204, for write-in and read-out of the
`digital video signal. In view of the relatively slow speed
`of each memory access cycle, the digital video signal is
`written into and read from the RAMs 13 8-bit words at
`a time,
`1 bit of each word being written into or read
`from a respective one of the 104 RAMS. Accordingly,
`the 8-bit video signal words from the A-D converter
`and latch 202 are shifted into a shift register 401 under
`the control of the signal fs, and the words are trans-
`ferred 13 at a time to a latch 402 under the control of the
`
`signal fl, to be written into the RAMs. Conversely, the
`8-bit words are read out from the RAMs and stored in
`an output latch 403 13 at a time under the control of the
`control circuit 204, and are loaded in parallel from the
`latch 403 into a shift register 404 under the control of
`the signal fs to constitute the digital scrambled video
`output of the memory unit 203. The number of 13 words
`written into and read from the RAMs is selected in view
`of the speed of the RAMs and the number of 910 sam-
`ples per horizontal line of the video signal, to provide a
`convenient number of 70 memory access cycles each
`horizontal line.
`The control circuit 204 is shown to the left, and the
`data processor 205 is shown to the right, of a broken line
`500 in FIG. 5. The control circuit 204 includes a modu-
`lo-65 counter 501, a PROM 502, and a latch 503 for
`producing control signals and selecting address signals,
`by means of an address selector 504, for each memory
`access cycle. The counter 501 is clocked by the signal f
`to increment its count, and for each count the PROM
`502 is addressed to produce a set of control signals
`which are latched in the latch 503 under the control of
`
`PMC Exhibit 2021
`
`Apple v. PMC
`|PR2016-00754
`
`Page 10
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`PMC Exhibit 2021
`Apple v. PMC
`IPR2016-00754
`Page 10
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`4,390,898
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`20
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`7
`8
`the signal f. The control signals in the latch 503 control
`515, and sets the signal N/V to l (opposite to the new
`the cyclical operation of the RAMS (block 400) and
`state of the signal SELECT). The new address which is
`latch 403 of the memory unit and the selection of a write
`latched in the latch 515 is different from the current
`address from a bus 505 or a read address from a bus 506
`read address, which is now offset from the write address
`5 by the offset contained in the latch 511 which with the
`for supply to the RAMs.
`signal SELECT=0 is selected by the selector 509. The
`The write address on the bus 505 is produced by a
`comparator 518 no longer detects equality and the sig-
`16-bit synchronous counter 507 which is clocked by the
`nal EQ remains 0.
`signal fl, so that the incoming video signal words are
`The offset stored in the latch 511 is selected so that
`written cyclically into successive memory locations.
`The read address on the bus 506 is produced by adding 10 now picture signal lines from another part of the mem-
`to the current write address, in a modulo 215 adder 508,
`ory are read out instead of the vertical interval signals.
`an offset which is selected by a selector 509 from a latch
`The address which is stored in the latch 515 is selected
`510 or a latch 511, and latching the sum in a latch 512
`in relation to this offset so that this reading of picture
`under the control of the signal fl. The selector 509 is
`signal lines instead of vertical interval signals continues
`controlled by a signal ‘SELECT’ produced at the Q 15 for a total of approximately 21 lines, i.e. for approxi-
`mately the duration of the vertical interval. At the end
`output of a D-type flip-flop 513, which signal is also
`supplied to a microprocessor 514 in the data processor
`of this period the comparator 518 again detects equality
`205. The microprocessor 514 supplies the offsets to the
`of addresses as described below. For example, in a par-
`latches 510 and 511, and supplies a read address to a
`ticularly simple situation the offset stored in the latch
`latch 515, via a common bus 516 under the control of
`511 may be equivalent to 21 picture lines less than the
`offset stored in the latch 510. In this situation the ad-
`respective latch loading signals on_li_nes 517. The micro-
`processor also supplies a signal N/V to the data input D
`dress stored in the latch 515 can remain unchanged in
`of the flip-flop 513. A comparator 518 compares the
`response to the interrupt to the microprocessor 514. On
`read address on the bus 506 with the read address stored
`the read address reaching the vertical interval start
`in the latch 515 and, when the compared addresses are 25 address after reading of a field of picture lines, the selec-
`the same, produces an output signal which is gated with
`tor 509 is controlled to cause the last 21 lines of the field
`the signal fi in an AND gate 519 to produce a signal EQ
`to be re-read instead of the following vertical interval
`which is supplied to the clock input CK of the flip-flop
`signals. When the vertical interval start address is again
`513 and as an interrupt signal to the microprocessor 514.
`reached, the selector 509 is controlled to cause the pic-
`The microprocessor 514 is also supplied with a vertical 30 ture lines of the next field to be read, as described be-
`interval start address from a latch 520; this is the write
`low.
`address on the bus 505 which exists at the start of a
`On the comparator 518 again detecting equality after
`vertical interval of the video signal and which is latched
`approximately 21 lines, as before the flip-flop 513 is
`in the latch 520 under the control of the signal ff.
`triggered to change the signal SELECT back to 1, so
`The components 507 to 520 of the control circuit 204 35 that the read address again becomes offset from the
`and the data processor 205 operate as follows. As al-
`write address by the contents of the latch 510, and the
`ready explained, the incoming video signal words are
`microprocessor 514 is again interrupted to read the
`written cyclically into the memory, and the start ad-
`signal SELECT, set the signal N/V to O, and to update
`dress of each vertical interval is stored in the latch 520.
`the contents of the latches as further described below.
`Reading from the memory of the video signal words of
`It should be appreciated from the above description
`picture lines (i.e. lines not in the vertical interval) takes
`that the vertical interval signals of each field of the
`place sequentially after a delay, or offset, which is deter-
`incoming video signal are replaced by repeated,
`mined by the contents of the latch 510. Accordingly,
`dummy, picture lines to produce the scrambled video
`during such reading, with the signals EQ=O, N/V =0,
`signal. The lines which are repeated may be constant,
`and SELECT: 1, the selector 509 is controlled to sup-_ 45 for example they may be the last lines of the previous
`ply the offset from the latch 510 to the adder 508, where
`field as described above, but are preferably varied re-
`this offset is added to the write address to produce the
`currently, eg. for successive fields, in order to make
`read address. The offset is stored in the latch 510 by the
`unauthorized descrambling of the scrambled video sig-
`microprocessor 514 as described below, and is an inte-
`nal more difficult. The dummy picture lines are selected
`gral multiple of 70 so tha