United States Patent
`
`[19]
`
`Pires
`
`[54] PAY TELEVISION SYSTEM UTILIZING
`BINARY CODING
`
`[75]
`
`Inventor: H. George Pires, Parlin, N.J.
`
`[73] Assignee:
`
`Teleglobe Pay-TV System, Inc.
`
`[21] Appl. No.: 706,929
`
`[22] Filed:
`
`July 19, 1976
`
`Int. C13 ............................................. .. H04N 1/44
`[51]
`[52] U.S. C1. .................................... .. 358/122; 358/84;
`358/123; 358/124
`[58] Field of Search .................. 358/122, 123, 124, 84
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`3,668,307
`3,789,131
`3,801,732
`3,878,322
`3,886,302
`3.9l9,462
`3,924,059
`3.934.079
`4,025,948
`
`............................. 358/86
`Face et al.
`6/1972
`.. 358/122
`1/1974 Hamey
`. 358/124
`4/1974 Reeves
`358/84
`4/1975
`Sullivan
`358/86
`5/1975 Kosco ......
`. 358/124
`11/1975 Hartung
`.. 358/124
`12/1975 Horowitz
`358/86
`1/1976 Bamhart ..
`5/1977
`Loshin ................................ .. 358/122
`
`Primary Examiner—S. C. Buczinski
`
`[57]
`
`ABSTRACT
`
`[11]
`
`[45]
`
`4,068,264
`
`Jan. 10, 1978
`
`the vertical retrace interval. The code number signals
`are also processed in accordance with a program assign-
`ment code to change or leave unchanged a predeter-
`mined characteristic of the television signal. Periodi-
`cally, program identification signals, each signifying a
`program identification number, are inserted into the
`television signal
`instead of the binary code number
`signals. At the receiving end, the program identification
`signals are utilized to address a random access memory
`which furnishes program assignment signals. The pro-
`gram assignment" signals control logic circuits to pro-
`cess the code number signals in accordance with the
`same program assignment code utilized at the transmit-
`ter. The output of these logic circuits is then utilized to
`decode the received encoded signal. Further, means are
`furnished to record the program identification number
`in the random access memory at the receiver for billing
`purposes, if the subscriber indicates acceptance of the
`program. Both this recording and the decoding of the
`encoded signal are impeded if a catagory switch at the
`decoder furnishes a catagory selection number which
`does not correspond to a catagory selection number
`inserted into the encoded television signal at the trans-
`mitting end.
`
`At the sending end randomly generated binary code
`number signals are inserted into predetermined lines of
`
`11 Claims, 7 Drawing Figures
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`PMC Exhibit 210
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`Apple v. PMC
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`2/2
`
`PMC Exhibit 2106
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`IPR2016-00753
`Page 1
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`

`
`U.S. Patent
`
`Jan. 10, 1978
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`Apple v. PM
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`PMC Exhibit 2106
`Apple v. PMC
`IPR2016-00753
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`PMC Exhibit 2106
`Apple v. PMC
`IPR2016-00753
`Page 3
`
`
`

`
`U.S. Patent
`
`Jan. 10, 1978
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`Apple v. PMC
`|PR2016-00753
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`Page 4
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`PMC Exhibit 2106
`Apple v. PMC
`IPR2016-00753
`Page 4
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`

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`U.S. Patent
`
`Jan. 10, 1978
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`PMC Exhibit 2106
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`Apple v. PMC
`|PR2016-00753
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`PMC Exhibit 2106
`Apple v. PMC
`IPR2016-00753
`Page 5
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`

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`U.S. Patent
`
`Jan. 10, 1978
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`PMC Exhibit 2106
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`Apple v. PMC
`|PR2016-00753
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`Page 6
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`PMC Exhibit 2106
`Apple v. PMC
`IPR2016-00753
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`

`
`1
`
`4,068,264
`
`PAY TELEVISION SYSTEM UTILIZING BINARY
`CODING
`
`BACKGROUND OF THE INVENTION
`
`The present invention resides in a pay television sys-
`tem, and more specifically in the type of pay television
`system disclosed in U.S. Pat. No. 3,924,059 (Horowitz).
`In this patent a pay television system is disclosed
`wherein, in addition to other features, the video signal
`information is inverted relative to the synchronizing
`portions of the signal prior to transmission during ran-
`domly selected frames. Whether or not the signal is so
`inverted is determined by the output of a bistable cir-
`cuit, referred to as a “polarity flip-flop”. If the polarity
`flip-flop is in a SET state, the video signal portion of the
`composite television signal is inverted, while if it is in a
`RESET state, no inversion takes place prior to trans-
`mission. In order that this inversion, if present, may be
`compensated for at the receiver, a code signal or burst
`is added to the mixer at predetermined time instants
`during the vertical blanking interval, again prior to
`transmission. At the receiver the code burst sets set a
`polarity flip-flop to the state corresponding to the state
`of the polarity flip-flop at the transmitter, thereby caus-
`ing reinversion of the video portion of the received
`signal when required.
`In a copending application, U.S. application Ser. No.
`552,787, filed Feb. 25, 1975, entitled “Coding System
`for Pay Television Apparatus”, a coding system is dis-
`closed wherein code bursts, that is oscillations of differ-
`ent frequencies, rather than just a single code burst, are
`applied to the television signal within predetermined
`horizontal line intervals in the vertical blanking inter-
`val. In a preferred embodiment disclosed in said appli-
`cation, six code bursts are utilized. A control panel is
`furnished which allows assignment of any of these code
`bursts to either an “A” mode, a “B” mode, a “C” mode
`or a “D" mode. Any code burst assigned to the (A)
`mode causes the polarity flip-flop to be reset. Any code
`burst assigned to the “B” causes the polarity flip-flop to
`be set, while “D” code burst causes a toggling of the
`polarity flip-flop, that is the polarity flip-flop fade is
`changed. Code bursts assigned to the “C” mode do not
`affect the polarity flip-flop at all but are used simply to
`confuse possible “pirates”, that is people wishing to
`break the code in order to avoid payment of fees. These
`code bursts are inserted into the composite television
`signal during predetermined lines of vertical blanking
`interval. At the receiver the code bursts are detected
`and used to control a polarity flip-flop which in turn
`controls the reinversion of the portions of the television
`signal which were inverted at the transmitter. In the
`above-identified Loshin application at the transmitter
`the assignment of each of the tone bursts (eight different
`tone frequencies are used) to the “A”, “B”, “C” or “D"
`mode is carried out by logic circuits which include
`externally operable switches. At the decoder the tone
`bursts are filtered out and the corresponding logic cir-
`cuits are set up in accordance with a punch card having
`a program corresponding to the code assignment at the
`transmitter.
`
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`The disadvantages of the above-described Loshin
`system are that the operation of the whole system de-
`pends upon the accuracy of the frequencies of the indi-
`vidual tones. But differences in path length can cause
`distortions in the received frequency, as can interfering
`elements such as, for example, airplanes. At the re-
`
`65
`
`2
`ceiver, there is some problem with the selectivity of the
`vtuned circuits, which must be high enough to reject »
`extraneous noise signals and at the same time suffi-
`ciently broad to include the above-mentioned possible
`distortions. Further, the cost of the system is relatively)
`high.
`A further disadvantage of the known system is that
`the subscriber must insert the program card carrying
`the code assignments.
`
`SUMMARY OF THE INVENTION
`
`It is an object of the present invention to furnish a
`binary-type coding system to replace the tone bursts of
`the known system.
`It is a further object of the present invention to fur-
`nish a coded television system wherein only minimal
`cooperation by the subscriber is required for setting up
`the program assignment code.
`The present invention is a subscriber television sys-
`tem which comprises, at the sending end, code number
`signal furnishing means for furnishing sets of code num-
`ber signals each signifying a corresponding number. It
`further comprises program identification signal furnish-
`ing means for furnishing sets of binary program identifi-
`cation signals each signifying a program identification
`number. Means are also provided at the sending end for
`inserting said binary code number signals and said pro-
`gram assignment signals into said television signal at
`predetermined time instants thereof. Encoder means are
`furnished at the sending end for encoding said television
`signal at least in part under control of said sets of binary
`code number signals. Means are furnished for sending
`the so-encoded television signal to the receiving end. At
`the receiving end, demodulating means are furnished
`for generating said sets of code number signals and said
`sets of program identification signals in response_to the
`received encoded television signal. Further, decoding
`means are furnished which operate under control of
`said binary program identification signals and are re-
`sponsive to said binary code number signals for decod-
`ing said encoded television signal, thereby furnishing a
`decoded television signal.
`The novel features which are considered as charac-
`teristic for the invention are set forth in particular in the
`appended claims. The invention itself, however, both as
`to its construction and its method of operation, together
`with additional objects and advantages thereof, will be
`best understood from the following description of spe-
`cific embodiments when read in connection with the
`
`'
`accompanying drawings.
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 illustrates waveforms used in the present in-
`vention;
`FIG. 2 is a block diagram of circuits at the sending
`end;
`FIG. 3 is a block diagram showing the circuits at the
`receiving end, for detecting code number signals, and
`the logic circuits controlled thereby;
`FIG. 4 shows the program assignment logic circuit
`block of FIG. 3 in greater detail;
`FIG. 4a is a more detailed schematic diagram of the
`individual program assignment circuits of FIG. 4;
`FIG. 5 illustrates a number of hexadecimal program
`identification numbers;
`FIG. 6 is a schematic block diagram of the decoder
`circuitry at the receiving end; and
`
`PMC Exhibit 210
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`Apple v". PMC
`|PR2016-00753
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`

`
`3
`
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`
`4,068,264
`
`A preferred embodiment of the present invention will
`now be described with reference to the drawing. How-
`ever, it should be noted that where timing signals are
`required for the present invention which were required
`for either the above-identified patent or the above-iden-
`tified copending application,
`the derivation of these
`timing signals will not again be discussed in detail. Each
`timing signal will be identified and its time duration
`clearly stated.
`In accordance with the present invention, the tones
`which are inserted into specified horizontal line inter-
`vals during the vertical retrace interval in the known
`system are replaced by a binary coded decimal number.
`More specifically, a single binary coded digit is trans-
`mitted serially on each line. There are six lines during
`the vertical
`interval
`together containing six binary
`coded decimal digits.
`The format of each of the horizontal line intervals
`during the vertical blanking interval which is to carry
`one of the binary coded decimal code digits is as fol-
`lows: The period of the line which is free of synchroni-
`zation and blanking signals, that is that portion of the
`horizontal
`line interval which occurs following the
`trailing edge of the last previous horizontal blanking
`signal and before the leading edge of the next subse-
`quent horizontal blanking signal,
`is divided into four
`parts, indicated as slot 1, slot 2, slot 3 and slot 4 in FIG.
`1. The pulse shown as the l H enable pulse shown in
`FIG. 1, defines the portion of the horizontal line inter-
`val described above. Also shown in FIG. 1 is an oscilla-
`tor output signal which, it will be noted, has a frequency
`somewhat higher than four times the horizontal line
`frequency. The oscillator output signal is so synchro-
`nized with the l H enable pulse that the trailing edge of
`each of its output pulses falls substantially in the center
`of the corresponding slot. The oscillator output signal is
`used as a timing signal to sample each of the four slots
`at the correct time both for insertion of the binary bit
`and for decoding purposes at the receiver. This oscilla-
`tor output signal is herein referred to as a 4 H oscillator
`output signal and the oscillator furnishing it as the 4 H
`oscillator.
`
`Thus at the encoder at the transmitting end, during
`each vertical retrace interval or, alternatively, during
`selected vertical retrace intervals, code information is
`transmitted during six lines which,
`in the preferred
`embodiment, are six consecutive lines. The so-transmit-
`ted numbers are herein referred to as code numbers. It
`is further required that a validation code (see also the
`copending application Ser. No. 553,436, filed Feb. 24,
`1975 (Nieson), assigned to the same assignee) be re-
`peated once per second over a six field period. The
`validation code is a fixed set of numbers which will be
`discussed in greater detail below. Further it is required
`that once per second on the half second, the program
`identification number, whose function is discussed in
`great detail in connection with the decoder circuitry at
`the receiver, be transmitted. This program identifica-
`tion number is a two-digit number. Its transmission is
`signalled by an identification flag which, in a preferred
`embodiment of the present invention, is the number 9.
`Following the program identification number is a one-
`digit number designating the selected catagory. This
`too will be discussed in greater detail below. At present,
`only the circuits for inserting the required information
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`into the transmitted signal will be discussed with refer-
`ence to FIG. 2. The circuitry for inserting the random
`numbers into the coded television signal
`includes a
`random number generator which comprises an oscilla-
`tor 201 whose output frequency is high with respect to
`the horizontal drive frequency. The output of oscillator
`201 is applied to a three-stage counter 202 comprising
`flip-flops FF1, FF2 and FF3. The output of flip-flop
`FF3 is connected through a differentiating circuit to the
`PRESET input of a further flip-flop FF4. The PRE-
`SET input of flip-flop FF4 is set by the negative going
`edge of the Q output of flip-flop FF3. The data input of
`flip-flop FF4 is grounded. The Q outputs of the four
`flip-flops are connected to the data input of a parallel-
`in/serial-out register 203. The load control input for
`register 203 is supplied with horizontal drive pulses.
`The clock input controlling the serial output of register
`203 is controlled by the output of the 4 H oscillator
`described above. This is designated by reference nu-
`meral 204 in FIG. 2. 4 H oscillator 204 is enabled by the
`output of a six line counter 206 which counts horizontal
`drive pulses following each vertical drive pulse up to
`the count of 6. The horizontal drive pulses applied to six
`line counter 206 are also applied to a four line counter
`207 which serves to count the first four lines in the
`vertical retrace interval. The vertical drive pulses are
`also applied to a frequency divider 208 which furnishes
`a pulse toggling a flip-flop FF5 once every half second.
`The Q output of flip-flop FF5 is applied to a gate 209
`through a monostable multivibrator 208a. Gate 209 has
`two further inputs receiving, respectively, the 4 H oscil-
`lator output signal and the output signal of counter 207.
`A first output of gate 209 is applied to the first inhibit
`input of gate 205, while the second output of gate 209 is
`applied as an input to a parallel-in, serial-out register
`210. Register 210 is a 96-bit register which receives its
`input from a validation code input 211.
`The Q output of flip-flop FF5 constitutes, after pass-
`ing through a monostable multivibrator 208b, one input
`of a gate 212 whose second input receives the 4 H oscil-
`lator output signal and whose third input is connected
`to the output of counter 207. One output of gate 212 is
`connected to the second inhibit input of gate 205, while
`the other output is connected to the input of a parallel-
`in, serial-out register 213. The inputs of register 213 are
`connected to receive the identification flag number 9,
`the two program assignment code digits and the catalog
`selector digit. The outputs of gate 205, register 210 and
`register 213 are each connected to an input of an OR-
`gate 214. The output of OR-gate 214 is mixed with the
`coded television signal prior to transmission.
`The above-described equipment operates as follows:
`The output pulses of oscillator 201 are counted in
`standard fashion by counter 202. Each time the most
`significant bit, namely the Q output of flip-flop FF3
`goes to zero, flip-flop FF4 furnishes a “l” output at its
`Q output. Since flip-flop FF3 goes to zero only on the
`count of 000, flip-flop FF4 will furnish a “1” output only
`on this count. On the following clock pulse the Q output
`of flip-flop FF4 will again be low. Thus if the outputs of
`all four flip-flops are examined, it will be noted that the
`count will range from 1000 to 0001 without going to 000
`or to any number exceeding 1000. With flip-flop FF4
`constituting the most significant bit, the count on the
`four flip-flops will thus range from 1 to 8. This four-bit
`code is continually present at the input of register 203.
`Register 203 is loaded by the horizontal drive pulses.
`Since the oscillator 201 is not synchronized to horizon-
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`4,068,264
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`5
`tal drive, a random number is loaded into register 203
`each time a horizontal drive pulse appears. The so-
`entered number is then read out serially under control
`of the 4 H oscillator 204. Since oscillator 204 is enabled
`only by the output of the six line counter 206, the signal
`at the output of register 203 will appear only during the
`first six lines of the vertical retrace interval and will,
`during these time intervals, contain a randomly selected
`number from the set of numbers 1-8. The signal at the
`output of gate 205 will be identical to the signal at the
`output of register 203, except when inhibit pulses are
`present at either of the two inhibit inputs of this gate.
`The first inhibit pulse is applied to gate 1 when the
`validation code is to be transmitted. This takes place for
`six consecutive fields once for every second. Specifi-
`cally.
`the vertical drive signals are applied to a fre-
`quency divider 208 which thus furnishes an output sig-
`nal approximately two times each second. The output of
`frequency divider 208 toggles a flip-flop FF5. The Q
`output of flip-flop FF5, through a monostable multivi-
`brator 2080 is applied to the input of gate 209. The time
`constant of monstable multivibrator 208a is such that
`gate 209 is enabled for six consecutive fields after flip-
`flop FF5 switches to the Q output. The Q output of
`flip-flop FF5 is applied through a monostable multivi-
`brator 208b to an enabling input of gate 212. The time
`constant of monostable multivibrator 208b is such that
`gate 212 is enabled for one vertical blanking interval
`following the switching of flip-flop FF5 to the Q out-
`put. The output of four line counter 207 is applied to the
`inputs of both gates 209 and 212, as is the output of the
`4 H oscillator 204. During the six vertical blanking
`intervals during which gate 209 is enabled, the valida-
`tion code is clocked out serially from register 210 and
`applied to an input of OR-gate 214. After each com-
`pleted output from register 210, the register is reloaded
`automatically from validation code input 211, so that
`the correct validation code is present for the next read-
`out.
`
`Similarly, when gate 212 is enabled for one vertical
`blanking interval following the switching of flip-flop
`FF5 to the Q output, the contents of register 213 are
`read out serially and applied to the third input of OR-
`gate 214. When gate 212 is enabled, gate 205 is disabled,
`so that OR-gate 214 receives an input from register 213
`only. Again, register 213 is automatically reloaded fol-
`lowing each read out.
`It is thus seen that the output of OR-gate 214 will
`comprise first of all random numbers in the first six lines
`of each vertical blanking interval. Secondly, once every
`second on the second a validation code will be sent out.
`During this time the transmission of the random num-
`bers is inhibited. Thirdly, every second on the half sec-
`ond a program identification number acccompanied by
`the necessary identification flag and a catagory selector
`number will be sent out. The transmission of random
`numbers is also inhibited during this time period.
`At the decoder, it is now required that these numbers
`be detected. The circuitry for detecting these numbers
`is shown in FIG. 3. The encoded television signal in-
`cluding the code numbers in the first six lines of the
`vertical retrace interval are received at terminal 300.
`The signal is applied to a level detector 301 which must
`be capable of detecting the “1” and “O” signals reliably
`independent of large changes in overall signal ampli-
`tudes. Detector 301 includes,
`in the main, a-Schmitt
`trigger for which the 50% grey level is used as refer-
`ence. Any signal larger than the 50% grey level to
`
`6
`which the television signal is clamped will be inter-
`preted as a “l” signal, while signals smaller than the
`50% grey level signals will be “0” signals at the output
`of the detector 301. Further, an integrator circuit can be
`used at the input of the Schmitt trigger circuit to im-
`prove the signal-to-noise ratio. The output of detector
`301 will thus constitute a pulse series of “1” and “O”
`signals. The signals are applied to the input of the series-
`parallel shift register 302. Shift register 302, however,
`does not accept pulses at all times, but only when en-
`abled by the output of an oscillator 303. Oscillator 303
`furnishes the oscillator output signal shown in FIG. 1.
`Specifically,
`the clock input of shift register 302 is
`strobed by the trailing edge of each pulse furnished by
`oscillator 303. Oscillator 303 is enabled only by the 1 H
`enable signals described above. Specifically, oscillator
`303 is synchronized by the leading edge of the l H
`enable signal. The synchronizing signal is derived from
`the 1 H enable signal by passing it through a differenti-
`ator circuit including a capacitor 304, a resistor 305 and
`a diode 306 which shunts the differentiated signal gener-
`ated by the trailing edge of the 1 H enable signal to
`ground potential.
`The four bits constituting the binary coded decimal
`number in each of the lines is thus clocked into shift
`register 302 under control of clock pulses from oscilla-
`tor 303. When the four bits of a particular line have been
`transferred into shift register 302, that is at the time of
`the trailing edge of the 1 H enable pulse, the contents of
`the shift register are transferred to the four bit latch 307.
`The code transfer pulse which causes the transfer from
`the shift register to the four bit latch is derived from the
`1 H enable pulse by a differentiating circuit including a
`capacitor 308, a resistor 309, and a diode 310. This dif-
`ferentiating circuit is identical to that previously de-
`scribed for the leading edge of the 1 H enable signal,
`except for the fact that diode 310 is connected with
`opposite polarity to diode 306. The resultant code num-
`ber transfer signal strobes four bit latch 307 to receive a
`number from shift register 302. The output of four bit
`latch 307 is connected to a decoder 311. Decoder 311
`converts the binary coded decimal code at its input to a
`straight decimal code at the output, that is one of output
`lines 0-8 is energized in response to each signal combi-
`nation at the input of the decoder.
`The signals on lines 0-8 are applied to the inputs of a
`program assignment logic circuit 312 whose outputs
`constitute the signals “A”, “B”, “C” and “D” which
`determine the mode of the polarity flip-flop at the de-
`coder. (Actually the signal on line C could be omitted
`since the polarity flip-flop is not affected by “C” sig-
`nals.)
`FIG. 4 shows the program assignment logic circuit
`block 312 of FIG. 3 in greater detail. Lines numbered
`1-8 shown in FIG. 4 are the output lines of the decoder
`311 of FIG. 3. The lines labelled PA1, PA2, .
`.
`. PA15,
`PA16 are inputs derived from the program identifica-
`tion number as will be discussed in greater detail below.
`Essentially, each pair of program assignment numbers
`PA1, PA2; PA3, PA4; etc. controls the transmission of
`one of the program numbers 1-8 furnished by decoder
`311 through a corresponding one of the individual as-
`signment circuits 401-408 to one of the outputs A, B or
`D. Individual assignment circuit 401 is shown in greater
`detail in FIG. 4a. The remaining individual assignment
`circuits are identical to circuit 401 with the exception
`that of course the inputs are as specified in FIG. 4.
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`PMC Exhibit 210
`
`Apple v. PMC
`|PR2016-00753
`
`Page 9
`
`PMC Exhibit 2106
`Apple v. PMC
`IPR2016-00753
`Page 9
`
`

`
`4,068,264
`
`5
`
`15
`
`20
`
`25
`
`30
`
`35
`
`7
`Referring now to FIG. 4a, Line PA1 is directly con-
`nected to the first inputs of two AND-gates 412 and 413
`and is connected through an inverter 410 to the input of
`further AND-gate 414. Similarly, line PA2 is directly
`connected to the input of AND-gates 412 and 414 and,
`through an inverter 411, to the input of AND-gate 414.
`The outputs of AND-gates 412, 413 and 414 are respec-
`tively connected to the first inputs of AND-gates 415,
`416 and 417. The second inputs of AND-gates 414—417
`are connected in common to output line 1 of decoder 10
`311. Thus it is seen that in the absence of a signal on line
`PA1 and the presence of a signal on line PA2, AND-
`gate 414 is conductive, while AND-gates 412 and 413
`are blocked. Upon receipt of code number 1, AND-gate
`417 will therefore furnish an output which energizes the
`A output. Similarly, the presence of a signal on line PA1
`and the absence of a signal on line PA2 will result in a
`B output upon receipt of code number 1, while the
`presence of signals on both lines PA] and PA2 will
`result in a D output upon receipt of code number 1 from
`the decoder 311. It is thus seen that the assignment of
`the signal from decoder 311 to A, B or D outputs takes
`place under control of the program assignment inputs,
`which in turn are derived from the program identifica-
`tion numbers as will be discussed below.
`As previously stated, during the vertical retrace in-
`terval code information is transmitted during six con-
`secutive lines. Each line contains, at random, one of the
`eight decimal numbers 1 through 8. These numbers are
`herein referred to as code numbers. Approximately
`once per second, the first lines of the six line sequence
`are used to transmit a program identification number in
`the following manner. The first line is a “9”, which
`serves as an identification flag. The two following lines
`contain two digits of a hexadecimal number. Each digit
`runs from O to F, where the letters A to F are used to
`symbolize numbers 10-15. The fourth line contains a
`hexadecimal number used for category selection which
`will be discussed below. The program identification
`number is used for two purposes. The first is to select
`one out of a group of assignment codes stored within
`the decoder, that is, to select one set of values for lines
`PA1—PA16 of FIG. 4. The second function is to store
`the eight bits confirming that number in a memory
`when the subscriber decides to accept the program.
`This is then used as the base for billing information and
`will not be discussed further herein.
`As reference to FIG. 4 shows, each assignment code
`is a 16 bit word, the bits being taken in pairs (PAI, PA2;
`.
`.
`. PA15, PA16). The sixteen bit word is extracted as a
`byte from a 48 bit string stored in a random access
`memory in the decoder. The first byte includes bits
`1-16. The second byte is obtained by shifting one place
`to the right (to start at bit 2). Thirty-two such bytes are
`possible from a forty-eight bit string. Since every bit in
`each code is shifted by one place, adjacent codes are
`quite different from one another even though there is
`only one new bit in each code. It is of course the func-
`tion of the program identification number, namely the
`two digit hexadecimal number, to select one of these
`thirty-two assignment codes (bytes). Since 256 different
`program identification numbers can be formed from the
`combinations O0 to FF of two hexadecimal digits, eight
`program identification numbers are allocated to each
`program assignment code (32 X 8 : 256). When a
`program identification number from O0 to 07 is re-
`ceived, program assignment code I is selected. A num-
`
`45
`
`50
`
`55
`
`60
`
`65
`
`8
`ber from 08 to 15 cause the selection of program assign-
`ment code 2, etc.
`The logic implementation of this selection process
`will best be understood with reference to FIG. 5. FIG.
`5 is a table wherein the first column is headed “Line 3”
`while the second column is headed “Line 2”. The four
`hits transmitted above as described in line 2 represent
`units, while the four bits transmitted in line 3 represent
`16’s. The hexadecimal number 07 will thus be repre-
`sented by four zero bits in line 3 and the sequence 01 ll
`in line 2. The hexadecimal number 08 will be repre-
`sented by four zero bits in line 3 and the sequence 1000
`in line 2. Hexadecimal number 15 (of which the decimal
`equivalent is 21) will be represented by the sequence
`0001 in line 3 and the sequence 0101 in line 2. It will be
`noted that the three least significant bits, namely the
`three rightmost bits in line 2 together form numbers
`from 0 to 7. Therefore, since eight program numbers are
`allocated to each program assignment code, only the
`five most significant bits, that is all bits on line 3 and the
`most significant bit on line 2 will be examined in order
`to select a program assignment code.
`The fourth line of the six lines which normally carry
`the randomly selected numbers contains a hexadecimal
`number from 0 to F which is used to category selec-
`tion. Category selection is an optional feature, but the
`type of coding used in the present invention is particu-
`larly suitable for implementing a category selection
`capability. The bits in line 4 are treated independently.
`There are three types of programs and three categories
`in two of these types.
`
`Type
`
`(a) Home
`
`(b) Special
`
`(c) Tavern
`
`General
`Parental Guidance
`Restricted
`Doctors
`Lawyers
`Educational
`
`The selection of programs on the decoder is as fol-
`lows: A selector switch is mounted on the front panel.
`When the switch is set at “General”, only programs
`meant for general audiences can be decoded. When set
`at
`the “Parental Guidance” position, both “Parental
`Guidance” and “General” programs will be decoded.
`When set to “Restricted”, all three types of programs
`can be received. When the switch is set to receive “Spe-
`cial” programs, hard wired jumpers within the decoder
`determine which type of program may be watched. For
`instance, if the decoder is wired up for a “Doctors”
`special and an “Educational" program is being transmit-
`ted, the decoder will not unscramble even though the
`switch is in the special position.
`It
`is also possible to inhibit Tavern decoder from
`unscrambling while other audiences are allowed to
`watch the program.
`The implementation of the above-described logic
`operations will now be described with reference to
`FIG. 6.
`Shown in FIG. 6