v--"*
`
`’
`
`'.‘."}_‘1,\Yf?.-ZC..:E OF CONTENTS
`
`1.0
`
`Introduction
`
`2.0 The NABU Network
`
`_
`
`3.0
`
`The'NABU personal computer
`
`3.1 Memory Organization
`
`3.2 The TMS9918A Videcz Display Proces3s.r>r
`3.2.1 Registers
`3.2.2 Text Mode
`3.2.3 Graphic 1 Mode
`3.2.4 Graphic 2 Mode
`3.2.5 Multicolour Mode
`3.2.6 Sprites
`3.2.7 VRAM table adéresses
`3.2.8 Graphics one Example
`
`page
`
`1—l
`
`"1--6
`
`V3’51-9
`
`I
`
`1»9
`
`‘V“.1:."-»_]..0
`' *1vl3
`;l~15
`' “Eels
`'
`leis
`.~1#18
`1419
`_lv22
`1»23
`
`3.3 The AY-3-8910 Programmable Sound Generator
`
`1~25
`
`4.0
`
`Internal Operating Software
`
`4.1 Conventions Used by the IOS
`4.1.1 Stack Operation and Requirements
`
`4.2 Introduction to DOS
`4.2.1 Segment Handling Routines
`:
`4.2.1.1 Introduction
`4.2.1.2 Segment Control and Status Block
`4.2.1.3 DOS Interface
`'
`.
`4.2.1.4 Segment Headers
`4.2.1.5 Examples
`
`1.
`
`Hm
`
`H
`
`4.2.2 Directory Routines
`4.2.2.1 Introduction
`
`4.2.2.2 Format of Directory
`4.2.2.3 Accessing the Directory
`
`251
`
`2:2
`2-4
`
`'2e9
`’2~10
`2-10
`2—lO
`2-13
`2716
`2-19
`
`2423"
`2-‘~23
`
`2-23
`2~25
`
`Spec. 50-90020490
`
`Page iii
`
`June 3. 1984
`
`PMC Exhibit 2077
`
`Apple v. PMC
`|PR2016-00753
`
`Page 1
`
`PMC Exhibit 2077
`Apple v. PMC
`IPR2016-00753
`Page 1
`
`

`
`4.2.3 Interrupt structure and Tasking Support
`4.2.3.1 Introduction
`4.2.3.2 Critical Regions
`4.2.3.3 User Task Attachment Routines
`4.2.3.3.1 Attachin~! Tasks to the Clock
`4.2.3.3.2 Keyboard User Tasks
`4.2.3.3.3 Expansion Slots
`
`4.2.4 Human Input Devices
`4.2.4.1 Introduction
`4.2.4.2 Special Key Operation
`4.2.4.3 Obtaining Data From the Keyboard
`4.2.4.4 Sym Table Operation
`
`4.2.5 Video Screen Device Driver
`
`4.2.6 Printer Output
`
`4.2.7 I/O router
`4.2.7.1 Physical Device Identification
`4.2.7.2 Logical Device Identification
`4.2.7.3 I/O Routing Entry Point
`
`4.3 Basic Operating Software
`
`5.0 Extended lOS (XIOS)
`
`5.1 Introduction
`
`5.2 Extended lOS Module Handler
`5.2.1 Memory Structure
`for Loaded XIOS Modules
`5.2.2 Loading XIOS Modules
`5.2.3 Unloading XI OS Modules
`5.2.4 Resolving References in XIOS Modules
`
`5.3 Disk System
`
`5.3.1 Introduction
`
`5.4 Multi-Window Screen Driver
`
`5.4.1 Introduction
`5.4.2 Operational Requirements
`5.4.3 Module Specific Error Codes
`5.4.4 Module Initialization
`5.4.5 Module De-Initiali:~ation
`5.4.6 DOS Call Interface
`5.4.7 BOS Call Interface
`
`2-31
`2-31
`2-32
`2-34
`2-34
`2-39
`2-41
`
`2-43
`2-43
`2-43
`2-45
`2-47
`
`2-49
`
`2-51
`
`2-52
`2-52
`2-53
`2-53
`
`3-1
`
`4-1
`
`4-1
`
`4-1
`
`4-2
`4-3
`4-5
`4-6
`
`5-1
`
`5-1
`
`6-1
`
`6-1
`6-1
`6-1
`6-1
`6-2
`6-2
`6-7
`
`Spec. 50-90020490
`
`Page j v
`
`June 8, 1984
`
`••••
`
`PMC Exhibit 2077
`Apple v. PMC
`IPR2016-00753
`Page 2
`
`

`
`•
`
`•
`
`5.5 80 Column Screen Driver
`
`5.5.1 Introduction
`5.5.2 Operational Requirements
`5.5.3 Module Specific Error Codes
`5.5.4 Module Initialization
`5.5.5 Module De-Initialization
`5.5.6 DOS Call Interface
`5.5.6.1 Input Status
`from Video Screen Window
`5.5.6.2 Output Data to Video Screen Window
`
`5.6 CP/M Compatible Logical Device Drivers
`
`5.6.1 Introduction
`5.6.2 Operational Requirements
`5.6.3 Module Specific Error Codes
`5.6.4 Module Initialization
`5.6.5 Module De-Initialization
`5.6.6 DOS Call Interface
`
`APPENDIX A
`A.O GLOSSARY
`
`7-1
`
`7-1
`7-1
`7-1
`7-1
`7-2
`7-2
`
`7-2
`7-3
`
`8-1
`
`8-1
`8-1
`8-1
`8-1
`8-1
`8-2
`
`9-1
`
`APPENDIX B
`B.O
`DOS and BOS number - Function Cross Reference 9-3
`
`APPENDIX C
`C.O
`Sample Program and Documentation
`
`9-6
`
`Spec. 50-90020490
`
`Page v
`
`June 8, 1984
`
`PMC Exhibit 2077
`Apple v. PMC
`IPR2016-00753
`Page 3
`
`

`
`•
`
`•
`
`THIS PAGE LEFT INTENTIONALLY BLANK
`
`Spec. 50-90020490
`
`Page vi
`
`June 8, 1984
`
`PMC Exhibit 2077
`Apple v. PMC
`IPR2016-00753
`Page 4
`
`

`
`INTRODUCTION
`
`1.0 INTRODUCTION
`
`This document is intended to provide the application programmer
`the
`necessary
`information and
`reference material
`to write
`application programs for the NABU personal computer. Complete
`programm~ng information on the internal operating software (IDS)
`as well as programming information of the Video display processor
`and the programmable sound generator are included.
`
`One of the aims of this manual was to collect all the information
`that was previously found in several documents into
`just one.
`Although
`this has yielded a document of some 200 pages,
`each
`section discusses
`a single concept related to
`the programming
`environment
`at NABU.
`Therefore
`the programmer need
`only
`investigate
`the portions of interest and not have to
`read
`the
`entire manual.
`
`a
`to put the IDS into perspective, we include here
`In order
`from
`the
`IDS Specification which spells out
`the
`section
`general functional requirements of IDS. This will enable you
`to
`judge what
`to expect
`from
`the
`Internal Operating System.
`
`•
`
`DESIGN REQUIREMENTS
`
`Overview
`
`Internal Operating
`This design specification defines the
`Software (IDS) for the NABU Personal Computer (NPC),
`a
`low(cid:173)
`cost, expandable personal computer.
`It is unique because it
`is capable of communicating on one-way, hybrid and
`two-way
`cable systems and telephone networks, as well as operating in
`a stand-alone mode, depending on which options are selected.
`When used in association with a CATV network the NABU P.C.'s
`prime
`function is to run software downline loaded
`from
`the
`cable head-end.
`
`system and device
`A versatile set of internal operating
`handling software is required for the NABU P.C. to run appli(cid:173)
`cations software under control of a user. For definition and
`development purposes this software, collectively referred to
`as the Internal Operating Software (IDS) consists of:
`
`o Applications program interfaces to IDS facilities
`o All physical device control and liD handlers
`o Basic task controlling and interrupt handling software
`o Communications Software
`
`•
`
`Spec. 50-90020490
`
`Page 1 - 1
`
`June 8, 1984
`
`PMC Exhibit 2077
`Apple v. PMC
`IPR2016-00753
`Page 5
`
`

`
`INTRODUCTION
`
`The internal operating software does NOT include:
`
`o Human Interface for Selection of Applications Programs
`o Any ROM Software in the NPC
`o Programming
`languages
`(eg. BASIC is not part of
`operating system.)
`o Monitors (ie. examine and change memory, etc., etc. ,etc)
`o High-level (user oriented) utilities
`
`the
`
`Operating Environment
`
`IOS must interact with four other functional components
`The
`of the NABU P.C •. These are:
`
`o The Basic NABU P.C. hardware
`o Optional hardware and peripheral devices
`o Communications with external systems,
`including the keyboard and NABU Adaptor (NA)
`o Applications Software
`
`these components
`requirements and functions of
`the
`is
`It
`which essentially define the requirements for the IOS.
`
`Internal Operating Software Requirements
`
`Internal Operating
`the
`requirement of
`fundamental
`The
`Software
`is
`to create an environment which
`supports
`the
`loading and execution of applications programs in a
`simple,
`efficient manner. The NPC hardware, its peripherals, communi(cid:173)
`cations and the IOS are really just necessary evils
`required
`to present content to an NPC user. The IOS provides a stable
`interface which allows applications access to the other NPC
`components while hiding the messy details of
`the hardware
`configuration and communications protocols, which are really
`of no interest to applications programs.
`
`IOS Flexibility
`
`resides
`IOS
`the
`to be as flexible as possible,
`In order
`completely in RAM.
`A separate program,
`the MAIN MENU pro(cid:173)
`gram,
`is
`loaded in along with the IOS when the NABU P.C. is
`"booted".
`The MAIN MENU performs all human interface func(cid:173)
`tions required to load in an application.
`
`Spec. 50-90020490
`
`Page 1 - 2
`
`June 8, 1984
`
`•
`
`•
`
`PMC Exhibit 2077
`Apple v. PMC
`IPR2016-00753
`Page 6
`
`

`
`INTRODUCTION
`
`•
`
`the NPC •
`A number of expansion options will be offered for
`These options may include:
`standalone operation through use
`of ROM readers andlor floppy disks, additional communications
`options though the use of telephone dialers,
`two-way
`cable
`moderns
`and other devices,
`and the support of various other
`peripherals via an 1/0 expansion bus.
`The lOS must be able
`to operate
`in a configuration
`independent manner.
`This
`implies:
`
`o The lOS must be able to sense the NPC configuration when
`"Booted"
`should protect the applications
`o The
`lOS
`"configuration-dependent"
`o Standard 1/0 handling procedures and 1/0 routing must be
`included in the lOS
`o The lOS may be required to operate using different
`of primary storage devices.
`
`from becoming
`
`types
`
`Applications Interfacing
`
`As was mentioned earlier the NPC and lOS exist to run appli(cid:173)
`cations.
`In
`this sense applications software is the highest
`level of software and it is in control of the lOS. Different
`applications have different
`requirements. Animated video
`games and other applications which require rich active human
`interfaces will require fast, efficient, unadorned access to
`NPC devices.
`At the other end of the scale are many of the
`computation type applications which are willing to sacrifice
`speed
`for 1/0 independence and ease of use. Other
`software
`such as a screen-oriented word processor lies between the two
`extremes of support.
`
`•
`
`This implies:
`
`over
`
`a
`
`o Applications must have as much control as possible
`the lOS
`o Applications should be able to access lOS features at
`number of different levels
`lOS
`support
`should be designed
`requirements and not vice versa
`
`o
`
`to fit applications
`
`Real Time Requirements
`
`the
`Unlike many other microcomputer operating environments,
`NPC will have time-critical tasks. The most obvious of these
`is communications on the CATV network. However many of
`the
`applications planned for the NPC have real-time components •
`
`•
`
`Spec. 50-90020490
`
`Page 1 - 3
`
`June 8, 1984
`
`PMC Exhibit 2077
`Apple v. PMC
`IPR2016-00753
`Page 7
`
`

`
`INTRODUCTION
`
`This implies:
`
`layers of the lOS must be as time-efficient as
`
`o The lower
`possible
`Interrupts must be well supported in the lOS
`o
`o Applications software has as much control as possible over
`the enabling of interrupts and the complexity of
`interrupt
`handling
`o Some simple tasking constructs should be provided
`o Attachment
`of applications supplied code
`to
`interrupt
`handlers should be supported where possible
`o Real-time counters
`(60Hz rate) should be supported by the
`lOS
`
`Application Time-out Requirement
`
`screen being used for the basic output dev(cid:173)
`Due to the T.V.
`ice,
`if no keyboard input is received for long periods of
`time (approx.
`20 to 30 minutes),
`the T.V. screen will
`go
`blank (to prevent burning of the TV screen).
`This assumes
`that
`the clock interrupt is running,
`inorder to do the tim(cid:173)
`ing.
`The program execution must continue even though no(cid:173)
`thing
`is being displayed. When any key on the keyboard
`is
`activated,
`the T.V.
`screen will
`return back to its normal
`display. The keystroke which re-activates the screen is not
`passed on to the application program.
`{This time-out will
`also be active if the NPC is in the ·PAUSED" mode.} ~he eftxy
`exee~~±eft ~e ~±me-e~~ req~±remeft~ ±e ~he eaee where ~he
`H.P.€.
`±e
`ift a Ahax~A me~e beea~ee ~he p~aSE key hae be eft
`ae~±va~e~. ~he p~aSE f~fte~±eft eaHses ~he ~es ~e exee~~e ±ft a
`very ~±gh~ xee~T Hft~±X p~aSE f~fte~±eft ±e ~eae~±va~ed.
`~h±e
`~±gh~ xee~ eeafte ~he key beard fer ~he ae~±va~±eft ef ~he
`p~aSE7 ~~H~eT aftd S¥M keye.
`
`Size Requirements
`
`The total size of the lOS Kernel should not exceed 10K bytes
`and shall be kept to a minimum.
`In order to accommodate all
`the different lOS functions, the lOS will be divided into two
`sections. The first section will be called the Kernel. This
`will form a "bare bones" type lOS.
`The remainder of the lOS
`will form the second section which is called the Extended lOS
`(XIOS). As applications
`require functions which are only
`found
`in the XIOS,
`the application will be able to load
`in
`the necessary sections (modules) of the XIOS,
`and then use
`the
`functions. When the functions are no longer necessary,
`the XIOS module can be deleted, thus freeing up memory space.
`
`Spec. 50-90020490
`
`Page 1 - 4
`
`June 8, 1984
`
`•
`
`•
`
`•
`
`PMC Exhibit 2077
`Apple v. PMC
`IPR2016-00753
`Page 8
`
`

`
`•
`
`•
`
`INTRODUCTION
`
`Internal Operating Software Structure
`
`three
`into
`is divided
`Internal Operating Software
`The
`These components are: the
`functionally separate components.
`1/0 handlers,
`the Basic Operating Software (BOS),
`and
`the
`Downloadable Operating Software (DOS).
`
`1/0 Handlers
`
`These portions of the software contain the low-level control(cid:173)
`ling code to handle input and output devices. Each physical
`device has
`its own 1/0 handler. This
`software masks
`the
`detailed physical operation of peripheral devices so that the
`higher
`levels of
`the operating system may be peripheral
`device independent. 1/0 Handlers provide:
`
`o Hardware Dependent Device Control Code
`o Interrupt Handling
`o Initialization Code
`o Data Link Layer Communications Protocols
`
`Basic Operating Software (BOS)
`
`This level of the operating system provides the key operating
`control software for the NABU P.C ••
`It interfaces to the 1/0
`handlers,
`the Downloadable Operating Software and applica(cid:173)
`tions programs. The BOS provides:
`
`o Functional Level 1/0 handling
`o Calling of 1/0 handlers and device control code
`o Interrupt and task handling control
`o A Method of Linking Directly to each BOS Routine
`
`Downloadable Operating Software
`
`This is the highest
`It
`interfaces
`to
`provide:
`
`layer of the internal operating software.
`the BOS
`and applications programs
`to
`
`o Common Entry Points for Applications
`o 1/0 Routing
`o Configuration Identification
`
`•
`
`Spec. 50-90020490
`
`Page 1 - 5
`
`June 8, 1984
`
`PMC Exhibit 2077
`Apple v. PMC
`IPR2016-00753
`Page 9
`
`

`
`NABU NETWORK
`
`2.0 THE NABU NETWORK
`
`a
`linking
`idea of
`the
`formed on
`The NABU Network was
`these
`two
`The union of
`microcomputer
`to
`the cable network.
`the
`introduction of
`a
`technologies has paved
`the way
`for
`microcomputer
`complete with a large base of software
`into
`the
`homes of the population at large.
`
`This section will describe the various links in the chain of
`this Network with a view to giving a broad understanding of
`the
`pathway followed by an application program from the cable company
`to
`the end user's RAM.
`Refer to the diagram for
`a pictorial
`representation of this data flow.
`
`The Head End
`
`the
`in
`this is the originating node
`the name suggests,
`As
`Network.
`The Head End is actually a minicomputer and it is here
`that all the programs and data to be broadcast on the cable are
`found.
`The Head End minicomputer is constantly outputing
`the
`information
`in its database and it does so in a cyclic fashion -
`when all the information has been sent,
`the mini starts at
`the
`beginning and re-sends the database.
`This cyclic nature of the
`data
`flow enables one to envision the data as being written on
`the edge of a wheel which is read as it revolves.
`
`an
`tagged
`is
`"wheel"
`the
`on
`with
`application
`Each
`the
`This number becomes important
`identification number.
`at
`applica-
`other end of the NABU Network to select the proper user
`tion.
`
`The Head End
`database.
`Any
`with in order to
`as these changes
`
`this
`is also responsible for the maintenance of
`additions or deletions must be carefully dealt
`ensure the overall integrity of the
`information
`will alter the "diameter" of the "wheel".
`
`The RF Modulator
`
`information
`The
`digital in nature.
`data signal must
`this function.
`
`the Head End m~n~ is of course
`output by
`Before this can be put onto the cable,
`the
`be modulated.
`The RF modulator will perform
`
`Spec. 50-90020490
`
`Page 1 - 6
`
`June 8, 1984
`
`•
`
`•
`
`•
`
`PMC Exhibit 2077
`Apple v. PMC
`IPR2016-00753
`Page 10
`
`

`
`NABU NETWORK
`
`~ The Combiner
`radio),
`Since there are other services on the cable (eg. TV,
`there must be another piece of equipment that will merge the NABU
`programs with that information. The Combiner performs this task.
`The NABU information is now broadcast on a specific channel and
`sent into the cable for distribution.
`
`The Adaptor
`
`The Adaptor is a piece of hardware that acts as the interface
`between
`the cable coming into the home of the NABU user and
`the
`NABU Personal Computer.
`
`Essentially, the Adaptor performs the reverse functions of the
`Combiner and the RF Modulator.
`It is tuned to listen to the NABU
`channel, de-modulate the signal and convert it into the digital
`data that the NABU PC can understand.
`
`•
`
`On the cable side, the Adaptor is only capable of listening to
`the
`information coming down the cable - it cannot send
`commands
`back
`to the Head End.
`However,
`on the PC side of the Adaptor
`there is two-way communication. The PC can tell the Adaptor what
`it wishes from the cable and the Adaptor can inform the PC when
`that data is available to be read •
`
`Thus, when the user requests a particular application, the PC
`sends
`a Read
`command and the
`identification number of
`the
`application
`to the Adaptor. The Adaptor then "listens"
`to
`the
`cable until
`the appropriately identified data appears.
`The
`Adaptor fills its internal buffer and then informs the PC
`that
`the data
`is ready.
`The PC obtains the data from
`the Adaptor
`putting it into the appropriate location in the RAM of the PC •
`
`•
`
`----------------------------------------------------------------
`Spec. 50-90020490
`Page 1 - 7
`June 8, 1984
`
`PMC Exhibit 2077
`Apple v. PMC
`IPR2016-00753
`Page 11
`
`

`
`NABU NETWORK
`
`NABU
`HEAD END
`
`(software
`database)
`
`MODULATOR
`
`1
`1
`1
`_____ _ :-1
`\
`
`\
`
`\
`
`\
`
`\
`
`I
`\ ______ 1
`1
`1
`1
`1
`1
`I
`1 COMBINER
`1
`1
`1
`1
`1
`1
`1
`
`CAB L E
`
`CATV
`HEAD END
`
`(Television
`Radio etc.)
`
`I
`
`I
`
`I
`
`I
`
`I
`
`I
`
`I
`
`I
`
`I
`
`I
`
`I
`
`I
`
`I
`
`1
`ADAPTOR
`1
`1
`1
`1---------------1
`NABU
`1
`1
`PC
`1
`1
`1
`1
`
`- THE NABU NETWORK -
`
`Spec. 50-90020490
`
`Page 1 - 8
`
`June 8, 1984
`
`•
`
`•
`
`•
`
`PMC Exhibit 2077
`Apple v. PMC
`IPR2016-00753
`Page 12
`
`

`
`NABU PERSONAL COMPUTER
`
`•
`
`3.0 THE NABU PERSONAL COMPUTER
`
`INTRODUCTION
`
`the application programmer
`section will provide
`This
`necessary
`introduction and information to the hardware of
`NABU Personal Computer.
`
`the
`the
`
`3.1 MEMORY ORGANIZATION
`
`The NABU Personal Computer is a 80 Kbyte machine. The 80K is
`partitioned as follows:
`
`It is the only region
`1) The primary memory is 64K in size.
`where Z80 microprocessor code may be executed.
`
`2) A 16K block of memory is dedicated for use by the TMS
`9918A video display processor.
`
`•
`
`64K RAM
`
`I
`16k videol
`RAM
`I
`I
`
`Z80A
`
`ITMS 9918AI
`
`above
`The
`organization.
`
`figure graphically
`
`describes
`
`the memory
`
`•
`
`Spec. 50-90020490
`
`Page 1 - 9
`
`June 8, 1984
`
`PMC Exhibit 2077
`Apple v. PMC
`IPR2016-00753
`Page 13
`
`

`
`VIDEO DISPLAY PROCESSOR
`
`3.2 THE TMS 99l8A VIDEO DISPLAY PROCESSOR
`
`responsible
`The TMS 99l8A Video Display Processor (VDP) is
`for all video display for the NABU Personal Computer
`(NPC).
`It provides
`for text, graphics and animation. Detailed
`knowledge of
`the control of the VDP is not required since
`all functions of
`the VDP are accessed
`through
`routines
`provided
`in the Internal Operating System (IOS) of the NPC.
`This section will outline the features of the VDP
`and
`the
`use of IOS routines to generate T.V.
`images for display on
`the NPC. Further
`information may be found in
`the Texas
`Instruments 9900 Data Manual
`(TMS99l8A/TMS9928A/ TMS9929A
`Video Display Processors).
`
`image that can be envisioned as a
`The VDP produces a T.V.
`series of display planes. Each plane has a display priority.
`An
`image on a plane of higher priority will overwrite an
`overlapping
`image on a lower priority plane. The display
`planes
`in order of lowest to highest priority are BACKDROP,
`PATTERN,
`and SPRITE. Sprites are special animation objects.
`The VDP provides 32 sprite planes, with sprite plane 1
`having the highest priority.
`
`which consists
`The lowest priority plane is the BACKDROP,
`of a single colour.
`It can be set to anyone of 15 colours.
`The area covered by the backdrop plane is larger that
`the
`other planes,
`and can form a border for the pattern plane.
`With
`the T.V. displays commonly used with
`the NPC,
`the
`border effect is generally limited to the top and bottom of
`the screen, while the side borders are cropped by the T.V.
`overscan. The colour of the backdrop is determined by write-
`only register 7 of the VDP (see 3.2.1 REGISTERS).
`
`image displayed in the pattern plane is determined by
`The
`the contents of 16K of Video RAM
`(VRAM) provided
`for
`the
`VDP. The contents of the PATTERN NAME TABLE
`(Name Table),
`PATTERN GENERATOR TABLE (Pattern Table),
`and COLOUR TABLE
`allocated
`in VRAM define the pattern plane image. The mode
`of
`the VDP determines the size and organization of
`the
`tables and hence
`the way in which VRAM is mapped
`to
`the
`screen. The VDP can operate in anyone of four modes, Text,
`Graphics I, Graphics II, and Multicolour.
`
`The images displayed in the sprite planes are defined in the
`SPRITE ATTRIBUTE TABLE and SPRITE PATTERN GENERATOR TABLE.
`These
`tables are also allocated in VRAM,
`and perform
`the
`sprite equivalents of pattern plane tables.
`
`Spec. 50-90020490
`
`Page 1 - 10
`
`June 8, 1984
`
`•
`
`•
`
`•
`
`PMC Exhibit 2077
`Apple v. PMC
`IPR2016-00753
`Page 14
`
`

`
`VIDEO DISPLAY PROCESSOR
`
`resolution
`The VDP produces a screen image with an absolute
`of 256 X 192 pixels. The VDP divides the pattern plane into
`blocks of pixels called patterns. In Text mode, the patterns
`are 6 X 8 pixels, yielding 40 text pattern per
`line.
`In
`Graphics modes the patterns are 8 X 8 pixels
`(32 patterns
`per
`line). There is a one byte entry in the Name Table for
`each pattern position on
`the
`screen. For
`example,
`in
`Graphics modes,
`the Name Table
`is 768 bytes
`long
`(32
`patterns per row X 24 rows of patterns).
`In Text mode,
`the
`Name Table is 960 bytes long (40 X 24). There is a one-to(cid:173)
`one mapping of entries in the Name Table and screen pattern
`positions (see Figure 1 for example). The screen origin
`is
`defined as the top left corner.
`
`+---+---+ -
`I
`01
`11
`1---+---+ -
`I 321 331
`1---+---+
`
`-
`
`-
`
`-
`
`1---+---+ -
`170417051
`1---+---+ -
`173617371
`+---+---+ -
`
`-
`
`-
`
`-
`
`-
`
`-
`
`-
`
`-
`
`-
`
`-
`
`-
`
`- +---+---+
`I 301 311
`- +---+---1
`I 621 631
`- +---+---1
`
`- +---+---+
`173417351
`- +---+---1
`176617671
`- +---+---+
`
`Fig. 1. Graphics I Name Table Mapping
`The figure
`illustrates the pattern positions on a T.V
`screen with
`the VDP in Graphics I mode. The number
`associated with each position maps
`to
`the entry
`(offset) within
`the Name Table. The Oth entry
`in
`the Name Table maps to the pattern position occupying
`the top left corner of the screen.
`
`The Pattern Table determines which pixels will be turned on
`within a pattern. Each entry in the Pattern Table is eight
`bytes
`long. The first byte of an entry defines the pixel
`arrangement of the top row of a pattern, the second byte the
`second row and so on. A 'I' bit specifies a pixel that is on
`and a
`'0' bit specifies a pixel that is off. The offset of
`an entry
`into the Pattern Table (i.e.
`the entry number)
`forms the 'name' of the pattern. A pattern can be displayed
`on
`the screen in any pattern position by writing its name
`(offset)
`to
`the appropriate entry in the Name Table. The
`number of patterns available in the Pattern Table depends on
`the mode of the VDP.
`
`Spec. 50-90020490
`
`Page 1 - 11
`
`June 8, 1984
`
`•
`
`•
`
`•
`
`PMC Exhibit 2077
`Apple v. PMC
`IPR2016-00753
`Page 15
`
`

`
`VIDEO DISPLAY PROCESSOR
`
`is capable of producing fifteen colours plus
`The VDP
`transparent. The Colour Table determines the colours of the
`pixels defined in the Pattern Table. The high order nibble
`a byte in the Colour Table defines the colour of the 'I'
`of
`bits
`in the associated byte of the Pattern Table. The
`low
`'0' bits. The
`order nibble defines
`the colour of
`the
`resolution of the mapping from Colour Table to ~attern Table
`is dependent on the mode of the VDP. The colours associated
`with each 4 bit nibble are shown in Table 1.
`
`the
`The base addresses of the VRAM tables are derived from
`values contained in the VDP's write-only registers,
`and are
`subject
`to restrictions dependent on the mode of the VDP.
`The base addresses are defined by calling the specific
`IOS
`routine for that table, which will set the correct bits
`in
`the appropriate VDP register. This process does not require
`a knowledge of the register addressing scheme.
`
`HEX VALUE
`o
`1
`2
`3
`4
`5
`6
`7
`8
`9
`A
`B
`C
`D
`E
`F
`
`COLOUR
`
`Transparent
`Black
`Medium Green
`Light Green
`Dark Blue
`Light Blue
`Dark Red
`Cyan
`Medium Red
`Light Red
`Dark Yellow
`Light Yellow
`Dark Green
`Magenta
`Gray
`White
`
`Table 1. Colour Assignments
`The 4 bit hex values in the first column
`produce the colour in the second column
`
`Spec. 50-90020490
`
`Page 1 - 12
`
`June 8, 1984
`
`•
`
`•
`
`•
`
`PMC Exhibit 2077
`Apple v. PMC
`IPR2016-00753
`Page 16
`
`

`
`VIDEO DISPLAY PROCESSOR
`
`~ 3.2.1 REGISTERS
`a
`The VDP
`is equipped with eight write-only registers and
`single read-only status register. The write-only
`registers
`are used to define the mode of the VDP,
`table addresses in
`VRAM, and the backdrop colour. All access to these registers
`is by way of calls to routines in the IDS. Descriptions of
`these routines can be found in the section on BOS calls.
`
`routine
`The write-only registers may be loaded with the IOS
`VREGWR. Specialized
`routines are provided for
`specifying
`VRAM table addresses.
`In the NPC environment a RAM image of
`the write-only registers is maintained, allowing examination
`of register contents. The registers may be
`'read' by calling
`VREGRD, or with specialized routines (see IDS document).
`
`REGISTER 0
`REGISTER 1
`
`In
`registers contain VDP option control bits.
`two
`These
`they are not written to directly with VREGWR, but
`practise,
`rather are accessed through specialized routines. VSETXT is
`called to set the appropriate bits to place the VDP in TEXT
`mode. Other
`routines are VSETGI (Graphics I) and
`VSETG2
`(Graphics II).
`
`(the video
`'vertical blanking' option
`The VDP also has a
`register 1.
`screen
`is "blacked out") which is selected in
`The
`screen may be blanked with no effect on VRAM by calling
`the IDS routine VBLKON. The screen is restored with VBLKOFF.
`Other bits in register 1 determine the size and magnifica(cid:173)
`tion of sprites (see 3.2.6 SPRITES).
`
`REGISTER 2
`
`2 defines the base address of the Name Table. The
`Register
`address is set by calling VNAMEST.
`
`REGISTER 3
`
`Register 3 defines the base address of the Colour Table. The
`address is set by calling VCOLRST.
`
`REGISTER 4
`
`Register 4 defines the base address of the Pattern Generator
`Table. The address is set by calling VPTRNST •
`
`----------------------------------------------------------------
`Spec. 50-90020490
`Page 1 - 13
`June 8, 1984
`
`~
`
`•
`
`PMC Exhibit 2077
`Apple v. PMC
`IPR2016-00753
`Page 17
`
`

`
`VIDEO DISPLAY PROCESSOR
`
`REGISTER 5
`
`~
`
`Register 5 defines the base address of the Sprite Attribute
`Table. The address is set by calling VATRIST.
`
`REGISTER 6
`
`Register 6 defines the base address of the Sprite Pattern
`Generator Table. The address is set by calling VSPRIST.
`
`REGISTER 7
`
`The high order 4 bits of register 7 define the colour code
`'I' pixels in Text mode. The low order bits define
`of
`the
`for '0' pixels in Text mode and
`colour code
`the backdrop
`colour
`in all modes. Register 7 is
`loaded
`by calling
`VREGWR.
`
`STATUS REGISTER
`
`The status register contains the following flags.
`
`F
`
`C
`
`5S
`
`raster
`the
`Interrupt Flag is set at the end of
`- The
`scan of the last line of the display. It is reset to 0
`after
`the VDP Status Register is read or the VDP
`is
`reset.
`
`is
`flag
`The Coincidence Flag
`two
`set whenever
`'I' bits at the same
`sprites have
`screen
`location.
`(see 3.2.6 SPRITES).
`
`four
`is set whenever more than
`The Fifth Sprite Flag
`sprites are displayed on the same horizontal line. The
`number of the fifth sprite is also loaded into the VDP
`Status Register. (see 3.2.6 SPRITES).
`
`~
`
`----------------------------------------------------------------
`Spec. 50-90020490
`Page 1 - 14
`June 8, 1984
`
`~
`
`PMC Exhibit 2077
`Apple v. PMC
`IPR2016-00753
`Page 18
`
`

`
`VIDEO DISPLAY PROCESSOR
`
`~ 3.2.2 TEXT MODE
`for
`is primarily
`As
`is
`implied by the name, Text mode
`textual applications. The Name Table and Pattern Table are
`used
`to define the appearance of the screen. The Colour
`Table is not used. Patterns are 6 X 8 pixels, which allows
`for an increase to 40 characters per line. The Name Table is
`960 (40 X 24) bytes. The Pattern Table contains the library
`of
`text patterns to be displayed.
`It is 2048 bytes
`long,
`consisting of 256 eight byte entries. Since each
`text
`position
`is only 6 pixels wide,
`the two least significant
`bits of each row of the pattern are ignored. There can only
`be two colours for the entire screen, one colour for all of
`the 'I' bits,
`and a second colour for all of the '0' bits.
`The colours are defined
`in VDP
`register 7
`(see 3.2.1
`REGISTERS).
`
`text patterns are loaded into the Pattern Table,
`Typically,
`such that the entry number corresponds to the ASCII code for
`the letter. For example,
`the ASCII code for the letter 'A'
`is 65 (decimal). With the eight byte pattern fot toe letter
`'A' occupying pattern number 65 in the Pattern Table,
`the
`letter can be written
`to screen pattern position 3
`by
`writing 65 to the third entry in the Name Table (Figure 2).
`
`~
`
`a T.V
`line on
`40 characters per
`for
`allows
`Text mode
`display. However, because of T.V. overscan, characters
`should not be written
`to columns 0,1,38 or 39. This
`effectively reduces the display to 36 characters per line.
`
`3.2.3 GRAPHICS I MODE
`
`imaqa
`The VRAM tables that are used to generate the screen
`for Graphics I mode are the PATTERN NAME TABLE (Name Table),
`PATTERN GENERATOR TABLE (Pattern Table) and COLOUR TABLE.
`The Name Table determines the screen position for a pattern.
`T~e Pattern Table determines which pixels within a pattern
`wlll be turned on. The Colour Table determines the colour of
`a pixel.
`
`~
`
`PMC Exhibit 2077
`Apple v. PMC
`IPR2016-00753
`Page 19
`
`

`
`VIDEO DISPLAY PROCESSOR
`
`screen into 8 X 8 pixel patterns,
`the
`The VDP divides
`meaning
`that the Name Table has 768 one byte entries. The
`Pattern Table contains a library of patterns that may be
`placed
`in any pattern position on the screen. The Pattern
`Table
`is 2048 bytes long, consisting of 256 eight byte
`entries. There
`is a maximum,
`therefore, of
`256 unique
`patterns which may be displayed at anyone time in Graphics
`I. The offset of the pattern within the Pattern Table forms
`the name of the pattern. To display a pattern at a specific
`position on the screen,
`the pattern name is written to
`the
`appropriate entry in the Name Table.
`
`~
`
`~
`
`----------------------------------------------------------------
`Spec. 50-90020490
`Page 1 - 16
`June 8, 1984
`
`~
`
`PMC Exhibit 2077
`Apple v. PMC
`IPR2016-00753
`Page 20
`
`

`
`•
`
`•
`
`VIDEO DISPLAY PROCESSOR
`
`NAME TABLE
`+--------+ <-- ENTRY 0
`
`+--------+ <-- ENTRY 3
`1
`(65)
`1
`+--------+
`
`+--------+ <-- ENTRY 95
`(66)
`1
`1
`+--------+
`
`+--------+ <-- ENTRY 959
`1
`1
`+--------+
`
`PATTERN TABLE
`+--------+ <-- ENTRY 0
`
`+--------+ <-- ENTRY 65
`1000000--1
`1001000--1
`1010100--1
`1100010--1
`1111110--1
`1100010--1
`1100010--1
`1100010--1
`+--------+ <-- ENTRY 66
`1000000--1
`1111100--1
`1100010--1
`1100010--1
`1111100--1
`1100010--1
`1100010--1
`1111100--1
`+--------+ <-- ENTRY 67
`
`+--------+ <-- ENTRY 255
`+--------+
`
`T.V. Display has 'A' (pattern 65) in screen position 3,
`and 'B' (pattern 66) in position 95.
`
`A
`
`B
`
`Fig. 2. Name and Pattern Table Mapping in
`Text Mode
`
`•
`
`Spec. 50-90020490
`
`Page 1 - 17
`
`June 8, 1984
`
`PMC Exhibit 2077
`Apple v. PMC
`IPR2016-00753
`Page 21
`
`

`
`VIDEO DISPLAY PROCESSOR
`
`The colours of pixels are specified in the Colour Table. The
`colour
`table contains 32 one byte entries. Each entry
`defines
`two colours,
`the high order nibble of each entry
`defines the colour of the 'I' bits, and the low order nibble
`defines the colour of the '0' bits. The first entry in
`the
`Colour Table defines the colours for patterns 0
`- 7,
`the
`second entry
`for patterns 8 - 15 and so on. This
`scheme
`imposes
`the
`following colour
`restrictions: 1) anyone
`pattern can only display two colours and 2)
`changing
`the
`colours
`for one pattern implies a colour change
`for
`the
`seven other patterns within the colour group.
`
`•
`
`3.2.4 GRAPHICS II MODE
`
`II mode is similar to Graphic