throbber
Takahashi anticipates claims 1-8, 11-16, and 18 of U.S. Patent No. 5,591,678 to
`Bendik et al. (“the ʼ678 Patent”) under 35 U.S.C. § 102
`
`
`Prior Art Cited in this Chart:
`U.S. Patent No. 5,347,154 to Takahashi et al. (“Takahashi”)
`
`
`Claim Language
`Claim 1
`A method of fabricating
`a microelectronic device,
`comprising the steps of:
`
`furnishing a first
`substrate having an
`etchable layer, an etch-
`stop layer overlying the
`etchable layer, and a
`wafer overlying the etch-
`stop layer;
`
`Takahashi
`
`
`“The present invention relates to a semiconductor
`device and a process for manufacturing the same and,
`more particularly, to a semiconductor substrate having
`a structure composed of a thin film laminated layer
`intensively formed with transistor elements and a light
`valve device having said semiconductor substrate, a
`liquid crystal layer and an opposed substrate integrated
`with one another.” 1:7-14.
`“First of all, the single crystal silicon plate and the
`tentative substrate 82 are prepared.” 14:35-36.
`
`“Below this surface insulating film 3, there is arranged
`a single crystal semiconductor Thin film 4.” 5:54-56.
`
`“For forming the insulating film, a silicon nitride film
`may be deposited at first as a surfacing treatment on the
`tentative silicon substrate, and then the silicon dioxide
`layer may be deposited by the CVD.” 7:35-38.
`
`“The silicon nitride layer thus deposited as the
`surfacing treatment performs as an etching stopper at a
`later step.” 7:42-44.
`
`Figure 11
`
`forming a
`
`
`
`
`
`
`“This single crystal semiconductor thin film 4 is
`1
`
`Petitioner Samsung - SAM1016
`
`

`
`Claim Language
`microelectronic circuit
`element in the exposed
`side of the wafer of the
`first substrate opposite to
`the side overlying the
`etch-stop layer;
`
`Takahashi
`formed not only with a channel forming region 5 for
`each transistor element but also with a source region 6
`and a drain region 7 which merge into the channel
`forming region 5. Below the single crystal
`semiconductor thin film 4, there is arranged through a
`gate oxide layer 8 an intermediate electrode film which
`forms a gate electrode 9 of the transistor element.”
`5:56-63.
`
`“Below said intermediate electrode film, moreover,
`there is arranged a back layer film 10. This back layer
`film 10 is formed with contact holes which extend to
`the source region 6 and the drain region 7 so that a
`source electrode 11 and a drain electrode 12 are
`arranged therethrough.” 5:63-68.
`
`Figure 12
`
`
`
`
`“At a step shown in FIG. 14, moreover, the support
`substrate 15 is adhered to the surface of the applied
`adhesive film 14.” 16:13-15.
`
`“By heat treatment in this state, the solvent contained in
`the adhesive film 14 is evaporated away, and the fusion
`of the silicon dioxide particle advances until the
`support substrate 15 and the SOI substrate 81 are
`rigidly adhered to each other in face-to-face relation.”
`16:18-23.
`
`Figure 14
`
`
`
`attaching the wafer of the
`first substrate to a second
`substrate; and
`
`
`
`2
`
`

`
`Claim Language
`
`
`
`Takahashi
`
`
`
`
`“For forming the insulating film, a silicon nitride film
`may be deposited at first as a surfacing treatment on the
`tentative silicon substrate, and then the silicon dioxide
`layer may be deposited by the CVD. This CVD silicon
`dioxide layer is excellent in adhesiveness to the
`semiconductor substrate so that the semiconductor
`substrate can be thermally bonded in a fixed manner.
`The silicon nitride layer thus deposited as the surfacing
`treatment performs as an etching stopper at a later step.
`At the aforementioned fourth step, the tentative
`substrate can be etched off by using the silicon nitride
`layer as the etching stopper. As a result, a flat
`insulating film is exposed to the outside.” 7:35-47.
`
`“Specifically, due to the difference in the etching rate
`between the silicon and the silicon nitride, the etching
`removal of the tentative substrate 82 of silicon
`substantially ends at the step reaching the silicon nitride
`film. Thus, the semiconductor device shown in FIG. 1
`can be finally obtained. Incidentally, the arrangement
`shown in FIG. 14 is inverted upside-down from that
`shown in FIG. 1 so that it may be easily understood.”
`16:43-47.
`
`
`
`etching away the
`etchable layer of the first
`substrate down to the
`etch-stop layer.
`
`
`
`3
`
`

`
`Takahashi
`
`
`
`Figure 1
`
`Claim Language
`
`Figure 14
`
`
`
`Claim 2
`The method of claim 1,
`further including an
`additional step, after the
`step of etching, of
`patterning the etch-stop
`layer.
`
`
`
`
`
`“The thin film laminated layer 1 is partially formed
`with a through hole 16. This through hole 16 can be
`formed by etching the field insulated film 13
`selectively.” 9: 21-23.
`
`Figure 3
`
`Claim 3
`
`
`
`
`
`
`
`
`4
`
`

`
`Claim Language
`The method of claim 2,
`further including an
`additional step, after the
`step of patterning, of
`forming an electrical
`connection to the
`microelectronic circuit
`element through the
`patterned etch-stop layer
`and through the wafer.
`
`Takahashi
`“The surface insulating film 3 is formed thereover with
`a pad electrode 17 for connecting the drain electrode 12
`electrically through the through hole 16. The pad
`electrode 17 is provided for electric connection
`between the semiconductor device and an external
`circuit and is wire-bonded, for example. For this
`purpose, the pad electrode is given a size of about 100
`μm square far larger than that of the transistor element.
`Thus, the pad electrode occupying an especially large
`area is separated from the back wiring of the integrated
`circuit and formed on the surface so that the area of the
`back can be effectively exploited.” 9:24-36.
`
`Figure 3
`
`
`
`
`
`“The surface insulating film 3 is formed thereover with
`a pad electrode 17 for connecting the drain electrode 12
`electrically through the through hole 16. The pad
`electrode 17 is provided for electric connection
`between the semiconductor device and an external
`circuit and is wire-bonded, for example. For this
`purpose, the pad electrode is given a size of about 100
`μm square far larger than that of the transistor element.
`Thus, the pad electrode occupying an especially large
`area is separated from the back wiring of the integrated
`circuit and formed on the surface so that the area of the
`back can be effectively exploited.” 9:24-36.
`
`
`
`Claim 4
`The method of claim 2,
`further including an
`additional step, after the
`step of patterning, of
`forming an electrical
`connection to the wafer
`through the patterned
`etch-stop layer.
`
`
`
`5
`
`

`
`Takahashi
`
`
`
`Figure 3
`
`Claim Language
`
`Claim 5
`The method of claim 1,
`wherein the etchable
`layer is silicon, the etch-
`stop layer is silicon
`dioxide, and the wafer is
`single-crystal silicon.
`
`Claim 6
`The method of claim 1,
`wherein the second
`substrate contains a
`second microelectronic
`circuit element.
`
`
`
`
`
`
`
`“For forming the insulating film, a silicon nitride film
`may be deposited at first as a surfacing treatment on the
`tentative silicon substrate, and then the silicon dioxide
`layer may be deposited by the CVD. This CVD silicon
`dioxide layer is excellent in adhesiveness to the
`semiconductor substrate so that the semiconductor
`substrate can be thermally bonded in a fixed manner.
`The silicon nitride layer thus deposited as the surfacing
`treatment performs as an etching stopper at a later step.
`7:35-44.
`
`“Preferably at said first step, the semiconductor
`substrate made of single crystal silicon is thermally
`bonded at first to the tentative substrate of silicon
`through the insulating film of silicon dioxide.” 7:30-33.
`
`“Another effect is that the semiconductor device
`satisfying various applications can be remarkably easily
`manufactured by adding various electrodes to the
`exposed surface of the semiconductor device in
`accordance with the design specifications. For example,
`
`6
`
`

`
`Claim Language
`
`Takahashi
`the semiconductor device substrate for driving the light
`valve is obtained by forming a transparent electrode for
`defining the pixel, for example. Moreover, the DRAM
`can be easily manufactured by forming a capacity
`electrode. By forming an additional gate electrode,
`furthermore, it is possible to manufacture a
`semiconductor device which is composed of transistor
`elements having an excellent ON/OFF ratio.” 17:12-
`28.
`
`“Between said substrate 191 and a support substrate
`192 formed with a transparent electrode 197, there is
`formed an electrooptical substance layer 194.” 25:2-5.
`
`“The support substrate 192 is formed on its surface
`with the common electrode 197 made of a transparent
`conductive film.” 26:28-30.
`
`“In the present embodiment, the thin semiconductor
`film over the thin insulating film, from which the
`support substrate of the semiconductor device, is used
`as one substrate of the light valve device.” 24:62-65.
`
`“FIGS. 25(a) and 25(b) are sections showing a
`sixteenth embodiment according to the present
`invention, in which the semiconductor device is
`constructed as a light valve device.” 5:29-32.
`
`Figure 14
`
`
`
`7
`
`
`
`
`
`

`
`Claim Language
`
`Takahashi
`Figure 25(a) (inverted)
`
`Figure 25(b)
`
`
`
`Claim 7
`The method of claim 6,
`wherein the step of
`attaching includes the
`step of making an
`electrical contact from
`the microelectronic
`circuit element on the
`wafer of the first
`substrate to the second
`microelectronic circuit
`element on the second
`substrate.
`
`
`
`
`
`
`
`“As a result, this flat surface insulating film 3 can be
`easily subjected to a variety of additional treatments
`including at least the formation of electrodes, and the
`single crystal silicon thin film 4 can also be easily
`subjected, if desired, to an additional treatment.” 16:53-
`58.
`
`“As has been described hereinbefore, according to the
`present invention, the integrated circuit formed on the
`SOI substrate is transferred to the support substrate, and
`the tentative substrate portion of the SOI substrate is
`then removed so that the semiconductor device has its
`one face wired in advance and its other face exposed to
`the outside. This exposed face has a flat surface and is
`arranged just therebelow with the single crystal
`semiconductor thin film. Since the exposed face can be
`subjected to the additional treatment of forming
`8
`
`

`
`Claim Language
`
`
`
`Takahashi
`electrodes or wiring, the semiconductor device
`according to the present invention can be given the
`double-side wiring structure to raise an effect that its
`packaging density is improved far better than the prior
`art.” 16:59-17:4.
`
`“Another effect is that the semiconductor device
`satisfying various applications can be remarkably easily
`manufactured by adding various electrodes to the
`exposed surface of the semiconductor device in
`accordance with the design specifications. For example,
`the semiconductor device substrate for driving the light
`valve is obtained by forming a transparent electrode for
`defining the pixel, for example. Moreover, the DRAM
`can be easily manufactured by forming a capacity
`electrode. By forming an additional gate electrode,
`furthermore, it is possible to manufacture a
`semiconductor device which is composed of transistor
`elements having an excellent ON/OFF ratio.” 17:12-
`28.
`
`“Between said substrate 191 and a support substrate
`192 formed with a transparent electrode 197, there is
`formed an electrooptical substance layer 194.” 25:2-5.
`
`“The support substrate 192 is formed on its surface
`with the common electrode 197 made of a transparent
`conductive film.” 26:28-30.
`
`“In the present embodiment, the thin semiconductor
`film over the thin insulating film, from which the
`support substrate of the semiconductor device, is used
`as one substrate of the light valve device.” 24:62-65.
`
`“FIGS. 25(a) and 25(b) are sections showing a
`sixteenth embodiment according to the present
`invention, in which the semiconductor device is
`constructed as a light valve device.” 5:29-32.
`
`
`9
`
`

`
`Claim Language
`
`Figure 14
`
`Takahashi
`
`
`Figure 25(a) (inverted)
`
`Figure 25(b)
`
`
`
`
`
`Claim 8
`The method of claim 1,
`wherein the step of
`attaching includes the
`steps of placing a layer
`of epoxy between the
`second substrate and the
`
`
`
`
`
`
`
`“Preferably, said support layer 2 has a two-layer
`structure composed of an adhesive film 14 applied to
`the back layer film 10 and a support substrate 15
`fixedly adhered face-to-face by the adhesive film 14.”
`6:10-13.
`
`
`10
`
`

`
`Claim Language
`wafer portion of the first
`substrate, and degassing
`and curing the epoxy.
`
`Takahashi
`“A material to be used for the adhesive can be
`exemplified by a polyimide resin or an epoxy resin.”
`15-55:57.
`
`“The support substrate 15 may be formed in advance
`with through holes for releasing the gas which is
`generated during a heat treatment of the adhesive.”
`6:17-20.
`
`“Without such through holes, the gas produced in the
`course of thermally setting the adhesive film 14 would
`have no way of escape to make it difficult to adhere the
`uniform and rigid support substrate 15 fixedly in the
`face-to-face relation. If the produced gas is confined in
`the adhesive film 14 to form bubbles, it deteriorates the
`reliability of the semiconductor device. In order to
`eliminate this disadvantage, therefore, the degasifying
`through holes 15 are formed in advance in the support
`substrate 15 in accordance with the present
`embodiment.” 12:14-24.
`
`Figure 1
`
`Claim 11
`A method of fabricating
`a microelectronic device,
`comprising the steps of:
`furnishing a first
`substrate having an
`etchable layer, an etch-
`stop layer overlying the
`etchable layer, and a
`
`
`
`
`
`
`
`See, claim 1, supra.
`
`See, claim 1, supra.
`
`11
`
`

`
`Claim Language
`wafer overlying the etch-
`stop layer;
`forming a
`microelectronic circuit
`element in the exposed
`side of the wafer of the
`first substrate opposite
`the side overlying the
`etch-stop layer;
`attaching the wafer of the
`first substrate to a second
`substrate, the second
`substrate having a
`second microelectronic
`circuit element therein;
`making an electrical
`contact from the
`microelectronic circuit
`element in the wafer of
`the first substrate to the
`second microelectronic
`circuit element on the
`second substrate; and
`etching away the
`etchable layer of the first
`substrate down to the
`etch-stop layer; and
`forming an electrical
`connection to the
`microelectronic circuit
`element in the wafer of
`the first substrate
`through the etch-stop
`layer.
`
`Claim 12
`The method of claim 11,
`wherein the etchable
`layer is silicon, the etch-
`
`
`
`Takahashi
`
`See, claim 1, supra.
`
`See, claims 1 and 6, supra.
`
`See, claim 7, supra.
`
`See, claim 1, supra.
`
`See, claims 2 and 3, supra.
`
`
`See, claim 5, supra.
`
`12
`
`

`
`Claim Language
`stop layer is silicon
`dioxide, and the wafer is
`single-crystal silicon.
`Claim 13
`A method of fabricating
`a microelectronic device,
`comprising the steps of:
`furnishing a first
`substrate having a silicon
`etchable layer, a silicon
`dioxide etch-stop layer
`overlying the silicon
`layer, and a single-
`crystal silicon wafer
`overlying the etch-stop
`layer, the wafer having a
`front surface not
`contacting the silicon
`dioxide layer;
`forming a
`microelectronic circuit
`element in the front
`surface of the single-
`crystal silicon wafer;
`attaching the front
`surface of the single-
`crystal silicon wafer to a
`first side of a second
`substrate; and
`etching away the silicon
`etchable layer down to
`the silicon dioxide etch-
`stop layer using an
`etchant that attacks the
`silicon layer but not the
`silicon dioxide layer.
`
`Takahashi
`
`
`See, claim 1, supra.
`
`See, claims 1 and 5, supra.
`
`See, claim 1, supra.
`
`See, claim 1, supra.
`
`See, claim 1, supra.
`
`“Specifically, due to the difference in the etching rate
`between the silicon and the silicon nitride, the etching
`removal of the tentative substrate 82 of silicon
`substantially ends at the step reaching the silicon nitride
`film.” 16:43-47.
`
`Figure 1
`
`
`
`13
`
`

`
`Claim Language
`
`
`
`Takahashi
`
`
`
`
`
`See, claim 2, supra.
`
`
`See, claim 3, supra.
`
`Claim 15
`The method of claim 14,
`further including an
`additional step, after the
`step of patterning, of
`forming an electrical
`connection to the
`microelectronic circuit
`element through the
`patterned etch-stop layer
`and through the wafer.
`Claim 16
`The method of claim 14,
`further including an
`additional step, after the
`step of patterning, of
`forming an electrical
`connection to the wafer
`through the patterned
`etch-stop layer.
`Claim 18
`
`The method of claim 13, See, claim 8, supra.
`14
`
`
`See, claim 4, supra.
`
`Claim 14
`The method of claim 13,
`further including an
`additional-step, after the
`step of etching, of
`patterning the etch-stop
`layer.
`
`
`
`

`
`Takahashi
`
`Claim Language
`wherein the step of
`attaching includes the
`steps of placing a layer
`of epoxy between the
`second substrate and the
`front surface of the
`single-crystal silicon
`wafer, and
`degassing and curing the
`epoxy.
`
`
`
`
`15

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