Case 2:15-cv-00341-JRG-RSP Document 112-4 Filed 01/29/16 Page 2 of 11 PageID #:
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`Jerzy Ruzyllo
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`SEMICONDUCTOR
`GLOSSARY
`
`Semitone' The leading online learning resource
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`Case 2:15-cv-00341-JRG-RSP Document 112-4 Filed 01/29/16 Page 3 of 11 PageID #:
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`SEMICONDUCTOR GLOSSARY
`rri)1^"iil nintri ,
`An Introduction to Semi,` (cid:9)
`
`Jerzy Ruzyllo
`
`Penn State University
`University Park, Pennsylvania
`
`Prosto Multimedia Publishing
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`Case 2:15-cv-00341-JRG-RSP Document 112-4 Filed 01/29/16 Page 4 of 11 PageID #:
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`Information in this glossary, either numerical or conceptual, is provided at the
`author's discretion. Author disclaims any liability based on or related to the
`contents of this glossary.
`
`Semiconductor Glossary
`
`Published by:
`
`Prosto Multimedia Publishing
`Post Office Box 283
`State College, PA 16804, USA
`
`Copyright ©2004 by Jerzy Ruzyllo.
`
`All rights reserved. No part of this book may be reproduced or transmitted in any form
`or by any means, electronic or mechanical, including photocopying, microfilming, and
`recording or by any information storage and retrieval system, without permission in
`writing from the author.
`
`Cover design by Pawel Ruzyllo
`
`To order additional copies or to inquire about discounts on bulk quantities
`visit:
`www.semiconductorglossary.com
`
`Library of Congress Control Number: 2004095961
`
`ISBN 0-9759820-0-1
`
`PRINTED IN THE UNITED STATES OF AMERICA
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`Case 2:15-cv-00341-JRG-RSP Document 112-4 Filed 01/29/16 Page 5 of 11 PageID #:
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`access time time needed for the bit of information to go to and
`return from the memory cell.
`memory cell
`
`accumulation condition of semiconductor surface in MOS devices
`in which concentration of majority carriers is higher than concentration
`of dopant atoms.
`depletion, inversion
`
`activation energy defines reaction kinetics of the process; amount
`of energy required to initiate the reaction; expressed in units of eV.
`
`active Si layer Si la-y-er on top of the Iouried oxide (BOX) in SOI
`substrates; "active" because transistors are built into it; as opposed to
`Si substrate (Si underneath BOX) which is there to provide mechanical
`support only.
`BOX fully depleted SOL SOI.
`
`ADC Analog to Digital Converter.
`
`adhesion ability of materials to stick (adhere) to each other.
`adhesion promoter
`
`adhesion promoter material used to improve adhesion of materials;
`typically understood as a material improving adhesion of photoresist to
`the wafer surface in the lithographic processes.
`HMDS
`
`binding between foreign molecules and the solid
`adsorption (cid:9)
`occurring only on the solid surface; specie is attached to the solid
`surface by weak physical forces (van der Waals force).
`Desorption, van der Waals force
`
`AFM see Atomic Force Microscopy.
`
`afterglow plasma see remote plasma.
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`Boltzmann constant, k 1.38 x 1023 J/K
`
`Boltzmann transport equation (cid:9)
`fundamental relationship
`describing transport of free carriers in semiconductors.
`
`bonded SOI SOI substrates formed by bonding two silicon wafers
`with oxidized surfaces; following bonding one wafer is polished down
`to the desired thicknes's of active layer with interface oxide becoming a
`buried oxide, alternative approach: cleaved SOL
`cleaved SOI, SIMOX
`
`100r011 element from the IIIrd group of periodic table acting. as 1111
`acceptor (p-type dopant) in silicon; the only p-type dopant broadly
`used in silicon device manufacturing.
`acceptor
`
`boron penetration term usually refers to penetration of the gate
`oxide by boron from heavily p-doped poly-Si gate contact in PMOS
`part of the CMOS cell; at elevated temperature boron from the contact
`readily segregates into the adjacent oxide causing reliability problems.
`ONO, segregation coefficient
`
`bottom anti-reflective coating a layer deposited on the back
`surface of the wafer to prevent reflection from the bottom surface of
`radiation passing through the wafer; in advanced photo- lithography
`used to enhance control of critical dimensions (CD) by suppressing
`standing waves effects and reflective notching.
`anti-reflective coating
`
`bottom-up processing way of building functional structures on
`semiconductor substrates which relies on self-assembly of molecules
`and self-patterning taking place at the surface of the substrate.
`top-down processing
`
`boundary layer a layer in contact with solid surfaces immersed in
`gaseous or liquid medium; within boundary layer characteristics of the
`medium are different than in its bulk.
`
`BOX see buried oxide.
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`BRT Base Resistance controlled Thyristor.
`thyristor
`
`brush scrubbing cleaning of semiconductor surfaces using rotating
`brushes; used to remove heavy residues which cannot be efficiently
`removed without mechanical interactions; used in post-CMP wafer
`cleaning.
`post-CM' cleaning, scrubbing
`
`BST (BaSr)TiO3, barium strontium titanate, dielectric featuring very
`high k (in the range 160-600) at thicknesses exceeding about 40 nm;
`displays feiToelectrie properties; used in storage capacitors, can be
`deposited by the variety of methods including MOCVD, sputtering,
`and misted deposition (LSMCD).
`MOCVD, sputtering, mist deposition
`
`BTS see bias-temperature stress.
`
`buffer layer term typically refers to a layer sandwiched between
`two single-crystal materials to accommodate difference in their
`crystallographic structures (lattice constants).
`superlattice
`
`bulk CMOS CMOS circuitry implemented on a standard bulk Si
`wafer rather than in a thin layer of Si on insulator (SOI substrate).
`SOI wafer
`
`buried oxide, BOX oxide layer in SOI substrates; oxide (Si02)
`buried in silicon wafer at the depth ranging from less than 100 nm to
`several micrometers from the wafer surface depending on application;
`formed by oxidation or oxygen implantation depending on the type of
`SOT substrate; thickness of BOX is typically in the range from about 40
`nm to about 100 nm.
`bonded SOI, SIMOX
`
`burn-in reliability testing procedure used to force defective devices
`to fail; process designed to detect early failures of semiconductor
`devices; device is subjected to electric stress at elevated temperature
`for a lengthy period of time.
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`EST Emitter Switched Thyristor.
`Thyristor
`
`etch, etching subtractive process in the course of which a solid is
`either dissolved in liquid chemicals (wet etching) or converted into
`gaseous compound (dry etching); one among key processes in
`semiconductor manufacturing.
`dry etching, wet etching
`
`etch anisotropy
`etching is taking place preferentially in the
`Lk/ the siarface oind with no lateral vtn~inrr• key
`A ; (cid:9)
`"yrri .11 -Fr%
`requirement in definition of very fine geometrical features;
`accomplished by accelerating of etching species toward the substrate.
`anisotropic etch, isotropic etch
`
`etch mask material blocking etching in select areas on the wafer
`surface; typically photoresist is acting as an etch mask.
`photoresist
`
`etch selectivity selected material is etched at the much higher rate
`than other materials present on the wafer surface.
`non-selective etching, selective etching
`
`etch stop material featuring drastically different etch characteristics
`than material to be etched; layer of "etch stop" material is placed
`underneath etched material to stop etching process.
`endpoint
`
`EUV see extreme UV.
`
`EUVL Extreme Ultraviolet Lithography, i.e. photolithography using
`wavelength <150 nm; shorter than the wavelength emitted by excimer
`lasers.
`excimer laser
`
`evaporation common technique used to deposit thin film materials;
`Ton
`material to be deposited is heated in vacuum in 10-6 Ton - (cid:9)
`range until it melts and starts evaporating; vapor of material is
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`segregation coefficient, mat given temperature solubility of a
`given element in material A is in general not the same as in material B;
`m = equilibrium concentration of an element in material A/ equilibrium
`concentration of the same element in material B.
`boron penetration
`
`SEL see Surface Emitting Laser.
`
`Selective Area Chemical Vapor Deposition, SACVD CVD
`process which deposits thin film material in selected areas on the wafer
`surface only; selectivity of deposition is controlled by chemical
`composition of the surface which can be locally altered.
`CVD
`
`selective deposition see Selective Area Chemical Vapor Depo-
`sition ; also deposition can be limited to selected areas on the wafer by
`using masks.
`mask
`
`selective epitaxy epitaxial growth on the substrate which is only
`partially a single-crystal material; for instance in the case of single
`crystal Si partially covered with oxide, Si will grow epitaxially only
`(selectively) on the surface of a single-crystal Si; also chemical
`composition of the surface can be altered for the purpose of promoting
`selective epitaxial-growth,
`epitaxy, SACVD
`
`selective etching etching processes in which one material is etched
`rapidly while the other is etched very slowly, or not etched at all; e.g.
`HF:H20 solution is etching SiO2 very rapidly while not etching silicon.
`non-selective etching
`
`selective exposure foundation of pattern definition using litho-
`graphic processes; only selected areas of the resist are exposed to
`radiation; accomplished either by using masks or by localizing
`exposure using finely focuses beam.
`e-beam lithography, lithography photolithography, mask, resist
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`tdopted by the
`"sport between
`
`SOG see Spin-on Glass.
`
`rds and used to
`
`bstrate in which
`
`tplex electronic
`
`riscous liquid is
`trough thermal
`
`i element in the
`ninants of Si02
`' the influence of
`ristics of MOS
`vented in Si
`
`which wafer is
`Tolatilization of
`irried out using
`
`tte oxide but no
`
`SOI Silicon-On-Insulator; silicon substrate of choice in cutting edge
`CMOS technology; basically a silicon wafer with a thin layer of oxide
`(Si02) buried in it (buried oxide, BOX); devices are built into a layer of
`silicon (active layer) on top of the buried oxide; SOI substrates provide
`superior isolation between adjacent devices in an integrated circuit as
`compared to devices built into bulk wafers; allows elimination of
`"latch-up" in CMOS devices; also, improved performance of SOI
`devices due to reduced parasitic capacitances; also used in MEMS
`manufacturing in which case buried SiO2 acts as a sacrificial material;
`other than SiO2 materials can be used as a buried insulator; e.g. SOS
`and SOAN..
`bonded SOT, bulk CMOS, latch-up, SIMOX, SOAN, SOS, UTSi
`
`solar cell two-tettninal semiconductor device which converts solar
`light into electric signal; requires presence of potential barrier within
`semiconductor which is typically accomplished by the formation of a
`p-n junction; potential barrier separates hole and electrons generated by
`irradiation of semiconductor establishing different potential at device
`teuninals; because of the low cost, solar cells using amorphous silicon
`are the most common in spite of the fact that their efficiency is lower
`than efficiency of solar cells made out of polycrystalline or single-
`crystal silicon; semiconductors other than Si are also used to
`manufacture solar cells.
`photoelectric effect
`
`solid-phase crystallization, SPC process in the course of which
`adequately executed heat treatments cause conversion of amorphous
`phase in the solid into crystalline phase.
`
`solid-solubility limit to the number of atoms of element A that can
`be incorporated into solid B at any given temperature; in silicon
`processing an upper limit on the concentration of dopant atoms that can be
`absorbed by the Si lattice at given temperature.
`doping
`
`SOM (cid:9)
`Sulphuric (acid)-Ozone Mixture; H2SO4/03; increasingly
`common cleaning solution designed to remove organic contaminants
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`VUV Vacuum Ultraviolet; very short wavelength UV radiation
`emitted by plasma.
`UV
`
`w
`
`wafer thin (thickness depends on wafer diameter, but is typically less
`than 1 mm), circular slice of single-crystal semiconductor material
`used to manufacture semiconductor discrete devices and integrated
`circuits; depending on material, wafer diameter may range from about
`25, mm to :300 mm• cut along selected crystallographic plane from the
`larger piece (typically ingot or boule) of single-crystal semiconductor;
`typically one surface only is finely polished, although, wafers polished
`on both sides are also available; wafer can be entirely homogenous
`(bulk wafer) or highly engineered (e.g. SOI wafer); entire
`semiconductor device manufacturing infrastructure is adapted to the
`size and shape of processed wafers.
`bulk CMOS, ingot, SOI
`
`wafer bonding process in which two semiconductor wafers are
`bonded to form a single substrate featuring specific properties;
`commonly applied to form SOI substrates; bonding of wafers of
`different materials, e.g. GaAs on Si, or SiC on Si allows development
`of novel device structures.
`bonded SOl, SOl
`
`wafer charging process of acquiring static electric charge by the
`wafer during processing; highly undesired effect that needs to be
`monitored and minimized.
`static charge
`
`wafer diameter depending on material and needs semiconductor
`substrates are available in the form of circular "wafers" 0.5 mm to 1
`mm thick and ranging in diameter from 1 inch (25 mm) to 12 inch (300
`mm); wafer diameter is determined by the availability of sufficiently
`large single-crystal ingots/boules of any given semiconductor; largest
`for Si, smaller for hard to process compound semiconductors such as
`Sic, or GaN.
`wafer
`
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