6(3
`
`n
`
`IriTILITY (cid:9)
`
`'44R4U
`o
`SERIAL NUMBER
`
`5.594678
`
`;
`PATENT DATE (cid:9)
`VAN 0 7 1997
`
`PATENT
`NUMBER
`
`(4*
`ot
`
`FILING DATE
`
`CLASS
`
`SUBCLASS
`
`2_ 0 ig
`
`GROUP ART UNIT
`
`RONALD (cid:9)
`
`FX,NN)ILA, CARLMAD, CA
`
`„
`
`0 0 „ (cid:9)
`
`1.11. /
`
`IL
`
`',."•••••
`
`Foreign priority claimed (cid:9)
`,,,.
`0 yes (cid:9) El no (cid:9)
`35 USC 119 conditions met (cid:9) 0 y (cid:9)
`.. ''''''
`Verified and Acknowledged (cid:9)
`Examinert initials
`,
`
`,As
`FILED
`1"1040'
`
`STATE OR
`COUNTRY
`1...: A
`
`SHEETS
`DRWGS.
`3
`
`TOTAL
`CLAIMS
`1.8
`
`INDEP.
`CLAIMS
`3
`
`FILING FEE
`RECEIVED .
`,.:730.00
`
`ATTORNEY'S
`DOCKET NO.
`PD-92654A
`
`ANOELES.
`
`PRocPYiY,:c nr ,'il,iHFAc'TUP:f.Nr. A MTORCELECTRIC DEVICE UST% A REMOVABLE.
`SUPPORT OUBSTRATE AN;-:, ETCH-STOP
`
`U.S. DEPT. OF COMM.! PAT. & TM--PTO-436L (Rev.12-94)
`
`PARTS OF APPLICATION
`FILED SEPARATELY
`
`NOTICE 00 ALLOWANCE MAILED
`
`7
`
`D/3 ðW (cid:9)
`
`Assistant Examiner
`
`/01/6t
`Applications Examiner
`CLAIMS ALLOWED
`Print Claim
`Total Claims (cid:9)
`
`Yent
`
`ISSUE FEE
`Date Paid,/V1
`Amount Due
`
`/7)6'0,06
`
`.0M
`
`Label
`Area
`
`Form I5TO-436A
`(Rev. 8/92)
`
`John iNigbliff'
`Supen/j§oryatent Examiner
`PaterifExamining Group 110
`Primary Examiner
`PREPARED FOR ISSUE
`
`DRAWING
`
`Sheets Drw
`
`r.Prinf Fig.
`
`ISSUE
`BATCH
`NUMBER
`
`WARNING: The information disclosed herein may be restricted. Unauthorize
`by the United States Code Title 35, Sections 122, 181 and 36
`Patent & Trademark Office is restricted to authorized employee
`
`disc sure may be prohibited
`ssession outside the U.S.
`and contractors only.
`
`(FACE)
`
`FEE IN FILE
`
`Petitioner Samsung - SAM1011
`
`1
`
`(cid:9)
`

`
`PATENT APPLICATION
`
`II
`
`I 11111111
`
`08482172
`
`II
`
`'PROVED FOR LICENSE
`
`"1-iALS— (cid:9)
`
`Date
`Received
`or
`Mailed
`
`OS/
`
`Date
`Entered
`or
`Counted
`
`13. (cid:9)
`Lela 14 (cid:9)
`n
`q\LO
`Co. (cid:9)
`17.
`175.
`
`CONTENTS
`
`pplication (cid:9)
`
` Pre Jk rn
`bi sc\oc,uog
`
`papers.
`
`•
`
`JAN 0 7 1997
`
`1-20-
`21. (cid:9)
`2:2
`
`7.
`
`'1•••• ;
`
`31.
`
`(FRONT)
`
`2
`
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`

`
`*.U.S. GOVERNMENT PRINTING OFFICE 1993-347-700
`
`PATENT NUMBER
`
`CLASS
`
`APPLICATION SERIAL NUMBER
`
`ORIGINAL CLASSIFICATION .
`SUBCLASS
`
`'i--37
`
`zb
`
`.._
`
`Osg7 (cid:9)
`
`4401K 1-% ?) I 7 2._
`
`APPLICANT'S NAME (PLEASE PRINT)
`
`j bs.E: ph (cid:9) 7, 0/f it/pm
`
`IF REISSUE, ORIGINAL PATENT NUMBER
`
`1
`i (cid:9)
`,.,., T Q i ,
`
`1-
`
`INTERNATIONAL
`TERNATIONAL CLASSIFICATION
`21 / 2.3
`,:..) /
`2. (
`
`, (cid:9) f.
`2- (cid:9) I / 1.-,so
`
`/ L
`
`f,,i
`
`a
`
`H
`
`ID
`
`! (cid:9) !
`
`)-1
`
`(.7
`
`PTO 270
`(REV. 5.91)
`
`Date
`
`Claim
`713
`
`. .c. (cid:9)
`
`Ts
`iC
`
`,
`12, V
`
`:3 3
`Ly; 4
`
`56
`..._
`/ 7
`q 8
`9
`10 10
`
`-\
`
`--.7-,
`
`12, 1-3" 7..-.
`'..1"4.
`
`15' 17
`16 18
`17 19
`ji3 20 —....".
`'24...4
`22
`23
`24
`25
`26
`27
`28
`29
`30
`31
`32
`33
`34
`35
`36
`37
`38
`39
`40
`41
`42
`43
`44
`45
`46
`47
`48
`49
`50
`
`1 (cid:9)
`
`CROSS REFERENCE(S)
`
`SUBCLASS
`(ONE SUBCLASS PER BLOCK)
`77 et-
`
`b)6, 135 D)6, /5O
`6 6 2. t i 630 t 1 •:vp#-
`
`CLASS
`
`f 37
`/ ii- 5
`t 5 6
`
`I
`
`,.
`
`GROUP
`ART UNIT
`
`i i .07
`
`ASSISTANT EXAMINER (PLEASE STAMP OR PRINT FULL NAME)
`04 U / ID E. 64)4 ://3/U
`PRIMARY EXAMINER (PLEASE STAMP/O
`RINT FULL NAME)
`c- ki, e
`ISSUE CLASSIFICATION SLIP
`
`U.S. DtPARTMENT OF COMMERCE
`PATENT AND TRADEMARK OFFICE '
`
`1P
`
`....—...
`Si
`.c
`cm
`
`T-
`
`To (cid:9)
`C
`Lr.
`
`0-
`
`51
`52
`53
`54
`55
`56
`57
`58
`59
`60
`61
`62
`63
`64
`65
`66
`67
`68
`69
`70
`71
`72
`73
`74
`75
`76
`77
`78
`79
`80
`81
`82
`83
`84
`85
`86
`87
`88
`89
`90
`91
`92
`93
`94
`95
`96
`97
`98
`99
`100
`
`SYMBOLS
`
`Rejected
`Allowed
`- (cid:9)
`_ (Through numheral) Canceled
` Restricted
`1.1 (cid:9)
`Non-elected
` Interference
`I
`Appeal
`A (cid:9)
`Objected
`0 (cid:9)
`
`(LEFT INSIDE)
`
`3
`
`(cid:9)
`(cid:9)
`(cid:9)
`

`
`ID NO. (cid:9)
`
`DATE
`
`)
`
`--
`1
`4,
`
`30?
`
`i 2"/95
`
`
`
` - 9,5 7i /
`
`POSITION (cid:9)
`CLASSIFIER
`EXAMINER
`TYPIST
`VERIFIER
`CORPS CORR.
`SPEC. HAND
`FILE MAINT.
`DRAFTING
`
`
`
`Date
`
`Tel c
`
`Claim
`To
`•c cn
`0
`51
`52
`53
`54
`55
`56
`57
`58
`59
`60
`61
`62
`63
`64
`65
`66
`67
`68
`69
`70
`71
`72
`73
`74
`75
`76
`77
`78
`79
`80
`81
`82
`83
`84
`85
`86
`87
`88
`89
`90
`91
`92
`93
`94
`95
`96
`97
`98
`99
`100
`
`Claim
`76
`a)
`a
`
`c
`Li:
`
`t,y 4
`
`I 07.7_
`
`3 3
`.1- 4
`.--- 5
`? 6
`7 7
`
`9
`;3!) 10
`
`1
`
`1
`
`).4.,
`13 (5):::
`If 16
`15' 17
`lb 18
`}719
`1
`'1g 20 ":"....*
`''.2s1,,,t
`22
`23
`24
`25
`26
`y
`28
`29
`33
`31
`32
`33
`34
`35
`36
`37
`38
`39
`o
`41
`42
`43
`44
`45
`46
`47
`48
`o
`93
`
`INDEX OF CLAIMS
`
`Date
`
`SYMBOLS
`
`Rejected
`Allowed
`(Through numberal) Canceled
`Restricted
`Non-elected
` Interference
`Appeal
`Objected
`
`1.4
`
`A (cid:9)
`0 (cid:9)
`
`(LEFT INSIDE)
`
`4
`
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`

`
`•••••
`
`SEARCH NOTES
`
`Date
`
`Exmr.
`
`A PS (egif,-7-01F)
`
`II-3513
`
`Class
`
`I-37
`
`1 411
`
`I i il-...
`
`5E4,-,,d4
`4-37
`
`SEARCHED
`Sub.
`Date
`
`Exmr.
`
`fi-zcf--93 o-
`2Airi
`Dii,-, )355
`ITC).
`" (cid:9)
`/
`
`U Lo (cid:9)
`
`631)J" -1
`701
`uprikig,
`q15-
`um/...a._
`
`1-11,e1-
`7.1-1'1
`
`cfi---
`0-
`
`
`
`
`
`,
`
`,
`
`INTERFERENCE SEARCHED
`Class
`Sub.
`Date
`Exmr.
`eRzitti)
`ce--
`1,37
`
`,,p,r', ii,f , :,,1
`zo
`
`/5 L-
`
`'
`
`f (cid:9)
`
`-
`
`'7014,
`
`'----- (cid:9)
`
`-----'
`
`
`
`(RIGHT OUTSIDE)
`
`5
`
`

`
`UTILITY
`SERIAL (cid:9)
`NUMBER
`
`MQ
`MU
`
`SERIAL NUMBER (cid:9)
`
`DATE
`
`' (cid:9)
`• „
`
`I GROUP ART UNIT
`i: i fi 7
`
` EXAMINER
`
`620e.heL..
`
`FMN (cid:9)
`
`1
`GERARD T. MALLOY, 'OCEANS IDE, CA;
`MRLSDAD, CA.
`
`**T (cid:9)
`
`jAm********************
`
`VERI.FtED
`
`"rnrJ:7 GRAWTED 07/a7/93
`
`Foreign priority ciairned
`_.
`35 USC 1195oridltIons met
`_..----
`Verified and Acknowledged
`
`0 yes
``1:3 y
`
`(lino
`no
`
`Exam er's Ini (cid:9) as
`
`AS
`FILED
`loommoten
`
`STATE OR
`COUNTRY
`.
`
`CA
`
`SHEETS
`DRWGS.
`
`TOTAL
`CLAIMS
`
`INDEP.
`CLAIMS
`
`. FILING FEE
`RECEIVED
`
`ATTORNEY'S
`DOCKET NO.
`
`::.::I
`
`::;::1
`
`3
`
`V:i:f.-i-.:::-..: „ 1..-; 0
`F---1) -- 926 (cid:9)
`
`zi-
`
`E:LDG (cid:9)
`
`c: —126
`
`';;0000-002S
`
`•T-a
`
`PRO CE SS OF /214AA)FAcivAIA/6-
`(cRoEi..,EcTRoNtc D4(,/ic.,E vs/A/4- 4 4'&101/4/31.4. suPpoRr (cid:9)
`74 TE AND ETCH-5 TOP
`US. DEPT. of COMMePat. & TM Office— PT0•4361. (rev. 1048)
`
`7'
`
`PARTS OF APPLICATION
`FILED SEPARATELY
`
`NOTICE OF ALLOWANCE MAILED
`
`ISSUE FEE
`Date Paid
`Amount Due
`
`4-1-/1"6 E, G-6Wei31LL
`
`Assistant Examiner
`
`(cid:9)lIIMINIMIOSIMMICOMPSMOSIOMOSIM,
`
`u
`
`_ Applications Examiner 7-a/ii44(
`,CLAIMS ALLOWED
`Print Claim
`TotaLCIalins
`
`I (3
`
`Sheets Drwg.
`
`DRAWING
`Figs. Drwg.
`
`Print Fig.
`
`ISSUE--"
`'BATCH
`„NUMBER
`
`Label
`Area
`
`(cid:9)!NM
`
`Form PTO-436A
`(Rev, 8/92)
`
`141 (cid:9)
`
`Primary Examiner
`PREPARED FOR ISSUE
`
`WARNING: The information disclosed herein may be restricted. Unauthorized disclosure may be prohibited
`by the United States Code Title 35, Sections 122, 181 and 368. Possession outside the U.S.
`Patent & Trademark Office is restricted to authorized employees and contractors only.
`
`(FACE)
`
`6
`
`(cid:9)
`(cid:9)
`

`
`APPROVED FOR LICENSE
`
`I.
`
`INITIALS (cid:9)
`
`
`
`13qF-Pe ate
`
`Received
`or
`Mailed
`
`00 O 6120-
`
`Date
`Entered
`or
`Counted
`
` 1. Application
` 2. /—E-
`
` 3
`
` 4.
`
`5.
`
`CONTENTS
`
`papers.
`
`b-sZA
`qh9
`
`6. (cid:9)
`7. Mi.- (cid:9)
`8. 10014
`
`
`\o/ kmot+
`
`Iv AN
`-n6",
`
`9Atc-r (cid:9)
`
`
`
`4,-- 6
`9 -dt
`
`tiffi N 9SE
`
`
`
`
`
`
`
`
`
`
`
`
`
`10k (cid:9)
`
`11. (cid:9)
`
` 12. (cid:9)
`
` 13. (cid:9)
`
`14.
`
` 15. (cid:9)
`
` 16. (cid:9)
`
`17. (cid:9)
`
` 18. (cid:9)
`
` 19. (cid:9)
`
`20. (cid:9)
`
`21. (cid:9)
`
`22. (cid:9)
`
`23.
`
`24.
`
`25.
`
`26.
`
`27.
`
`28.
`
`29. (cid:9)
`
`30. (cid:9)
`
` 31. (cid:9)
`
`32. (cid:9)
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`(FRONT'
`
`-,••n•n•••••••
`
`7
`
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`

`
`AWL!: (cid:9)
`
`AMA
`
`tr U.S. GOVERNMENT PRINTING OFFICE 1993-347-700
`
`PATENT NUMBER
`
`ORIGINAL CLASSIFICATION
`
`APPLICATION SERIAL NUMBER
`
`0 S 0o6 Ps
`
`APPLICAN 'S NAME (P(ASE PRINT) (cid:9)
`
`,
`
`,
`
`0--05kpi-( a :&v b ik e4- a )(
`
`IF REISSUE, ORIGINAL PATENT NUMBER
`
`INTERNATIONAL CLASSIFICATION 5`
`
`R 0 1 L--
`
`.E_.) S LLL.
`8
`0 (cid:9)
`i
`L
`
`PTO 270
`(REV. 5-91)
`
`2_ (
`,5--
`2-( / 3
`Z (
`4 0
`
`Claim
`Tcs ...ac
`
`Tu_
`
`'0
`....#
`
`Date
`
`
`'2.. 2V \
`..f, (cid:9) 3
`
`Li• (cid:9) 4
`5
`6
`
`1 7
`8
`
`9
`1 (cid:9)
`it) (cid:9) 10
`
`NP44%,
`
`13 F5.
`16
`17
`g, 18
`IA 19
`20
`
`•
`
`--,
`..--
`
`----
`
`, (cid:9)
`
`S V
`2.2
`23
`24
`25
`26
`27
`28
`29
`30
`31
`32
`33
`34
`35
`36
`37
`38
`39
`40
`41
`42
`43
`44
`45
`46
`47
`48
`49
`50
`
`CLASS
`
`CLASS
`
`SUBCLASS zo
`' CROSS REFERENCE(S)
`/
`SUBCLASS
`/ (cid:9)
`(ONE SUBCLASS PER BLOCK)
`
`3? pl.-
`7 16
`Dia )35- DIG, WO
`—1--/-1
`66,2-
`
`3b
`
`.
`
`'
`
`GROUP
`UNIT
`ARE
`1....
`
`07
`
`ASSISTANT EX6MINER )PLEASE STAMP OR PRINT FULL NAME)
`/
`
`3 gl--
`
`AV/ (cid:9)
`° WO ri
`PRIMARY EXAMINER (PLEASE STAMP OR PRINT FULL NAME)
`
`0 • cliAcIbileig I
`ISSUE CLASSIFICATION SLIP
`
`U.S. DEPARTMENT OF COMMERCE
`PATENT AND TRADEMARK OFFICE
`
`Date
`
`•
`
`.
`
`.,
`
`
`
`al c
`IL
`
`Claim
`To
`.c 0)
`'c
`0
`51
`' 52
`53
`54
`55
`56
`57
`58
`59
`60
`61
`62
`63 .
`64
`65
`66
`67
`68
`69
`70
`71
`72
`73
`74
`75
`76
`77
`78
`79
`80
`81
`82
`83
`84
`85
`86
`87
`88
`89
`90
`
`91
`92
`93
`94
`95
`96
`97
`98
`99
`100
`
`SYMBOLS
`
`Rejected
`Allowed
`(Through numberal) Canceled
` RestrIcted
`Non-elected
` Interference
`Appeal
` Objected
`
`A (cid:9)
`0 (cid:9)
`
`(LEFT INSIDE)
`
`,
`
`8
`
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`

`
`N
`
`ID NO.
`
`,
`
`27 rr
`:1_(
`
`. (cid:9)
`
`POSITION (cid:9)
`CLASSIFIER
`EXAMINER
`TYPIST
`VERIFIER
`CORPS CORR.
`SPEC. HAND
`FILE MAINT.
`DRAFTING
`
`INDEX OF CLAIMS
`
`Date
`
`Claim
`-a
`.16: -
`
`.s u_
`
`1
`7
`5 41-
`
`2_ 2 V.
`3
`
`5
`G 6
`i 7
`C: 8
`
`1 9
`10 10 ,
`..-
`
`•=..'
`
`It
`t 13
`
`IM
`16
`15 (cid:9) 17
`18
`19
`
`V
`22 —
`23
`24
`25
`26
`27
`28
`29
`30
`31
`32
`33
`34
`35
`36
`37
`38
`39
`40
`41
`42
`43
`44
`45
`46
`47
`48
`49
`111111011111
`
`SYMBOLS
`
` Rejected
`Mowed
`_ (Through numberal) Canceled
` Restricted
`Non-elected
` Interference
`Appeal
` Objected
`
`
`
`1 - 11-1
`
`A (cid:9)
`0 (cid:9)
`
`1
`
`(LEFT INSIDE)
`
`DATE
`
`,---,-/-_,
`
`
`2/'i /^ 5
`( (cid:9)
`'
`
`
`
`
`
`•
`
`Date
`
`•
`
`.
`
`'a
`E
`
`Claim
`Co
`.c
`IF
`u
`51
`52
`53
`54
`55
`56
`57
`58
`59
`60
`61
`62
`63
`64
`65
`66
`67
`68
`69
`70
`71
`72
`73
`74
`75
`76
`77
`78
`79
`80
`81
`82
`83
`84
`85
`86
`87
`88
`89
`90
`91
`92
`93
`94
`95
`96
`97
`98
`99
`100
`
`9
`
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`

`
`SEARCHED
`
`Class
`
`437
`
`Sub.
`
`Date
`
`Exmr.
`
`-7.ablq.71-
`
`/)._2,03
`
`9-
`
`i1e-6
`
`6
`
`D16-, Bis)
`PI G , Jo
`( 3L)/ 6'2i
`q0/
`c(1
`ufWie-
`1-37 VC
`
`) j
`
`11- M3
`
`0'
`
`
`g--
`
`?-65-
`
`,
`
`SEARCH NOTES
`
`Date
`
`Exmr.
`
`frp 5f4Rew
`
`P-30-73
`
`a--
`
`INTERFERENCE SEARCHED
`Sub.
`Date
`Exmr.
`Class
`(E).-
`7-$--?It
`715-
`-Lo--
`....ila
`11
`Zex
`((
`4.41, (cid:9)
`I's I I
`1,6Z, 0.5
`WO i (
`
`itvg;rmv. (cid:9)
`)56
`
`'
`
`.
`
`.
`
`(RIGHT OUTSIDE)
`
`10
`
`

`
`PATENT APPLICATION SERIAL NO.
`
`09 006120
`
`U.S. DEPARTMENT OF COMMERCE
`PATENT AND TRADEMARK OFFICE
`FEE RECORD SHEET
`
`C$14080 02/09/93 OB006120'
`
`•8-325. (cid:9)
`
`101
`
`732.00CH
`
`D-92654 I,'
`
`PTO-1556
`(5/87)
`
`11
`
`(cid:9)
`(cid:9)
`(cid:9)
`(cid:9)
`

`
`BAR CODE LABEL
`
`111 1111 1 (cid:9) 11 11111111 1 ii 11
`
`U . S . PATENT APPLICATION
`,
`
`SERIAL NUMBER
`
`FILING DATE
`
`CLASS
`
`GROUP ART UNIT
`
`08/006,120
`
`01/19/93
`
`437
`
`-
`
`1107
`
`. (cid:9)
`
`OA
`CIA. (cid:9) ,?Li_.-E- (cid:9)
`
`
`-61;IJOSEPH )7t JBENDIK, CARLSBAD, CA; GERARD TI MALLOY, OCEANSIDE, CA;
`
`8 (cid:9)
`RONALD MI/FINNILA, CARLSBAD, CA.
`(1-4
`ie,OC)
`
`... (cid:9)
`
`**CONTINUING DATA*********************
`VERIFIED
`
`**FOREIGN/PCT APPLICATIONS************
`VERIFIED
`
`FOREIGN FILING LICENSE GRANTED 07/07/93
`TOTAL
`CLAIMS
`
`STATE OR
`COUNTRY
`
`SHEETS
`DRAWING
`
`INDEPENDENT
`CLAIMS
`
`FILING FEE
`RECEIVED
`
`ATTORNEY DOCKET NO.
`
`CA
`
`3
`
`21
`
`3
`
`$862.00
`
`PD-92654
`
`HUGHES AIRCRAFT COMPANY
`BLDG. Cl MAIL STATION A-126
`cn (cid:9)
`c.) . (cid:9)
`P. 0. BOX 80028
`LI
`LOS ANGELES, CA 90080-0028
`
`PROCESS OF MANUFACTURING A MICROELECTRONIC DEVICE USING A REMOVABLE
`SUPPORT SUBSTRATE AND ETCH—STOP
`
`1 (cid:9)
`P
`
`This is to certify that annexed hereto is a true copy from the records of the United States
`Patent and Trademark Office of the application which is identified above.
`By authority of the
`COMMISSIONER OF PATENTS AND TRADEMARKS
`
`Date (cid:9)
`
`Certifying Officer
`
`12
`
`

`
`3$ (cid:9)
`
`L
`Ju ly
`10
`1
`99?
`US "
`IB 800 170 (cid:9)
`"Express Mail" mail 4) 10)03
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`APPLICATION TRANSMITTAL LETTER
`
`Certification under 37 CFR 1,10 (If applicable)
`
`Docket No. PD- 926
`
`00612e0
`
`Jan. 19, 1993
`Date of Deposit
`
`Is being deposited with the United States Postal Service "Express Mail Post Office
`I hereby certify that this application
`1.10 on the date indicated above and is addressed to the Commissioner of Patents
`to Addressee service under 37 CFR
`20231.
`and Trademarks, Washington, D.C.
`
`Sue S. Freitag
`(Typed or printed name of person
`mailing application)
`
`S
`(Signature of person (cid:9)
`
`ication)
`
`The Commissioner of Patents and Trademarks
`Washington, D.C. 20231
`Sir:
`1_,06 Transmitted herewith for filing is the patent application, including 2 sheet(s) of drawings, of inventor(s)
`Joseph J. Bendik et al.
`for: (Method of Fabricating a Microelectronic Device.
`
`The filing fee for this application is calculated below:
`
`For:
`
`Basic Fee
`Total Claims
`Independent Claims
`Multiple Dependent Claims
`TOTAL FIUNG FEE
`
`Number (cid:9)
`Filed (cid:9)
`
`21
`
`3
`0
`
`CLAIMS AS FILED
`Number
`Extra (cid:9)
`
`Rate
`
`-20 =
`-3 =
`
`1
`
`0
`
`x
`x
`
`$ 22.00
`$ 74.00
`$230.00
`
`$ 710.00
`$ 22.00
`$ 0
`
`$ (cid:9)
`$ 732.00
`
`Please charge Deposit Account No. 08-3250 of Hughes Aircraft Company, Los Angeles, California, In the amount
`732.00
`(cid:9). The Commissioner is hereby authorized to charge any additional fees which may be
`of $ (cid:9)
`required, or credit any overpayment, to that account.
`
`The Commissioner is further hereby authorized to charge to said above Deposit Account No. 08-3250, pursuant
`to 37 CFR 1.25(b), any fees whatsoever which may properly become due or payable, as set forth in 37 CFR 1.16 to
`1.17 inclusive, for the entirependency of this application without specific additional authorization.
`
`This form Is submitted in triplicate.
`
`HUGHES AIRCRAFT COMPANY
`
`W. C. Schubert, Reg. No. 30,102
`
`ED
`
`hes_AIrcraft-Company._—
`Cl, Mail Station A:126
`P.O. Box 80028
`tmosIglide§„SK:Koao-oon
`805-562-2108
`Telephone: (cid:9)
`Jan. 19, 1993
`Date: (cid:9)
`
`09-506 (9/92)
`
`13
`
`

`
`N't‘
`
`(cid:9) 0a. THE UNITED STATES PATENT AND TRADEMARK OFFICE
`JAN
`APPUCATION TRANSMITTAL LETTER
`
`93
`IB 800 44311
`'Express Mar (cid:9)
`
`mber
`
`Certification under 37 CFR 1.10 (if aoollcablel
`
`PA .i IT
`Docket No. PD- 92654
`
`Jan. 19, 1993
`Date of Deposit
`
`I hereby certify that this application Is being deposited with the United States Postal Service 'Express Mail Post Office
`to Addressee" service under 37 CFR 1.10 on the date indicated above and is addressed to the Commissioner of Patents
`and Trademarks, Washington, D.C. 20231.
`
`Sue S. Freitag
`(Typed or printed name of person
`mailing application)
`
`The Commissioner of Patents and Trademarks
`Washington, D.C. 20231
`Sir:
`
`• 5\fq— S .Al2-tr't
`(Signature of person mallime (cid:9)
`
`'cation)
`
`Transmitted herewith for filing is the patent application, including 2 sheet(s) of drawings, of inventor(s)
`Joseph J. Bendik et al.
`for Method of Fabricating a Microelectronic Device.
`
`The filing fee for this application Is calculated below:
`
`For:
`
`Basic Fee
`Total Claims
`Independent Claims
`Multiple Dependent Claims
`TOTAL FIUNG FEE
`
`Number (cid:9)
`Filed (cid:9)
`
`21
`3
`0
`
`CLAIMS AS FILED
`Number
`Extra (cid:9)
`
`Rate
`
`-20
`-3 ii.
`
`1
`0
`
`x
`x
`
`$ 22.00
`$ 74.00
`$230.00
`
`$ 710.00
`22.00
`$ (cid:9)
`
`$ 73S.00
`
`Please charge Deposit Account No. 08-3250 of Hughes Aircraft Company, Los Angeles, California, In the amount
`732.00
`(cid:9). The Commissioner is hereby authorized to charge any additional fees which may be
`of $ (cid:9)
`required, or credit any overpayment, to that account.
`
`The Commissioner Is further hereby authorized to charge to said above Deposit Account No. 08-3250, pursuant
`to 37 CFR 1.25(b), any fees whatsoever which may properly become due or payable, as set forth In 37 CFR 1.16 to
`1.17 inclusive, for the entire pendency of this application without specific additional authorization.
`
`This form is submitted in triplicate.
`
`HUGHES AIRCRAFT COMPANY
`
`W. C. Schubert, Reg. No. 30,102
`
`Hughes Aircraft Company
`Bldg. Cl, Mali Station A-126
`P.O. Box 80028
`Los Angeles, CA 90080-0028
`Telephone: (cid:9)
`805-562-2108
`Date: (cid:9)
`Jan. 19, 1993
`
`14
`
`

`
`og/roo6Izo
`
`PATENTS
`PD-92654
`
`METHOD OF FABRICATING A MICROELECTRONIC DEVICE
`
`Inventors:
`
`Joseph J. Bendik
`
`Gerald T. Malloy
`
`Ronald M. Finnila
`
`15
`
`

`
`00 006120
`
`-1-
`
`METHOD OF FABRICATING A MICROELECTRONIC DEVICE
`
`S31 BACKGROUND OF THE INVENTION
`
`This invention relates to microelectronic
`devices, and, more particularly, to a microelectronic
`5 device that is moved from one support to another
`support during fabrication.
`
`Microelectronic devices are normally prepared
`by a series of steps such as patterning, deposition,
`implantation, growth, and etching that build up an
`10 electronic circuit on or near the top surface of a
`Interconnection pads are
`thin substrate wafer. (cid:9)
`placed on the surface of the wafer to provide
`connections to external leads or to other
`microelectronic devices. (cid:9)
`Such a microelectronic
`15 device is considered a two-dimensional structure in
`the plane of the substrate wafer. There are usually
`multiple layers of deposited conductors and
`insulators, but each layer is quite thin. Any height
`of the device in the third dimension perpendicular to
`20 the substrate surface is much less than the
`dimensions in the plane of the substrate wafer, and
`is often no more than a few thousand Angstroms.
`The microelectronic devices or arrays of such
`devices are usually placed inside a protective
`25 housing called a package, with leads or connection
`pads extending out of the package. (cid:9)
`When the
`microelectronic devices are used, a number of the
`packages with their contained microelectronic devices
`are normally affixed to a base such as a phenolic
`30 plastic board. (cid:9)
`Wires are run between the various
`devices to interconnect them. There may be metallic
`traces imprinted onto the base to provide common
`power, ground, and bus connections, and the base
`itself has external connections. Such boards with a
`
`16
`
`

`
`-2-
`
`number of interconnected devices are commonly found
`inside both consumer and military electronics
`For example, an entire microcomputer may
`equipment. (cid:9)
`be assembled as a number of microelectronic devices
`5 such as a processor, memory, and peripheral device
`controllers mounted onto a single board.
`The present inventors have determined that for
`some applications it would be desirable to stack and
`interconnect a number of such two-dimensional
`10 microelectronic devices, fabricated on a substrate
`wafer, one on top of the other to form a
`three-dimensional device. (cid:9)
`The stack might also
`include other circuit elements such as interconnect
`layers and thin film sensors as well. (cid:9)
`To
`15 interconnect the stacked wafers using leads that
`extend from the pads on the top of one wafer to the
`pads on the top of another wafer, around the sides of
`the wafers, or using plug interconnects or the like,
`would be clumsy, space consuming, and impossible to
`20 do for the case of highly complex circuitry requiring
`many interconnects.
`In considering fabrication techniques to
`produce such three-dimensional, stacked devices, the
`fragility of the devices is a concern. (cid:9)
`The
`25 individual substrate wafers and their microelectronic
`circuitry are usually made of fragile semiconductor
`materials, (cid:9)
`chosen (cid:9)
`for (cid:9)
`their (cid:9)
`electronic
`characteristics rather than their strength or
`fracture resistance. (cid:9)
`The selected fabrication
`30 technique cannot damage the circuitry that has
`already been placed onto the substrate wafer.
`Thus, there is a need for a method to
`fabricate three-dimensional microelectronic devices
`using stacked substrate wafers with circuitry already
`35 on them. (cid:9)
`The present invention fulfills this need,
`and further provides related advantages.
`
`17
`
`

`
`-3-
`
`SUMMARY OF THE INVENTION
`
`The present invention provides an approach for
`fabricating microelectronic devices that permits
`three-dimensional manipulations and fabrication steps
`5 with two-dimensional devices already deposited upon a
`invention (cid:9)
`permits
`wafer (cid:9)
`substrate. (cid:9)
`The (cid:9)
`microelectronic devices to be prepared using
`well-established, inexpensive thin-film deposition,
`etching, and patterning techniques, and then to be
`10 further processed singly or in combination with other
`such devices, into more complex devices.
`In accordance with the invention, a method of
`fabricating a microelectronic device comprises the
`steps of furnishing a first substrate having an
`15 etchable layer, an etch-stop layer overlying the
`etchable layer, and a wafer overlying the etch-stop
`layer, and forming a microelectronic circuit element
`in the wafer of the first substrate. The method
`further includes attaching the wafer portion of the
`20 first substrate to a second substrate, and etching
`away the etchable layer of the first substrate down
`to the etch-stop layer. (cid:9)
`The second substrate may
`include a microelectronic device, and the procedure
`may include the further step of interconnecting the
`25 microelectronic device on the first substrate with
`the microelectronic device on the second substrate.
`In a typical application, the "back side"
`etch-stop layer is patterned, and an electrical
`connection to the microelectronic circuit element on
`30 the wafer is formed through the etch-stop layer.
`This technique permits access to the microelectronic
`circuit element from the back side. (cid:9)
`Electronic
`connections can therefore be made directly to the
`back side of the wafer layer, and indirectly to the
`35 front side microelectronic circuit element by opening
`
`18
`
`

`
`-4-
`
`access to front-side interconnects from the back
`side. (cid:9)
`Such an ability to achieve electronic access
`can be valuable for some two-dimensional devices, and
`also permits multiple two-dimensional devices to be
`5 stacked one above the other to form three-dimensional
`devices by using techniques such as indium bumps to
`form interconnections between the stacked devices.
`In a preferred approach to practicing the
`invention, a method of fabricating a microelectronic
`10 device comprises the steps of furnishing a first
`substrate having a silicon etchable layer, a silicon
`dioxide etch-stop layer overlying the silicon layer,
`and a single-crystal silicon wafer overlying the
`etch-stop layer. (cid:9)
`The wafer has a front surface not
`15 contacting the silicon dioxide layer. (cid:9)
`A
`microelectronic circuit element is formed in the
`single-crystal silicon wafer on or through the font
`surface. (cid:9)
`The method further includes attaching the
`front surface of the single-crystal silicon wafer to
`20 a first side of a second substrate, and etching away
`the silicon etchable layer of the first substrate
`down to the silicon dioxide etch-stop layer using an
`etchant that attacks the silicon layer but not the
`silicon dioxide layer. As discussed previously, the
`25 silicon dioxide layer may then be patterned and
`connections formed therethrough.
`The present approach is based upon the ability
`to transfer a thin film microelectronic circuit
`element or device from one substrate structure to
`30 another substrate structure. (cid:9)
`The circuit element
`usually is fabricated with a relatively thick first
`substrate that provides support during initial
`fabrication and handling. (cid:9)
`However, it is difficult
`to achieve electrical connections through such a
`35 thick substrate, because of the difficulty in
`locating deep, through-support vias precisely at the
`required point, the difficulty in insulating the
`
`j•
`
`19
`
`

`
`-5-
`
`walls of deep vias, and the difficulty in filling a
`The first
`deep via with conducting material. (cid:9)
`substrate cannot simply be removed to permit access
`to the bottom side of the electrical circuit element,
`5 as the assembly could not be handled in that very
`thin form.
`In the present approach, after initial circuit
`element fabrication on a first substrate structure,
`the electrical circuit element is transferred to a
`10 second substrate structure. (If the second substrate
`itself contains another microelectronic circuit
`element, (cid:9)
`between (cid:9)
`the (cid:9)
`two
`interconnections (cid:9)
`microelectronic circuit elements are made at this
`point, as by using an indium-bump technique/epoxy
`15 technique.) (cid:9)
`With the circuit element thus supported,
`the etchable portion of the first substrate, is
`removed by etching, down to the etch-stop layer. The
`terms "etchable" and "etch-stop" are used herein
`relative to a specific selected etchant. There is
`20 chosen an etchant that readily etches the etchable
`layer but has a much lower etching rate for the
`etch-stop layer. It is understood, however, that the
`etch-stop layer may be generally or selectively
`etched by yet other techniques, after the etchable
`25 layer is removed.
`Once the etchable layer is removed, the
`relatively thin etch-stop layer may be patterned and
`through-etched to provide access to the microelec-
`tronic circuit element, including its connection
`30 pads, through the etch-stop layer. Many alternative
`approaches are possible. (cid:9)
`For example, the
`two-dimensional structure may be used with direct
`back connections and indirect front connections. The
`additional surface area on the bottom of the
`35 etch-stop layer provides space for deposition of
`interconnection (cid:9)
`metallization (cid:9)
`traces. (cid:9)
`The
`two-dimensional structure may be stacked with other
`
`20
`
`

`
`(cid:9) (cid:9)
`
`-6-
`
`a
`form (cid:9)
`to (cid:9)
`structures (cid:9)
`two-dimensional (cid:9)
`three-dimensional structure. Further circuitry could
`be deposited upon the back side of the etch-stop
`layer, as needed and permitted by constraints imposed
`5 by the front-side circuit element structure.
`Thus, the present approach provides a highly
`flexible approach to the fabrication of complex
`microelectronic devices using a building-block
`Other features and advantages of the
`approach. (cid:9)
`10 present invention will be apparent from the following
`more detailed description of the preferred
`embodiment, taken in conjunction with the
`accompanying drawings, which illustrate, by way of
`example, the principles of the invention.
`
`15 (cid:9)
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`20
`
`Figure 1 is a diagrammatic process flow
`diagram for the approach of the invention, with the
`structure at each stage of fabrication indicated
`schematically;
`Figure 2 is a schematic side sectional view of
`a microelectronic device structure prepared according
`to the procedure of Figure 1;
`Figure 3 is a schematic side elevational view
`of a three-dimensional microelectronic device built
`25 from two-dimensional devices using the present
`approach; and
`Figure 4 is a schematic side elevational view
`of a "smart board" configuration.
`
`DETAILED DESCRIPTION OF THE INVENTION
`
`30 (cid:9)
`
`Referring to Figure 1, the present invention
`is practiced by first providing a first substrate 40,
`
`21
`
`

`
`-7-
`
`The first substrate 40 includes an
`numeral 20. (cid:9)
`etchable layer 42, an etch-stop layer 44 grown upon
`and overlying the etchable layer 42, and a wafer
`layer 46 bonded to and overlying the etch-stop layer
`5 44. Such substrates can be purchased commercially.
`In the preferred practice, -the etchable layer
`42 is a layer of bulk silicon about 500 micrometers
`thick and the etch-stop layer 44 is a layer of
`silicon dioxide about 1 micrometer thick. The wafer
`10 layer 46 is normally thicker than required when it is
`bonded to the etch stop layer 44, and is thinned to
`the required final thickness. (cid:9)
`A typical thinning
`process (cid:9)
`a
`involves (cid:9)
`lapping (cid:9)
`followed (cid:9)
`by (cid:9)
`chem-mechanical polish. (cid:9)
`Preferably, the wafer layer
`15 46 is a layer of single crystal silicon initially
`about 500 micrometers thick which becomes, after
`thinning, about 30 nanometers to 50 micrometers
`thick. (cid:9)
`These dimensions are not critical, and may be
`varied as necessary fo-r particular applications.
`20 (The structure depictions in Figures 1-4 are not
`drawn to scale.) (cid:9)
`The wafer layer 46 may also be or
`include an interconnect material such as a metal or
`other structure as may be appropriate for a
`particular application. (cid:9)
`In the present case, an
`25 optional via opening 48 is provided through the wafer
`layer 46. (cid:9)
`The use of this via 48 will become
`apparent from subsequent discussions.
`The first substrate 40 is prepared by applying
`well-known microelectronic techniques. (cid:9)
`The silicon
`30 dioxide etch-stop layer 44 is produced on a bulk
`silicon piece 42 by heating it in an oxygen-hydrogen
`atmosphere at a temperature of about 1100C for a time
`sufficient to achieve the desired thickness,
`typically about 2 hours. (cid:9)
`The wafer layer 46 is
`35 either deposited directly upon the etch-stop layer 44
`or fabricated separately and bonded to the etch-stop
`layer 46 by direct interdiffusion, preferably the
`
`22
`
`

`
`-8-
`
`The via 48 is produced by
`latter, and thinned. (cid:9)
`standard patterning and etching techniques. (All
`references herein to "standard" or "well known"
`techniques, or the like, mean that individual process
`5 steps are known generally, not that they are known in
`the present context or combination, or to produce the
`present type of structure.)
`A microelectronic circuit element 50 is formed
`in the wafer layer 46, numeral 22, working from a
`10 front exposed side 52. The microelectronic circuit
`element 50 may be of any type, and may itself include
`multiple (cid:9)
`layers (cid:9)
`semiconductors,
`metals, (cid:9)
`of (cid:9)
`insulators, etc. (cid:9)
`Any combination of steps can be
`used, (cid:9)
`including, (cid:9)
`for (cid:9)
`example, (cid:9)
`deposition,
`15 implantatidn, film growth, etching, and patterning
`steps. (cid:9)
`As used herein, the term "microelectronic
`circuit element" is to be interpreted broadly, and
`can include active devices and passive structure.
`For example, the microelectronic circuit element 50
`20 can include many active devices such as transistors.
`Alternatively, it may be simply a patterned
`electrical conductor layer that is used as an
`interconnect between other layers of structure in a
`stacked three-dimensional device, or may be a sensor
`25 element.
`An important virtue of the present invention
`is that it is operable with a wide range of
`microelectronic circuit elements 50, and therefore
`the present invention is not limited to any
`30 particular circuit element 50. (cid:9)
`In the presently
`preferred case, the first substrate 40 is silicon
`based, and therefore the microelectronic circuit
`element 50 is preferably a silicon-based device.
`Where the microelectronic circuit element 50 is based
`35 upon other material systems, it may be preferred for
`the first substrate to be made of a material
`compatible to that material system. In this usage,
`
`23
`
`

`
`-9-
`
`
`
`(cid:9) (cid:9)(cid:9) (cid:9)
`
`10
`
`15 (cid:9)
`
`20
`
`"compatible" means that the first substrate permits
`fabrication of the microelectronic circuit element 50
`therein.
`As it is illustrated in Figure 1, the
`5 microelectronic circuit element 50 includes two types
`of electrical interconnects. A front-side electrical
`interconnect (cid:9)
`direct (cid:9)
`electrical
`54 (cid:9)
`permits (cid:9)
`interconnection to the microelectronic circuit
`element 50 from "above", and back-side electrical
`interconnects 56 and 56' permit indirect front-side
`electrical interconnection to the microelectronic
`circuit element 50 and direct back-side electrical
`interconnection to the wafer layer 46 from "below",
`respectively. (cid:9)
`The front-side electrical interconnect
`54 is a metallic pad, and the back-side electrical
`interconnects 56 and 56' are each an electrical
`conductor such as polysilicon or a metal deposited
`into the via 48. (cid:9)
`The interconnect 54 is formed
`during the fabrication of the microelectronic circuit
`element 50, and the interconnects 56 and 56' are
`formed by opening. vias throug