United States Patent [191
`Cade et a1.
`
`[11] Patent Number:
`[45] Date of Patent:
`
`4,599,792
`Jul. 15, 1986
`
`[54] BURIED FIELD SHIELD FOR AN
`INTEGRATED CIRCUIT
`[75] Inventors: Paul E. Cade, Colchester; Badih
`El-Kareh, Milton; Ick W. Kim, St.
`Albans, all of Vt.
`International Business Machines
`Corporation, Armonk, NY.
`[21] Appl. No.: 620,982
`[22] Filed:
`Jun. 15, 1984
`
`[73] Assignee:
`
`[51] Int. 01.4 .................... .. H01L 21/20; HOlL 21/31
`[52] US. Cl. ............................. .. 29/576 w; 29/576 E;
`29/577 C; 29/580; 148/DIG. 25; l48/DIG. 50;
`l48/DIG. 135; 148/187
`[58] Field of Search .............. .. 29/576 W, 576 E, 571,
`29/577 C, 580; 148/DIG. 26, DIG. 25, DIG.
`50, DIG. 135, 187; 357/34, 49, 53
`References Cited
`U.S. PATENT DOCUMENTS
`
`[56]
`
`3,846,198 11/1974 Wen et a1. ........................... .. 156/17
`3,959,045 5/1976 Antypas .................... ..
`4,089,021 5/ 1978 Sato et a1. ................. ..
`4,290,831 9/1981 Ports et a1. ........................ .. 148/ 187
`
`OTHER PUBLICATIONS
`Jastrzebski, “Comparison of Different SOI Technolo
`gies” RCA Review, vol. 44, Jun. 1983, pp. 251-269.
`Kimura et al., “Epitaxial Film Transfer Technique”
`Applied Physics Letter 43(3), Aug. 1, 1983, pp.
`263-265.
`Primary Examiner-Aaron Weisstuch
`Assistant Examiner-T. Quach
`Attorney, Agent, or Firm—Sughrue, Mion, Zinn,
`Macpeak, and Seas
`ABSTRACT
`[57]
`A method for fabrication of a buried ?eld shield in a
`semiconductor substrate. A seed substrate is prepared
`by depositing an epitaxial layer or a seed wafer and then
`depositing a heavily doped layer and a thin dielectric,
`The thin dielectric is patterned for contact holes and
`then a conductive ?eld shield is deposited and pat
`terned. A thick quartz layer is deposited over the ?eld
`shield and dielectric. A mechanical substrate is anodi
`cally bonded to the quartz of the seed substrate and the
`original seed wafer is etched back to expose the epitax=
`ial layer for further fabrication.
`
`
`
`4,404,737 9/1983 Kanzaki et al. 4,408,386 10/1983 Takayashiki et al.
`
`29/576 E
`
`10 Claims, 17 Drawing Figures
`
`Si - SUBSTRATE
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`BURIED FIELD SHIELD FOR AN INTEGRATED
`CIRCUIT
`
`DESCRIPTION
`Field of Invention
`The invention pertains generally to integrated cir
`cuits. In particular, it pertains to the fabrication of a
`buried ?eld shield beneath other semiconductor devices
`on an integrated circuit chip.
`
`BACKGROUND OF THE INVENTION
`A technology for integrated circuits must be judged
`on at least two criteria besides the obvious need for
`practicality of fabrication. The devices should be
`densely packed on the integrated circuit to allow a large
`number of individual devices on a small area chip. Fur
`thermore, the devices must be fast so that the integrated
`circuit has a high throughput. The speed of most tech
`nologies is limited by stray capacitance, both between
`devices and to the substrate. Many recent designs, such
`as those disclosed by Rao in U.S. Pat. No. 4,388,121 and
`by Koomen et al in U.S. Pat. No. 4,317,690, have at
`tempted to reduce the area by using multi-layer struc
`tures so that two separate elements are occupying the
`same surface area and no area is occupied by their inter
`connects. This approach, however, introduces capaci
`tance between the layers. Furthermore, these devices
`are usually built on a semiconductor substrate so that
`there is an unavoidable capacitance to the substrate. It
`should be noted that, in some situations, a high capaci
`tance is desired, such as in dynamic memory cells. If the
`capacitance per area of the memory cell can be in
`creased, the total area of the memory cell can be de
`creased, resulting in a high chip density. A further ad
`vantage of high capacitance for small area memory cells
`is the immunity to alpha particles. Thus, it is desirable to
`simultaneously have low capacitance and high capaci
`tance areas on the same integrated circuit.
`One technology that eliminates substrate capacitance
`is silicon on sapphire (SOS). In SOS, a layer of silicon is
`grown on top of an insulating sapphire substrate. As a
`result, substrate capacitance is negligible. However,
`SOS tends to require fairly large surface areas and mul
`ti-layer SOS devices are not common.
`A recent variant of SOS is silicon on insulator ($01),
`in which a silicon layer is formed on top of a layer of
`silicon dioxide. A description of SOI technology is
`contained in a technical article by A. Jastrzebski, ap
`pearing in the RCA Review, Vol. 44, June 1983 at
`pp.250-269 and entitled “Comparison of Different SOI
`Technologies: Assets and Liabilities”.
`
`25
`
`40
`
`45
`
`SUMMARY OF THE INVENTION
`Accordingly, it an object of this invention to provide
`for the fabrication of dense integrated circuits.
`It is a further object of this invention to provide for
`the fabrication of multi-layered devices on an integrated
`circuit chip.
`It is yet a further object of this invention to provide
`both high and low capacitance areas on the same inte
`grated circuit chip.
`The invention provides a buried conductive ?eld
`shield separated by a thin dielectric layer from the epi
`taxial region in an $01 integrated circuit. The epitaxial
`layer is grown upon a seed wafer and the thin dielectric
`layer and the conductive shield are deposited upon the
`epitaxial layer. A thick layer of quartz is then deposited
`
`55
`
`60
`
`65
`
`2
`and the quartz is mechanically bonded to a mechanical
`substrate. The original seed wafer'is then removed to
`expose the epitaxial layer for de?nition of the integrated
`circuit. The ?eld shield lies beneath the epitaxial layer
`and can be used for high capacitance elements, for bur
`ied wiring and for shielding the epitaxial layer against of
`migration of mobile ions from the quartz.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`FIGS. 1-3 illustrated a conventional method of pro
`ducing a silicon on insulator structure by anodic bond
`mg.
`FIG. 4 illustrates a die and its kerf region.
`FIG. 5 is a cross-sectional illustration of a ?rst step of
`one embodiment of the present invention.
`FIG. 6 illustrates alignment marks on a wafer.
`FIGS. 7-11 and 13 are cross-sectional illustrations of
`further steps in the ?rst embodiment, with FIG. 13
`being the ?nal structure.
`FIG. 12 is an enlarged cross-sectional view of an
`alignment mark.
`FIG. 14 is an enlarged cross-section of the alignment
`marks in a variation of the ?rst embodiment.
`FIGS. 15 and 16 are cross-sectional illustrations of
`steps in a second and preferred embodiment of the in
`vention.
`FIG. 17 is a cross-sectional illustration of a circuit
`that can be produced by means of the invention.
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`This invention provides a simple method for fabricat
`ing a buried ?eld shield in an integrated circuit. The
`buried ?eld shield is a thin conductive layer that lies
`below a semiconductor region in the integrated circuit
`chip and is separated from the semiconductor region by
`a thin dielectric layer. Such a buried ?eld shield can be
`used, for example, for memory storage cells and pro
`duces additional dielectric ?lm capacitance below the
`active devices without increasing the required surface
`area. The method of this invention relies upon a re
`cently developed technique for fabricating a buried
`insulating layer in a semiconductor material. This
`method is based on disclosures by Pomerantz in U.S.
`Pat. No. 3,595,719, and Antypas in U.S. Pat. No.
`3,959,045, and Kimura et al in a technical article entitled
`“Epitaxial Film Transfer Technique for Producing Sin
`gle Crystal Si Film on an Insulating Substrate” appear
`ing in Applied Physics Letters, Vol. 43, No. 3, Aug. 1,
`1983 at Pages 263-265. Additional references for the
`bonding of two wafers are U.S. Pat. Nos. 3,332,137,
`4,384,899 and 4,389,276, German Patentschrift b.
`593,559 and Japanese patent document No. 56-106430.
`A seed wafer 20, illustrated in FIG. 1, is prepared‘
`from a (100) silicon wafer 22. For sake of example, let
`the silicon wafer 22 have p+ doping.
`A silicon epitaxial layer 24 is grown on top of the
`silicon wafer 22. An insulating layer 26 is then formed
`on top of the epitaxial layer 24 by depositing a boron
`rich quartz. This quartz can be a borosilicate glass
`which matches the thermal expansion properties of
`silicon.
`A seed wafer 20 is then placed on top of a silicon
`substrate wafer 28 with the insulating layer 26 contact
`ing the substrate layer 28, as shown in FIG. 2. The two
`wafers 20 and 28 are then Mallory or anodically bonded
`by the method taught in the previously cited U.S. Pat.
`
`6
`
`

`
`25
`
`30
`
`20
`
`4,599,792
`4
`3
`could have been masked into individual regions for
`No. 3,595,719. This bonding forms a true hermetic seal
`further device de?nition utilizing the alignments marks
`between the two wafers 20 and 28. The formation and
`shown in FIG. 6.
`nature of this bonding seal are described by Wallis et al.
`A thin gate dielectric layer 58 is then grown or depos
`in an article entitled “Field Assisted Glass Metal Seal
`ing” appearing in the Journal of Applied Physics, Vol. 40,
`ited over the surface of the emitter layer 56, as shown in
`FIG. 8. The thickness of the dielectric layer 58 is some
`No. 10, 1969 at page 3946 and by Brooks et al. in an
`what arbitrary. A thin layer provides high capacitance
`article entitled “Low Temperature Electrostatic Silicon
`to Silicon Seals Using Sputtered Borosilicate Glass”
`but current technology sets a minimum thickness of 5
`appearing in the Journal of the Electrochemical Society,
`nm to prevent defects. Its composition is also somewhat
`arbitary but good adhesion to silicon is required. Di
`Vol. 119, No. 4, 1972 at page 545.
`electric layers 58 of SiO; are acceptable or a thin layer
`The bonded wafers 20 and 28 are then dip etched to
`of $102 for adhesion combined with a thicker Si3N4
`remove the region of the silicon wafer 22 and to pro
`layer may be used. Although the alignment marks of
`duce the structure illustrated in FIG. 3. This structure
`has a surface epitaxial layer 24 separated from the sili
`FIG. 6 are buried, they are apparent through the over~
`laying layers. Using these alignment marks, the gate
`con substrate 28 by the insulating layer 26. One of the
`dielectric layer 58 is patterned by standard photolitho
`purposes of this invention is to provide a method of
`graphic techniques to produce the structure shown in
`de?ning elements below the insulating layer 26 and to
`FIG. 8. The patterns on the dielectric layer 58 provide
`use parts of that layer 26 as ?eld barriers. It should be
`recognized that if elements had been de?ned in the
`openings 60 and 62 which will de?ne the contact to the
`silicon substrate 28 before the anodic bonding it would
`?eld shield to be grown later. It should be noted that
`FIG. 8 includes a larger portion of the area of the die 30
`be difficult to align to those elements because of the
`along the cross-sectional line VII—VII rather than
`featureless epitaxial surface of the structure of FIG. 3.
`along the shorter cross-sectional line V—V, which
`In integrated circuit fabrication, a wafer usually con
`concentrates on the kerf region 34. Although FIG. 8
`tains many dice. Each die is a complete integrated cir
`cuit and the circuit pattern is replicated among a large
`illustrates that the openings 60 and 62 are linear with the
`stop regions 48-52 de?ning the alignment marks, in fact,
`number of dice. A die 30 is shown in FIG. 4 on a wafer
`the openings 60 and 62 may be of any number and lo
`32. It is to be understood that the die is repeated in two
`cated anywhere within the area of the die 30 indepen
`dimensions in a rectangular close packed structure.
`dently of the location of the alignment marks within the
`' However, surrounding each die 30 is a kerf region 34.
`kerf region 34.
`When the wafer fabrication is completed, a mechanical
`In the embodiment illustrated in FIG. 8, the dielectric
`saw is applied to the kerf region 34 between the dice 30,
`layer 58 is a single thickness. However this layer 58 can
`‘ thereby separating the dice but also destroying the kerf
`be patterned to different thickness if high capacitances
`region 34. In one embodiment of the present invention,
`are desired for only a portion of the integrated circuit
`alignment marks are put in the kerf region 34 in order to
`while low capacitances are desired in other portions
`allow proper registration between different levels of the
`semiconductor fabrication. Alternatively, the alignment
`Where the ?eld shield is being used not as a capacitor
`marks can be put into peripheral regions of the wafer 32.
`but for wiring or for a shield against mobile ions.
`Providing for the alignment marks is one of the ?rst
`Then a layer of doped polysilicon or silicide or some
`other conductor is deposited on top of the gate dielec~
`' steps in one of the embodiments in this invention.
`tric layer 58 and is photo-lithographically de?ned, as
`Processing in a ?rst embodiment of the invention
`shown in FIG. 9, to form a ?eld shield 64. In one em
`‘ begins with a cleaned standard silicon wafer 36, shown
`bodiment, the ?eld shield 64 extends over the major
`in 'FIG. 5, with n—' or p— doping and an exposed (100)
`portion of the area of the die to provide a ?eld shield for
`face. The wafer 36 has a back-side protect 38 such as an
`nearly the entire integrated circuit. In other embodi
`oxide or Si3N4. A diffusion masking oxide is grown on
`the front surface of the wafer 36 and this oxide is opened
`ments, the ?eld shield 64 is used for buried wiring so
`that its patterning is complex.
`in a photoresist masking step to leave a series of small
`In the ?nal step of the preparation of the seed wafer,
`blocking oxide regions 40, 42 and 44. The pattern of the
`an insulating SOI (silicon on insulator) layer 66 is depos
`. oxide regions 40-44 provides the alignment marks, illus
`ited on top of the gate dielectric 58 and the ?eld shield
`trated in FIG. 6. The illustrated pattern is for ?ve marks
`64. The $01 insulating layer 66 should be a boron-rich
`but other patterns can be used. All the alignment marks
`glass which is deposited over the entire area either by
`should appear in the anticipated kerf region 34 or alter
`natively in the wafer periphery. Multiple sets of align
`sputtering or perhaps by chemical vapor deposition. An
`example of such a material is quartz. The sputtering
`ment marks are required for the integrated circuit but it
`procedure is described by Brooks et al in the previously
`is not necessary that they appear next to each die 30.
`cited article and the CVD process is described by Wer
`Then a p+ boron deposition and diffusion are made to
`provide a precision etch stop consisting of multiple stop
`ner Kern in a technical article entitled “Chemical
`Vapor Deposition of Inorganic Glass Films” appearing
`regions 46, 48, 50 and 52, shown in FIG. 7. The p+
`doping is 5 X lO19/cm3 or above. It is to be understood
`in Semiconductor International, March l982 at pp.
`89-103. Note that the thick quartz layer 66 tends to
`that the stop region 46 extends over a substantial area of
`the die 30.
`planarize the surface to a limited extent. The quartz
`should match the thermal expansion coef?cient of sili
`The front side blocking oxide regions 40-44 are then
`removed and an n-type epitaxial layer 54 is grown on
`con. This condition is satis?ed by a 17% boron content.
`Phosphorous rich glasses or a combination of phospho
`top of the silicon wafer 36 and its stop regions 46-52, as
`shown in FIG. 7.
`rous and boron can be used but a higher phosphorous
`content is required for the thermal matching. Sodium,
`A standard n+ emitter layer 56 is applied on top of
`65
`the epitaxial layer 54. The emitter layer 56 can be either
`such as is contained in PYREX, should not be used
`because of its degradation of dielectric-semiconductor
`blanket diffused or result from an ion implantation of
`the epitaxial layer 54. If desired, the emitter layer 56
`interfaces. The thickness of the quartz should be in the
`
`55
`
`7
`
`

`
`5
`range of 5-10 um to minimize capacitance to the sub
`strate. The back-side protect 38 is removed at this point.
`The resultant structure of FIG. 9 is the completed seed
`wafer that is used in $01 fabrication similarly to the
`seed wafer 20 of FIG. 1.
`The seed substrate of FIG. 9 is then anodically
`bonded to a mechanical substrate 68 as shown in FIG.
`10. The mechanical substrate 68 may be a wafer of
`crystalline silicon. The bonding voltages for a quartz
`layer of 7 pm thickness is in the range of 35-50 V. There
`are a number of important points to be explained for this
`bonding step. The ?eld shield 64 is at the same potential
`as the seed substrate 36 during bonding, thereby pre
`venting an electrostatic ?eld build-up across the thin
`insulating gate dielectric 58. The polysilicon or other
`material in the ?eld shield 64 provides a diffusion bar
`rier against any mobile ions which might otherwise
`migrate from the boron-rich quartz 66 into the thin
`dielectric region 58 beneath the ?eld shield 64. These
`mobile ions would cause problems with the subsequent
`operation of the fabricated devices in the area of the die.
`The ?eld shield 64 can be used, not for its electrical
`characteristics, but as a diffusion shield against mobile
`ions migrating from the quartz 66.
`The regions where the polysilicon ?eld shield does
`not protect the thin insulating gate layer 58 are nonethe
`less protected from inversion by the n+ stop layer 56 on
`top of the epitaxial layer 54.
`The non-planarity of the quartz surface, illustrated in
`FIG. 9, is not a major concern for the Mallory or anodic
`bonding. In fact, anodic bonding has been demonstrated
`on top of aluminum wiring patterns. Such successful
`bonding over de?ned features is described in a technical
`article by Roylance et al. entitled “A Batch-Fabricated
`Silicon Accelerometer” and appearing in IEEE Trans
`actions on Electron Devices, Vol. ED-26, No. 12, 1979 at
`page 1911 and in a technical article by Sander et al.,
`entitled “Monolithic Capacitive Pressure Sensor With
`Pulse-Period Output” and appearing in IEEE Transac
`tions on Electron Devices, Vol. ED-27, No. 5, 1980 at
`page 927. It has been suggested that the high energy
`density pulse at the initial phase of the anodic bonding
`increases the temperature at the local bonding site by as
`much as 560° C. which allows microscopic re?ow of
`the quartz around non-planar features. However, we
`45
`believe that the high local pressure causes a temporary
`decrease of the quartz viscosity around any protrusion
`of the bond interface. The re?ow process has been
`described in the previously cited articles by Wallis et al
`and Ramiller et al.
`The electrostatic ?eld and microscopic fusing occurs
`at the interface 70 between the quartz 66 and the me
`chanical substrate 68, thereby eliminating the possible
`problem mentioned by Barth in an article entitled “Sili
`con Sensors Meet Integrated Circuits” appearing in
`IEEE Spectrum, September 1981, at page 33. This prob
`lem concerns possible damage to existing semiconduc
`tor structures caused by electrostatic discharges in
`duced by the anodic bonding. The epitaxial layer 54 of
`the seed wafer is far removed from the bonding activity
`60
`at the interface 70. It is the mechanical substrate 68 that
`suffers the electrical surface property degradation dur
`ing bonding, not the silicon substrate 36 of the seed
`wafer or its epitaxial layer 54.
`The bonded wafer pair of FIG. 10 is then dip etched,
`perhaps using an anisotropic etch such as ethylene di
`amine pyrocatacol (EDP) to remove all the silicon in
`the seed wafer down to the p+ gate etch stop 46 in a
`
`4,599,792
`6
`process called etch-back. The use of EDP is described
`by Kurt Petersen in a technical article entitled “Silicon
`as a Mechanical Material” appearing in the IEEE Pro
`ceedings, Vol. 70, No. 5, May 1982 at pp. 420-457. It
`should be noted that the backside of the mechanical
`substrate needs to be protected by an oxide during the
`etch-back. For a quicker etch, a majority of the etching
`is performed with a caustic with the ?nal anisotropic
`etch done by EDP. The general principle of the EDP
`etch-back is that EDP readily etches silicon with dop
`ing concentrations below l0l9/cm3 but is ineffective at
`etching the p+ etch stop having a doping concentration
`above 5 X 1019/ cm3. The resultant structure is shown in
`FIG. 11 in which the wafers have been turned upside
`down from FIG. 10. However, in the vicinity of the
`alignment marks, the etch stop regions 46-52 are not
`continuous so that the etching in that region continues
`into the epitaxial layer 54 to form pyramids 70 and 72.
`The structure of one pyramid 70 is shown more accu
`rately and in more detail in FIG. 12. The sides of the
`pyramid 70 slope at an angle of 54.7° with respect to the
`surface because of the anisotropic nature of the etch.
`The etching, however, stops at the interface with the
`dielectric layer 58 with no additional undercutting if the
`wafer is left in the etch bath for more than the normal
`time. The pyramids 70 and 72 or the valleys between
`them provide alignment marks on an otherwise feature
`less surface of the p+ etch stop layer 46. The pyramids
`70 and 72 are necessarily aligned with whatever de?ni
`tion has been previously performed on the dielectric
`layer 58 or the ?eld shield 64.
`The p+ stop regions 46-52 are etched away with an
`echant such as hydro?ouric-nitric-acetic acid (HNA) in
`the proportions 1:3:8 that leaves the structure illustrated
`in FIG. 13. The etchant is chosen such that it etches
`only silicon above a certain dopant concentration so
`that the p+ gate etch stop 46 de?nes the precise limits of
`etching. This HNA etchant is described by Muraoka et
`al. in a chapter entitled “Controlled Preferential Etch
`ing Technology” appearing at page 327 in the book
`“Semiconductor Silicon 1973”, Electrochemical Soci
`ety Symposium Series (Princeton, N.J., 1973), edited by
`Huff et al. It is also described by Maggiore et al. in an
`article entitled “Thin Epitaxial dE/dx Detectors” ap
`pearing in IEEE Transactions on Nuclear Science, Vol.
`NS-24, No. 1, 1977 at page 104. If the epitaxial layer 54
`was applied as a blanket across the entire wafer, as
`shown in FIG. 7, the ?nal etching step produces under
`cutting of the pyramids 70 and 72 beneath the epitaxial
`layer 54, shown in FIG. 13. If, on the other hand, the
`deposition of the n+ layer 56 were masked around the
`alignment marks, as illustrated in FIG. 14, the alignment
`pit could be left free of the n+ layer 56. Then the HNA
`etch, intended for the etch stop layer 46, would never
`reach the n+ layer 56, thus preventing undercutting.
`This additional masking of the n+ layer 56 could also be
`used for buried device fabrication within the area of the
`die 30. Note that since the alignment marks appear in
`the kerf region 34, they would vanish upon dicing, thus
`not revealing how the alignment to the buried structure
`was accomplished.
`Transistors have been fabricated with the above ap
`proach but have been found to suffer unacceptable cur
`rent leakage. It has been determined that when the etch
`stop regions 46-52 have doping levels above
`3X l019/cm3, crystal slips form therein. These slip de
`fects propagate through the epitaxial layer 54 produc
`ing the observed degradation. Accordingly, a second
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`and preferred embodiment of the invention has been
`developed using a different etch-stop technique and
`using laser scribing for back-side alignment.
`Fabrication in the second embodiment begins with a
`heavily doped p+ seed substrate 80, shown in FIG. 15,
`on which is grown the n‘ epitaxial layer 54. There is no
`explicit etch-stop in this embodiment but the interface
`82 between the lightly doped n- epitaxial layer 54 and
`the heavily doped p+ seed substrate 80 provides the
`etch stopping characteristics to be described later. Then
`the n+ emitter layer 56 and the thin dielectric layer 58
`are grown just as in the ?rst embodiment.
`At this point, a laser is used to provide alignment
`marks on the dielectric layer 58. This procedure is de
`scribed in a patent application Ser. No. 620,644 ?led by
`one of the inventors, P. Cade on June 14, 1984 now US.
`Pat. No. 4,534,804 and entitled, “Laser Process for
`Forming Identically Positioned Alignment Marks on
`the Opposite Sides of a Semiconductor Wafer.” The
`advantage of the laser scribing techniques is that the
`20
`laser scribed marks propagate from the surface of the
`dielectric layer 58 through at least the epitaxial layer 54,
`thus providing back-to-front registry.
`The ?eld shield 64 and the boron-rich quartz 66 are
`likewise formed by similar procedures using the laser
`scribed alignment marks for any required de?nition
`including possible de?nition of the emitter layer 56. The
`mechanical substrate 68 of silicon is then anodically
`bonded to the quartz 66 by applying voltage to a volt
`age probe 84 with the seed substrate 80 grounded.
`The etch-back of the seed substrate 80 is performed
`with hydrofluoric-nitric-acetic acid (HNA) in the pro
`portions of 1:3:8. The etchant HNA is an isotropic etch
`and attacks heavily doped p+ or r1+ silicon. However, it
`does not appreciably attack silicon doped below the
`level of 1018/cm3. The etch stopping characteristics are
`improved by the p+/n junction at the interface 82. In
`order to prevent the etching of the silicon mechanical
`substrate 68 the backside of the mechanical substrate is
`protected with an oxide during the etch-back. How
`ever, the HNA etchant also attacks silicon oxide to
`some degree. Accordingly, the etching is divided into
`two steps. The ?rst major part of the etching is per
`formed with a caustic. The ?nal part of the etch is per
`formed with HNA to provide the precise etch-stopping
`characteristics. Whatever etching of the oxide protect
`of the mechanical substrate 68 occurs is insuf?cient to
`break through the oxide protect. The resultant structure
`after the etch-back is illustrated in FIG. 16. Not shown
`in this ?gure are the laser scribed registration marks
`which are visible at the top side of the epitaxial layer 54
`on an otherwise featureless surface. These etch marks
`are aligned with the ?eld shield 64 and whatever de?ni
`tion has been performed in the emitter layer 58. It is
`seen that structure of FIG. 16 closely resembles that of
`FIG. 13, except for the alignment marks.
`At this point, normal processing of the substrate of
`either FIGS. 13 or 16 proceeds upon the area of the die
`30 which has a smooth surface of the epitaxial layer 54
`and has a buried ?eld shield 64 underlying that die area.
`The pyramids 70 and 72 or the laser scribes are used as
`precision alignment marks to the buried structure of the
`dielectric layer 58 and the ?eld shield, not themselves
`visible. It is anticipated that the n+ region 56 is delin
`eated on top of the dielectric layer 58 so that devices,
`such as capacitors, can be fabricated using both the
`insulating layer 58 and the ?eld shield 64 as constituent
`elements.
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`An example of an integrated circuit built using the
`substrate of this invention is illustrated in FIG. 17. Two
`storage cells 90 and 92, chosen for illustrative purposes,
`each has a vertical transistor consisting of a diffused n+
`region 94, a diffused p region 96 and an epitaxial n re
`gion 98. The epitaxial n region 98 is part of the epitaxial
`layer 54 of the substrate of FIGS. 12 and 14. Underlying
`the epitaxial n region 98 is an n'*' layer 100 which is
`formed from the emitter step layer 56 of FIGS. 13 and
`16. A storage node with high capacitance results from
`the n+ layer 100, a thin dielectric layer 102 and a buried
`?eld shield 104. The dielectric layer 102 and the ?eld
`shield 104 are equivalent to the corresponding elements
`58 and 64 in FIGS. 13 and 16. The ?eld shield 104 is
`connected to the surface by ?eld shield reach-throughs
`or contacts 106 and 108. Support transistors 110 and 112
`are formed in an area of the die away from the ?eld
`shield 104. The transistor 110 consists of a diffused n+
`region 114, a diffused p region 116 and an n epitaxial
`layer 118. A planar contact is made to the n epitaxial
`layer 18 with an n+ layer 120 connected to the surface
`with a diffused n+ reach-through 122. The support
`transistors 110 and 112, the ?eld shield contacts 106 and
`108 and the storage cells are all isolated by dielectric
`trenches 124 extending from the surface to the dielectric
`layer 58. The required surface interconnections are not
`shown.
`Having thus described our invention, what we claim
`as new, and desire to secure by Letters Patent is:
`1. A method of fabricating a semiconductor structure,
`comprising the steps of:
`depositing an epitaxial semiconductor layer on a ?rst
`semiconductor substrate;
`forming and patterning a ?rst dielectric layer overly
`ing said epitaxial layer;
`forming a ?eld shield layer of a conductive'material
`on predetermined portions of said ?rst dielectric
`layer and on predetermined portions of said epitax
`ial layer;
`covering said ?eld shield layer and all exposed por
`tions of said ?rst dielectric layer and said epitaxial
`layer with a bonding material;
`bonding a second substrate to the side of said ?rst
`substrate covered with said bonding material,
`thereby forming a bonded structure; and
`removing said ?rst substrate from said bonded struc
`ture.
`2. A method of fabricating a semiconductor structure
`as recited in claim 1, further comprising the step of:
`forming on said ?rst substrate before the depositing of
`said epitaxial layer an etch stopping layer; and
`wherein said removing step is an etching step that
`does not substantially etch said etch stopping layer.
`3. A method of fabricating a semiconductor structure
`as recited in claim 2, wherein;
`said step of forming an etch stopping layer includes
`patterning said layer to exclude aligning areas; and
`said etching step is an anisotropic etching step.
`4. A method of fabricating a semiconductor structure,
`as recited in claim 1, wherein said removing step is an
`etching step that does not substantially etch said epitax
`ial layer.
`5. A method of fabricating a semiconductor structure v
`as recited in claim 4, wherein
`the conductivity type of said epitaxial layer is n-type
`and the doping concentration of said epitaxial layer
`is equal to or less than lO18/cm3; and
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`8. A method of fabricating a semiconductor structure
`as recited in claim 6,-further comprising the step of:
`forming on said epitaxial layer, before the forming
`and patterning of said dielectric layer, an emitter
`layer of a semiconductor of the same conductivity
`type as said epitaxial layer and having a doping
`concentration substantially larger than the doping
`concentration of said epitaxial layer; and
`wherein said patterning of said ?rst dielectric layer
`includes an etching step that does not substantially
`etch said emitter layer.
`9. A method of forming a semiconductor, as recited in
`claim 4, further comprising scribing alignment marks on
`said ?rst substrate before said bonding steps with a laser.
`10. A method of forming a semiconductor, as recited
`in claim 8,