United States Patent [19]
`Ralph et al.
`
`[11] Patent Number:
`[45] Date of Patent:
`
`4,700,185
`Oct. 13, 1987
`
`[54] REQUEST WITH RESPONSE MECHANISM
`AND METHOD FOR A LOCAL AREA
`NETWORK CONTROLLER
`
`[56]
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`[75] Inventors: Thomas J. Balph, Mesa; Bruce A.
`Loyer, Scottsdale, both of Ariz.
`
`[73] Assignee: Motorola Inc., Schaumburg, Ill.
`
`[21] Appl.No.: 686,352
`
`[22] Filed:
`
`Dec. 26, 1984
`
`[51] Int. cu .............................................. .. 1104.] 3/02
`[52] us. (:1. .......................... .. IMO/825.06; 340/8255;
`370/85
`[58] Field of Search ......... .. 340/825.06, 825.5, 825.51,
`340/825.52; 370/85, 94, 9O
`
`................ .. 340/8255
`4,536,874 8/1985 Stoffel et al.
`4,570,257 2/1986 Olson et al. .... ..
`.. 340/825.51
`4,590,468 5/1986 Sticglitz ...... ..
`340/825 5
`4,593,281 6/1986 Lare ................... ..
`340/8255
`4,593,282 6/1986 Acampora et al. .......... .. IMO/825.51‘
`Primary Examiner—Donald J. Yusko
`Attorney, Agent, or Firm-William J. Kubida; Dale E.
`Jepsen
`ABSTRACT
`[57]
`A request with response mechanism and method for a
`local area network controller utilizes an enable bit, a
`pointer, a counter and an interrupt to create the proper
`response to a received request with response data frame
`without the active aid of a host computer.
`
`12 Claims, 8 Drawing Figures
`
`1,
`
`MAIN SYSTEM BUS
`
`{
`
`(28
`
`LOCAL
`MEMORY
`
`(26
`
`MPU
`
`(24
`SYSTEM
`INTERFACE
`
`LOCAL
`BUS
`
`TOKEN BUS
`CONTROLLER
`
`(30
`PHYS 1 CAL
`LAY ER
`
`?
`
`NETWORK CABLE
`
`A
`
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`2K, ROCKSTAR
`Ex. 1022, p. 1 of 15
`
`

`
`- U. S. Patent Oct. 13,1987
`/0—\
`
`(/2
`
`Sheetl of6
`TO SYSTEM
`INTERFACE(24)
`
`(/4
`
`4,700,185
`
`BUS INTERFACE A
`
`v
`
`k
`
`I
`
`(/6
`
`E
`
`_
`
`DMA-
`
`A
`
`'
`
`MICRO-
`CONTROLLER ICONTROL‘
`BUS
`
`(/8
`
`ETERNAL
`BUS
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`
`HFO
`
`l
`
`—
`
`RECEIVE a
`TRANSMIT
`MACHINES
`
`REGISTER
`‘—’ FILE a AI_u
`
`IiE-l
`MAIN SYSTEM BUS
`
`1)
`
`(20
`
`‘
`
`(22
`
`To
`PHYSICAL
`LAYER (30)
`SERIAL
`INTERFACE
`
`Q
`
`l
`
`(24
`
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`INTERFAcE
`
`(28
`
`LOCAL
`MEMORY
`
`(26
`
`I
`
`MPU
`
`¢—
`
`LOCAL
`BUS ‘
`
`(/0
`TOKEN BUS
`CONTROLLER
`I
`
`(30
`I
`PHYSICAL
`LAYER
`I
`
`Y
`
`NETWORK CABLE
`IIG-S
`
`,4
`
`IPR2016-00726
`ACTIVISION, EA, TAKE-TWO,
`2K, ROCKSTAR
`Ex. 1022, p. 2 of 15
`
`

`
`‘U. S. Patent Oct. 13,1987
`
`Sheet2 Of6
`
`4,700,185
`
`SYSTEM
`INTERFACE
`
`vcc
`
`Vcc
`
`BUS
`ARBITRATION
`CONTROL
`
`ERR
`?g
`BGACK<——
`
`INTERRUPT
`CONTROL
`
`FRO‘
`‘Kc-Ra
`
`252mm
`CONTROL
`
`?-Q
`Elsi?»
`LDS(DS)‘—‘
`Rf!“
`ASH
`DTACKH
`
`PHYSICAL LAYER
`SERIAL INTERFACE
`
`—+TxOATA SMTXD \
`—-—>TXSYMO,-RESET
`
`EXCEPTION
`CONDITIONS
`
`BUS
`5501"’
`CONTROLLER ~—TXCLK
`
`53;?“
`REQUEST
`CHANNEL
`
`\
`
`PHYSICAL
`<_-RXDATA;SMRXD
`<_ RXSYMO,-RSACK DATA
`>INOICATION
`<--RXSYMI ‘.JABINH CHANNEL
`
`-— RXCLK
`
`—->MAC/S_?
`__
`SMREQ
`
`MODE
`CONTROL
`
`FUNCTION
`CODES
`
`FCI<--
`F¢2__
`
`FC3<__
`
`ADDRESS
`BUS
`
`A3_3| C
`
`Al ""
`A2“
`
`DATA BUS
`
`DO-ISO
`
`‘- MCLK
`
`I
`I
`GND GND \
`/0
`
`I15 -5
`
`IPR2016-00726
`ACTIVISION, EA, TAKE-TWO,
`2K, ROCKSTAR
`Ex. 1022, p. 3 of 15
`
`

`
`U. S. Patent Oct. 13,1987
`
`Sheet3 of6
`
`4,700,185
`
`i
`
`SYSTEM OR LOCAL BUS
`
`7;
`
`I
`
`INTERFACE MACHINE
`(IFM)
`
`ACcEss CoNTRoL
`MACHINE
`IACMI
`
`MAC
`LAYER
`
`l0
`
`‘
`
`K "
`
`[I
`
`RECEIVE |
`MACHINE |
`IRxM) I
`I
`
`I
`
`I
`
`ITRANSMIT
`FCS | MACHINE
`|
`(TXM)
`l
`
`PHYSICAL
`INTERFACE
`
`PHYsICAL
`LAYER
`
`‘
`
`;’
`
`TRANS.
`JABBER
`INHIBIT
`
`;
`
`\
`
`'
`
`TOKEN BUS CoAx
`
`35-4
`
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`2K, ROCKSTAR
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`
`

`
`U. S. Patent Oct. 13,1987
`
`Sheet 4 of 6
`
`4,700,185
`
`. @
`
`GET NEXT FD
`
`'
`
`I
`
`0 NORMAL
`' N
`TRANSMISSION
`
`YES
`
`TRANSMIT
`FRAME »
`
`I
`
`FRAME
`RECEIVED
`
`TIMEOUT
`DECREMENT
`RETRY COUNT
`
`UPDATE TX
`IR FD PTR
`
`NO
`
`UPDATE TX
`FD STATUS
`W/ SUCCESS
`CONFIRMATION
`
`YES
`
`‘
`
`‘
`
`UPDATE TX
`FD STATUS
`w/ FAILURE
`CONFIRMATION
`
`I NEXT FRAME )
`
`13:5- 5!).
`
`RECEIVE
`Rx FRAME
`
`N0 NORMAL
`RECEPTION
`
`NO NORMAL
`RECEPTION
`
`YES
`
`YES
`
`PULL
`INTERRUPT
`
`I
`USE POINTER
`AND COUNT TO
`TRANSMIT
`RESPONSE
`
`:Ffrs-SB
`
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`ACTIVISION, EA, TAKE-TWO,
`2K, ROCKSTAR
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`

`
`U. S. Patent Oct. 13,1987
`
`SheetS 01‘6
`
`4,700,185
`
`TBC READY I
`
`I
`RECEIVE
`RX FRAME
`
`No
`
`NORMAL RECEPTION
`
`NO
`
`NORMAL RECEPTION
`
`I
`LOAD RWR FD
`PTR w/ RX FD
`
`ASSERT TE
`
`GET
`COMMAND
`
`ANY BUS
`ACTIVITY
`(NON-SILENCE)
`
`YES
`
`‘YES
`
`GENERATE MAC
`CONTROL BYTE
`I
`I RXSA —> TXDA I
`
`I
`| RXDA —>TXSA
`
`APPEND DATA
`(USE IR 80- PTRI',
`IF BYTE COUNT
`=O. NO DATA
`
`UPDATE RX
`FD STATUS
`W/ ACK. IND
`
`I
`
`<
`
`TBC READY ’
`lira-5C
`
`IPR2016-00726
`ACTIVISION, EA, TAKE-TWO,
`2K, ROCKSTAR
`Ex. 1022, p. 6 of 15
`
`

`
`U. S. Patent Oct. 13,1937
`
`Sheet6 of6
`
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`|PR2016-00726
`ACTIVISIO
`
`N, EA, TAKE-TWO,
`2K, ROCKSTAR
`Ex 1022, p 7 of15
`
`IPR2016-00726
`ACTIVISION, EA, TAKE-TWO,
`2K, ROCKSTAR
`Ex. 1022, p. 7 of 15
`
`
`
`

`
`1
`
`4,700,185
`
`REQUEST WITH RESPONSE MECHANISM AND
`METHOD FOR A LOCAL AREA NETWORK
`CONTROLLER
`
`2
`multiple request with response frames and to acknowl
`edge such frames with a response frame.
`It is still further an object of the present invention to
`provide an improved request with response mechanism
`and method for a local area network controller which
`allows a user ?exibility as to the trade-off of cost, speed
`and performance.
`It is still further an object of the present invention to
`provide an improved request with response mechanism
`and method for local area network controller which
`allows a user to choose an appropriate response format.
`The foregoing and other objects are achieved in the
`present invention wherein there is provided a token bus
`local area network including a plurality of stations
`thereon incorporating a request with response mecha
`nism which comprises a transmitting station for sending
`a request with response data frame to a predetermined
`receiving station on the network. The predetermined
`receiving station responds to the transmitting station
`with a response data frame in response thereto if the
`request with response mechanism thereof is enabled.
`Also provided is a request with response mechanism
`and method for communicating between a plurality of
`stations on a local area network thereof which com
`prises a transmitting station for transmitting to a prede
`termined receiving station a transmit frame having a
`request with response data frame to a predetermined
`receiving station. The predetermined receiving station
`receives the transmit frame which is tested for the re
`quest with response data frame. The receiving station
`thereafter determines if a request with response mecha
`nism thereat is enabled and veri?es a valid bit having
`?rst and second conditions thereof. A pointer indicates
`where a response data frame to the request with re
`sponse data frame is located if the valid bit is in the ?rst
`condition thereof and a counter is utilized to determine
`the length of the response data frame at which time the
`response data frame may be transmitted to the transmit
`ting station. If the valid bit is in the second condition
`thereof, an interrupt is generated and the receiving
`station waits for the response frame to be generated.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`The foregoing and other features and objects of the
`present invention and the manner of attaining them will
`become more apparent and the invention itself will be
`best understood by reference to the following descrip
`tion of an embodiment of the present invention taken in
`conjunction with the accompanying drawings, wherein:
`FIG. 1 is a simpli?ed block diagram of a token bus
`controller for implementing the request with response
`mechanism and method of the present invention;
`FIG. 2 illustrates the input and output signals of the
`token bus controller of FIG. 1;
`FIG53 illustrates a block diagram of a token bus local
`area network node utilizing the token bus controller of
`FIGS. 1 and 2;
`'
`FIG. 4 illustrates a functional model of the token bus
`local area network node of FIG. 3;
`FIG. 5A is a simpli?ed ?ow chart for a request with
`response transmission in accordance with the present
`invention which may be initiated if a request with re
`sponse frame descriptor is encountered;
`FIG. 5B is a ?ow chart of a request with response
`reception in accordance with the request with response
`mechanism and method of the present invention;
`
`25
`
`BACKGROUND OF THE INVENTION
`The present invention relates, in general, to the ?eld
`of request with response mechanisms and methods for
`local area network controllers. More particularly, the
`present invention relates to a request with response
`mechanism and method which may be used in local area
`network (LAN) communications by a large scale inte
`gration (LSI) token bus protocol handler to create the
`proper response to a message requiring an answer (re
`quest with response) without the active aid of a host
`computer, or with minimum aid from the host.
`Local area networks are built to transfer data be
`tween several stations or nodes. In order to prevent
`coniusion on the network, protocols are used to deter
`mine how and when each station may transmit. In a
`token passing LAN, the single station who possesses the
`imaginary token is the only station which can transmit
`at that time. If another station wants to transmit, it must
`wait until the token is passed to it. Since the token is
`passed to each station in turn, every station gets an
`opportunity to transmit. There are some situations,
`however, especially in real-time control, when the
`transmitting station needs an immediate reply or re
`sponse from the receiving station. The response may be
`just a simple acknowledge (ACK) that the message was
`received correctly (NAK. if it was not) or a data mes
`sage the content of which is dependent upon the re—
`quest. This response transmission is consistent with a
`token passing protocol because the holder of the token
`(who is transmitting the request for a response) is dele
`gating to the receiving station the right to transmit the
`response.
`The mechanism utilized to _ generate the response
`must be a trade-off between cost, time, and perfor
`mance. The amount of time taken to create the response
`must be minimized because no other traf?c (data) can be
`transmitted during this time. Therefore, the longer it
`takes to create the response, the more wasted band
`width on a network there is. Moreover, the type of
`response is also important. The response can be a simple
`45
`acknowledgement (response with no data), a preset
`message, or the creation of a unique message for every
`request. Every LAN will have different requirements
`depending on their own goals. Moreover, in some net
`works the response mechanism may not be needed at
`all, so the ability to disable a request with response
`mechanism would be highly desirable. In still other
`instances, appropriate responses might include a very
`fast response with no data, a very fast response with
`?xed data, a fast hardware derived response or a rela
`tively slow software derived response.
`It is therefore an object of the present invention to
`provide an improved request with response mechanism
`and method for a local area network controller.
`It is further an object of the present invention to
`provide an improved request with response mechanism
`and method for a local area network controller which
`allows an LAN controller to create a response without
`the aid of the host computer.
`It is still further an object of the present invention to
`provide an improved request with response mechanism
`and method for a local area network controller which
`allows a media access control (MAC) layer to send
`
`35
`
`40
`
`50
`
`55
`
`60
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`65
`
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`2K, ROCKSTAR
`Ex. 1022, p. 8 of 15
`
`

`
`3
`FIG. 5C is an alternative flow chart illustrating a
`request with response reception in accordance with the
`request with response mechanism and method of the
`present invention; and
`FIG. 6 illustrates a token bus controller memory
`structure for use in implementing the request with re
`sponse mechanism and method of the present invention.
`
`25
`
`35
`
`4,700,185
`4
`local resource/local bus architecture provides the best
`environment to meet these performance criteria.
`The TBC 10 bus interface 14 supports many varia
`tions on system architecture including non-MC68000
`types with different byte ordering and control signals.
`Also, TBC 10 can directly interface to cost effective
`MC68020 based applications via the 32-bit address
`space.
`FIG. 2 shows the input and output signals for Token
`Bus Controller 10 in an integrated circuit embodiment.
`While system interface 24 is shown providing the com
`plete control capability necessary to be both a bus mas
`ter and slave (peripheral), such control may also be
`provided by an interface between MPU 26 and TBC 10
`(not shown). For DMA operation a full 32-bit address
`space and a 16-bit data path are provided. In addition to
`data transfer control signals, bus request/ grant, bus
`exception condition, and function codes are provided.
`Also, as a peripheral function several registers may be
`written and read, and TBC 10 can request interrupts
`and provide an 8-bit interrupt vector.
`Protocol Implementation - TBC 10 implements the
`sublayer of the IEEE 802.4 speci?cation. It provides
`the required services of LLC-MAC Interface, Station
`Management-MAC Interface, and also supports Physi
`cal Layer Interface and Management. The device con
`tains the functionality of the MAC Interface Machine
`(IFM), Access Control Machine (ACM), Receive Ma
`chine (RXM) and Transmit Machine (TXM) shown in
`FIG. 4.
`System Interface - To support the requirements of the
`IEEE 802.4 protocol, TBC 10 provides three communi
`cation means via system interface 24 as shown in FIG.
`2. These include:
`1. A command channel - the system or host processor
`requests services from TBC 10 via the command chan
`nel. An 8-bit TBC Instruction Register (IR) is written
`upon to request a command. Activities such as chip
`initialization, mode set, LLC service, and Station Man
`agement services are activated by these commands.
`2. Shared Memory tables and buffers - Memory struc
`tures used for communication between the system pro
`cessor and TBC 10 include an initialization table, free
`frame and buffer descriptors lists, receive frame and
`buffer descriptors, receive data buffers, transmit rame
`and buffer descriptors lists, and transmit data buffers.
`The shared memory structures are used primarily for
`normal message flow and for the host processor to mon
`itor TBC 10 activity.
`3. Interrupt request - TBC 10 can generate interrupt
`requests and respond to an interrupt acknowledge bus
`cycle by providing an 8-bit vector. Interrupts are gener
`ated as the result of a conformation or indication of a
`service, or an error condition.
`To facilitate the communications techniques, TBC 10
`provides both bus master and slave capabilities.
`Bus Master Mode (DMA) - The bus master mode is
`used to DMA required pointers and data into TBC 10
`and to pass updated pointers, status, and data to mem
`ory. TBC 10 provides a full 32-bit linear address space
`allowing it to DMA directly into the entire space of any
`microprocessor including the MC6802O available from
`Motorola, Inc. assignee of the present invention. The
`parallel interface may be based on the MC68010 al
`though it can be programmed to other types of proces
`sor interfaces (byte ordering and control line functional
`ity). With speci?c reference to FIG. 2, the bus master
`mode involves the following signal lines:
`
`40
`
`DESCRIPTION OF A PREFERRED
`EMBODIMENT
`With reference to FIG. 1, a simpli?ed block diagram
`of a token bus controller 10 in accordance with the
`present invention is shown. Token Bus Controller
`(TBC) 10 may be conveniently furnished as a VLSI,
`high performance device that provides the Media Ac
`cess Control (MAC) function for an IEEE 802.4 Local
`Area Network (LAN) node as described in IEEE Draft
`Standard 802.4 Rev. F, July, 1984 the contents of which
`is hereby speci?cally incorporated by reference. When
`20
`interfaced with a suitable Physical Layer 30 function,
`TBC 10 can support both baseband and broadband
`networks at 1, 5, and 10 Megabits/second. It fully im
`plements the sublayer of the IEEE 802.4 Token Bus
`Access Method standard plus real time extensions. In
`addition, network monitoring and diagnostics aids are
`provided. When designed using HCMOS technology,
`proprietary to Motorola, Inc. assignee of the present
`invention, TBC 10 provides low power as well as high
`performance with serial data rates up to 10 Mb/s. The
`‘device is con?gured to operate primarily in a local bus
`environment with supporting local memory 28 and
`microprocessor (MPU) 26. 1t can, however, be used
`easily in more cost-effective systems because it provides
`full Bus Master Mode (DMA) capability including a
`32-bit address space and intelligent systems interface.
`TBC 10 is part of a multichip implementation of an
`I IEEE 802.4 Token Bus LAN node. The simple model
`shown in FIG. 4 describes the functionality contained
`on the device and shows TBC l0 and physical layer 30.
`The 802.4 standard speci?es three different Physical
`Layer/Media types (a Phase continuous Frequently
`Shift Keyed (FSK) carrier band,(a phase coherent FSK
`carrier band, and a multilevel duobinary Amplitude
`Modulation/Phase Shift Keyed (AM/PSK) broad
`band). TBC 10 through its serial interface and function
`ality is designed to easily tie to any of these media.
`Acting as both a bus master and a peripheral device,
`TBC 10 is intended primarily to be used in a closely
`coupled con?guration with a local processor and local
`resources (mainly local RAM), an example is shown in
`FIG. 3. The local resources provide:
`1. Protocol control - Writing to TBC 10 as a periph
`eral, the local processor (MPU 26) initiates TBC 10 and
`sends command information. MPU 26 also manages
`message information through a linked buffer manage
`ment scheme, and responds to interrupt requests for
`error handling and protocol command response. MPU
`26 can also provide the LLC service to higher LAN
`communication levels.
`60
`2. Local memory - The local memory 28 (RAM)
`provides packet buffering, and serves as a communica
`tions media between MPU 26 and TBC 10, and is re
`quired for TBC 10 private parameter storage.
`3. Fast bus cycle and response times - For high serial
`data rates (10 Mb/s) and minimum worst case frame
`spacing of 2.4 microseconds, TBC 10 requires a bus
`system interface 24 with high performance capability. A
`
`45
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`2K, ROCKSTAR
`Ex. 1022, p. 9 of 15
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`

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`5
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`15
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`4,700,185
`5
`1. Bus Request, Bus Grant, Bus Grant Acknowledge
`(BR W, BGACK) - These 3 lines are used to request
`and hold use of the system during DMA activity.
`2. Address Lines - The address lines provide a full
`32-bit linear address space for DMA 16. The use of the
`address lines are in two categories:
`(a) A3-A3l are used only’for master bus cycles.
`(b) Al—A2 and optionally (A0) are bidirectional used
`both for master bus cycles and for selecting internal
`registers during chip slave cycles.
`3. Data Lines (DO-D7, D8-D15) - 16 lines are pro
`vided for data transfer.
`4. Function Codes (FCO-FC3) - These signals drive
`the corresponding function code lines for an MC8020
`type bus. Each DMA channel has a separate 4-bit func
`tion code register Therefore, during a bus master cycle
`controlled by a given DMA channel, the associated
`function code is asserted to the bus. In this manner, the
`system controller can direct the cycles to be classi?ed as
`user or supervisory, and data or program access. The
`function codes are included as part of the various point~
`ers.
`5. Bus Control Signals (UDS (A0), m (DS), R/W,
`‘AS, DTACK) - TBC 10 provides an asynchronous data
`25
`transfer bus cycle. Although they may be an MC80l0
`type control interface, the control lines (as well as byte
`ordering) are multifunctional and can be programmed
`at initialization. F55 and m are data strobes, R/W is
`a read/write indication signal, E is address strobe, and
`DTACK is data transfer acknowledge.
`The TBC 10 bus interface is asynchronous with E,
`L—DS (DS), m (A0), and DTACK controlling timing.
`The asynchronous nature of bus interface 14 allows
`adjustment of the bus cycle time by DTACK. Bus cycle
`times are a minimum of 4 chip clock cycles and increase
`in increments of clock cycles.
`Performance Factors - The worst case performance
`requirement demanded of TBC 10 is the 10 Mb/s data
`rate of the Serial Interface. With a 16-bit parallel trans
`fer capability, the l0 Mb/s serial translates to a require
`ment for a system bus data transfer cycle averaging
`every 1.6 microseconds. If TBC 10 is used in an envi
`ronment where it must share its system bus with another
`processor(s), the system design must provide suf?cient
`performance to meet the needs of TBC 10 and theyother
`processor.
`The characteristics of TBC 10 that affect system
`performance are:
`l. A 40-byte FIFO 18 is provided for message buffer
`lng.
`2. The minimum read or write cycle time for TBC 10
`is 4 chip clock cycles (400 ns minimum with a 10 MHz
`chip clock). This implies a “no wait-state” memory and
`suitable memory cycle time. Bus cycle times increase in
`increments of the chip clock cycle times (100 nanosec
`onds for 10 MHz).
`3. A DMA 16 request is initiated after 8 bytes in
`FIFO 18 have been ?lled. This implies 25.6 microsec
`onds latency time (32 bytes>< 8 bits/byteX0.l mi
`croseconds/bit) before TBC 10 must be given the bus.
`The local resources system con?guration provides
`the most effective architecture. As an example, if local
`memory 28 cycle time is 500 nanoseconds and average
`arbitration time is 500 nanoseconds, TBC 10 consumes a
`maximum of approximately 3.‘, of bus availability.
`Bus Slave Mode (Peripheral) - The bus slave mode is
`used to write initialization information and commands
`
`6
`to TBC 10 and to write the interrupt vector. The bus
`slave mode involves the following signal lines:
`1. Address Lines (Al-A2) - These lines are used to
`select internal registers.
`2. Data Lines (DO-D7, D8-D15) - 16 lines are used
`for data transfer.
`3. Control Lines (CS, U—DS (A0), ‘13% (DS), R/W,
`XS DTACK) - These control lines provide asynchro
`nous data transfer bus cycle. CS is the chip select used to
`indicate that TBC 10 is being accessed. UDS and IDS
`are the data strobes, R/W indicates a read or write
`cycle, and DTACK is returned by TBC 10 to indicate
`cycle termination.
`The primary means of communication between the
`host processor and TBC 10 is through shared memory
`structures. However, the slave mode allows the TBC 10
`initialization vector to be programmable (the memory
`tables then can be located anywhere in memory), com
`mands to be sent directly to TBC 10 causing more
`timely response, and the interrupt vector to be pro
`grammed.
`Interrupt Request - TBC 10 can generate an interrupt
`request from several sources, however, only one inter~
`rupt request line is asserted. When the interrupt request
`is acknowledged, an 8-bit vector is provided in which
`the upper 6 bits are driven from the Interrupt Vector
`Register (IV) and the lowest 2 bits are dependent on the
`interrupt request source.
`-
`The associated signal l_i_rle_s are:
`l. Interrupt Request (IRQ) - This output is asserted
`by TBC 10 to request an interrupt acknowledge.
`2. Interrupt Acknowledge (IACK) - This input is
`asserted to signal an interrupt acknowledge cycle. TBC
`10 responds by reading the interrupt vector and puts it
`on the data bus.
`3. Data Lines (DO-D7) - The 8-bit interrupt vector is
`read from these data lines.
`4. Control Lines (YD-S (DS), R/W, DTACK) - These
`additional control lines are used during the interrupt
`@nowledge cycle. R/W indicates a read bus cycle.
`LDS is asserted to indicate the data transfer is on the
`lower 8-bits of the data bus. TBC 10 asserts DTACK
`wben the vector is available on the data bus.
`The interrupt vector is programmable by the host
`system. The most signi?cant 6-bits of the vector are
`supplied by the IV register which is user programmed.
`The lowest 2-bits of the vector are a prioritized code
`from on TBC 10. If the vector is not initialized by the
`user, TBC 10 uses a default value of 15 (decimal).
`Physical Layer Serial Interface - TBC 10 connects to
`an IEEE 802.4 physical layer 30 function that contains
`circuitry for transmission of data units across the physi
`cal medium and also for communicating those data units
`with the MAC layer (TBC 10). The physical layer 30
`interface provides means for transferring requests for
`data unit transmission, indicating data unit reception,
`and station management of physical layer 30. Each
`Physical Service Data Unit is a symbol of a serial data
`transmission and they are delivered in the same order in
`which they are submitted to physical layer 30 by the
`MAC.
`Physical layer 30 produces within itself the timing
`signals for each symbol (Physical Data Unit). Physical
`layer 30 accepts a limited set of service primitives from
`the MAC which de?nes the transmitted signal at each
`timing interval (clock period), and in turn, sends to the
`MAC one of another set of clocked primitives based on
`reception of information from the medium.
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`ACTIVISION, EA, TAKE-TWO,
`2K, ROCKSTAR
`Ex. 1022, p. 10 of 15
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`The physical layer 30 interface shown in FIG. 2 the
`is, not receiving or transmitting information. The host
`consists of three functions:
`processor can then request required management func
`1. Physical Data Request Channel - When pro
`tions.
`grammed for MAC operation, this channel provides
`A signal is provided called MAC/W that is set low
`encoded requests (atomic symbols) for data unit trans
`to indicate station management functionality of the
`mission. The encoded symbols (lines TXSYMO,
`request channel. In this condition, the physical data
`TXSYMI, TXDATA) are synchronized to the physical
`symbol lines (TXSYMO, TXSYMI, TXDATA) serve a
`layer 30 generated TX clock.
`different function. These lines are used to implement the
`2. Physical Data Indication Channel - When pro
`required station management primitives. Requests to
`grammed for MAC operation, this channel provides
`physical layer 30 in this mode are synchronized to the
`encoded indications of data unit reception. The encoded
`TX clock.
`symbols(lines RXSYMO, RXSYMl, RXDATA) are
`A second signal is provided called SMREQ that is set
`synchronized to the physical layer 30 generated RX
`low by physical layer 30 (modem) to indicate that it is in
`clock.
`the station management mode. The SMREQ can be set
`3. Physical Layer Management - TBC 10 provides
`low in response to TBC 10 being put in SM mode or by
`the ability to pass a Station Management request to
`the physical layer having a need for SM service. An
`physical layer 30. A signal line is provided (MAC/W)
`example oi the latter case is the jabber inhibit timer
`which indicates when a station management mode is
`shown in FIG. 4 which may time-out indicating a trans
`envoked. The encoded symbol lines provide a dual
`mitter fault. When the SMREQ =low, the indication
`functionality where management requests and indica
`channel symbol lines (RXSMO, RXSYMl, RXDATA)
`tions are passed between TBC 10 and physical layer 30.
`Also, a request line (SMREQ) is provided for physical
`serve as SM inputs. These lines are used to implement
`the station management primitives. Con?rmations from
`layer 30 to indicate a need for service, and also indicates
`when the physical layer 30 is in the station management
`physical layer 30 are synchronized to the RX clock.
`Individual signal lines are used to provide four manda
`mode.
`__
`tory station management primitives:
`l. PHY13 RESET Request - The PHY_RESET out
`put (reset) of TBC 10 can be set and cleared via the
`command channel.
`2. PHY_RESET Con?rmation - the PHY_RESET
`CONF input (RSACK) sent to TBC 10 in response to
`the PHY_RESET command (output). This status is
`passed to the Station Management via TBC 10.
`3. PHY_MODE SELECT Request - TBC 10 pro
`vides an output that is a transmitter output inhibit
`(TXDIS). Commands to TBC 10 can set or clear this
`output.
`4. PHY_MODE SELECT Con?rmation - An input
`to TBC 10 indicates the status of the transmit output
`(JABINH). If the transmitter has been disabled in re
`sponse to a request (TXDIS) or the watchdog timer
`timing out, this line is asserted and the status is passed to
`station management by TBC 10.
`In addition, a data transmit line (SMTXD) and a data
`receive line (SMRXD) are used to request/indicate
`service primitives not speci?cally done by the above
`lines. The SMTXD and SMRXD are simple transmit
`and receive channels in which data is transferred in
`octets and synchronously clocked by the appropriate
`clock. The advantages of providing these channels is
`the ability to expand the station management service for
`more “intelligent” physical layers 30 and still have a
`simple interface for a minimum functionality physical
`layer 30.
`Memory Structures and Buffer Management - The
`IEEE 802.4 protocol requires 4 levels of message prior
`ity. To support 4 transmission queues, 4 receive queues,
`and other functions, TBC 10 uses a powerful, ?exible
`memory and buffer management structure. TBC 10
`supports minimal on-board registers and primary com
`munication between the host processor and TBC 10 is
`through common RAM. The host accessible registers
`include:
`1. IR - an 8-bit Instruction Register used to send TBC
`l0 commands (instructions).
`2. IV - an 8-bit Interrupt Vector register used to store
`the interrupt vector for an IACK cycle.
`
`1. ZERO——The logical data state zero
`2. ONE—The logical data state one
`3. NON-DATA—-Delimiter ?ag, always sent in pairs
`4. PAD-IDLE—One symbol of preamble/interframe
`:. idle
`5. SlLENCE—Transmit silence
`The symbol timing will be such that the indication
`lines will be valid for a speci?ed time before the rising
`clock edge of TXCLK.
`Physical Data Indication Channel (SMREQ=high;
`MAC Mode) - The class of service primitives associated
`with the indication channel is:
`< symbol > The
`PHY_DATA indication
`PHY_DATA indication primitives are synchronous to
`the RXCLK (receive clock) supplied by the physical
`layer. The PHY_DATA indication <symbol> set is:
`l. ZERO~The logical data state zero
`2. ONE—The logical data state one '
`3. NON-DATA—Delimiter flag, always present in
`pairs
`4. SlLENCE—Received silence or pseudo-silence
`5. BAD-SIGNAL-Illegal symbol or untranslatable
`sequence
`The symbol encoding is shown in FIG. 6B. The symbol
`timing will be such that indication lines will be valid for
`a speci?ed timing before the rising edge of RXC.
`Physical Layer 30 Management - Station manage
`ment is not a function of the MAC sublayer of the
`Token Bus node. However, TBC 10 provides a station
`management-physical layer 30 interface to facilitate
`control of physical layer 30. The SM-PL interface uses
`65
`a request/ con?rmation model similar to the other IEEE
`802.4 interfaces. To perform the station management
`functions TBC 10 is ?rst put into an “offline” mode, that
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`Physical Data Request Channel (MAC/SM=high,
`MAC Mode) .
`.
`. The class of service primitives associ
`ated with the request channel is:
`
`PHY_DATA request <symbol>
`
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`The PHY_DATA request primitives are synchro
`. nized to the TXCLK (transmit clock) supplied by phys
`ical layer 30. The PHY_DATA request <symbol > set
`is:
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`ACTIVISION, EA, TAKE-TWO,
`2K, ROCKSTAR
`Ex. 1022, p. 11 of 15
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`3. DIR - a 32-bit Data In Register used as a data input
`port to receive initialization pointers and data.
`The RAM based structures that TBC 10 uses include:
`1. TBC Private Area - used by TBC 10 to store inter
`nal variables and statistical information.
`2. Initialization Table - used by the host ,to pass initial
`ization parameters and pointers to TBC 10. Also, TBC
`10 maintains status indicator