Paper No. __
`Filed: March 17, 2016
`
`
`
`
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`____________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`____________________
`
`SAMSUNG ELECTRONICS CO., LTD.;
`MICRON TECHNOLOGY, INC.; and
`SK HYNIX, INC.
`Petitioner
`
`v.
`
`ELM 3DS INNOVATIONS, LLC
`Patent Owner
`
`____________________
`
`Patent No. 8,907,499
`____________________
`
`PETITION FOR INTER PARTES REVIEW
`OF CLAIMS 1 AND 49 OF U.S. PATENT NO. 8,907,499
`
`
`
`

`
`Petition for Inter Partes Review
`Patent No. 8,907,499
`
`TABLE OF CONTENTS
`
`I.
`
`II.
`
`III.
`
`IV.
`
`V.
`
`VI.
`
`INTRODUCTION .............................................................................................................. 1
`
`MANDATORY NOTICES UNDER 37 C.F.R. § 42.8 ...................................................... 1
`
`PAYMENT OF FEES UNDER 37 C.F.R. § 42.15(a) ........................................................ 3
`
`GROUNDS FOR STANDING ........................................................................................... 3
`
`PRECISE RELIEF REQUESTED ...................................................................................... 3
`
`THE ’499 PATENT ............................................................................................................ 5
`
`A.
`
`B.
`
`C.
`
`Technical Background ............................................................................................ 5
`
`Overview of the ’499 Patent ................................................................................... 6
`
`Level of Ordinary Skill in the Art ........................................................................... 7
`
`VII. CLAIM CONSTRUCTION ................................................................................................ 7
`
`A.
`
`B.
`
`“substantially flexible monocrystalline semiconductor layer” (Claim 1) ............... 8
`
`“substantially flexible structure” (claims 1, 49) ................................................... 12
`
`VIII. DETAILED EXPLANATION OF GROUNDS UNDER THE BROADEST
`REASONABLE CONSTRUCTIONS .............................................................................. 14
`
`A.
`
`Overview of the Prior Art References .................................................................. 14
`
`1.
`
`2.
`
`3.
`
`4.
`
`5.
`
`6.
`
`U.S. Patent No. 5,627,106 (“Hsu”) (Ex. 1008) ......................................... 14
`
`U.S. Patent No. 5,731,945 (Bertin ‘945) (Ex. 1073) ................................ 16
`
`U.S. Patent No. 5,354,695 (“Leedy ’695”) (Ex. 1006) ............................. 18
`
`U.S. Patent No. 5,208,782 (“Sakuta”) (Ex. 1067) .................................... 22
`
`U.S. Patent No. 5,162,251 (“Poole”) (Ex. 1005) ...................................... 24
`
`Japanese Patent Publication H3-151637 (“Kowa”) (Ex. 1007) ................ 25
`
`B.
`
`Ground 1: (a) Hsu and Leedy ’695 Render Obvious Claim 1; (b) Hsu,
`Leedy ’695 and Sakuta Render Obvious Claim 49 ............................................... 26
`
`1.
`
`2.
`
`Claim 1 ...................................................................................................... 26
`
`Claim 49 .................................................................................................... 32
`
`i
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`

`
`Petition for Inter Partes Review
`Patent No. 8,907,499
`
`
`Ground 2: (a) Bertin ’945 Leedy ’695, and Poole Render Obvious Claim
`1; (b) Bertin ‘945, Leedy ’695, Poole and Sakuta Render Obvious Claim
`49........................................................................................................................... 41
`
`C.
`
`1.
`
`2.
`
`Claim 1 ...................................................................................................... 41
`
`Claim 49 .................................................................................................... 51
`
`IX.
`
`GROUNDS UNDER ALTERNATIVE CONSTRUCTIONS.......................................... 56
`
`A.
`
`B.
`
`Ground 3: (a) Hsu and Kowa Render Claim 1 Obvious; (b) Hsu, Kowa and
`Sakuta Render Claim 49 Obvious ......................................................................... 56
`
`Ground 4: (a) Bertin ’945 and Leedy’695 Render Claim 1 Obvious; (b)
`Bertin ’945, Leedy’695 and Sakuta Render Claim 49 Obvious ............................ 58
`
`THE PROPOSED GROUNDS ARE NOT REDUNDANT ............................................. 58
`
`CONCLUSION ................................................................................................................. 60
`
`
`
`X.
`
`XI.
`
`
`
`
`
`
`
`ii
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`
`
`

`
`Petition for Inter Partes Review
`Patent No. 8,907,499
`
`LIST OF EXHIBITS1
`Ex. 1001 U.S. Patent No. 8,907,499
`Ex. 1002 Declaration of Dr. Paul D. Franzon
`Ex. 1003
`Curriculum Vitae of Dr. Paul D. Franzon
`RESERVED
`Ex. 1004
`Ex. 1005 U.S. Patent No. 5,162,251 to Poole et al., issued November 10, 1992
`Ex. 1006 U.S. Patent No. 5,354,695 to Leedy, issued October 11, 1994
`Ex. 1007
`Japanese Patent Publication No. 3-151337 to Kowa including
`Japanese-language version, English-language translation, and
`translation certification
`Ex. 1008 U.S. Patent No. 5,627,106 to Hsu, issued May 6, 1997
`RESERVED
`Exs. 1009-
`1010
`Ex. 1011 U.S. Patent No. 5,426,072 to Finnila, Issued June 20, 1995
`RESERVED
`Exs. 1012-
`1015
`Ex. 1016
`
`Lim et al., The Impact of Wafer Back Surface Finish on Chip
`Strength, 27th Annual Proceedings of Reliability Physics, April 11-
`13, 1989
`RESERVED
`Prosecution History of U.S. Patent No. 8,907,499 - Office Action
`dated May 29, 2013
`Prosecution History of U.S. Patent No. 8,907,499 - Response to
`Office Action dated June 20, 2013
`Prosecution History of U.S. Patent No. 8,907,499 - As-Filed Patent
`Application
`Prosecution History of U.S. Patent No. 12/497,652 - Response to
`Office Action dated September 26, 2013
`Prosecution History of U.S. Patent No. 12/497,653 - Response to
`Office Action dated October 24, 2013
`Prosecution History of U.S. Patent App. No. 12/497,652 - Response
`to Office Action dated 4/5/13
`
`Ex. 1017
`Ex. 1018
`
`Ex. 1019
`
`Ex. 1020
`
`Ex. 1021
`
`Ex. 1022
`
`Ex. 1023
`
`
`
` 1
`
` Citations to non-patent publications are to the original page numbers of the
`
`publication, and citations to U.S. patents are to column:line number of the patents.
`
`iii
`
`

`
`Ex. 1024
`
`Ex. 1025
`
`Ex. 1026
`
`Ex. 1029
`
`Ex. 1030
`
`Ex. 1031
`
`Ex. 1027
`Ex. 1028
`
`Petition for Inter Partes Review
`Patent No. 8,907,499
`Prosecution History of U.S. Patent No. 5,915,167 - Response to
`Office Action dated April 28, 1998
`Prosecution History of U.S. Patent No. 5,915,167 - Response to
`Office Action dated September 8, 1998
`Prosecution History of U.S. Patent No. 8,629,542 - Response to
`Office Action dated July 30, 2012
`RESERVED
`Prosecution History of U.S. Patent No. 7,705,466 - Response to
`Office Action dated February 16, 2009
`Prosecution History of U.S. Patent No. 7,705,466 - Response to
`Office Action dated June 25, 2009
`Prosecution History of U.S. Patent No. 8,928,119 - Response to
`Office Action dated September 4, 2012
`Prosecution History of U.S. Patent No. 8,928,119 - Appeal Brief
`dated June 3, 2013
`Prosecution History of U.S. Patent No. 8,410,617 - Response to
`Office Action dated December 14, 2010
`Prosecution History of U.S. Patent Application no. 12/497,652 - Final
`Office Action dated June 3, 2013
`Prosecution History of U.S. Patent Application No. 12/497,652 -
`Express Abandonment dated November 20, 2014
`Prosecution History of U.S. Patent Application No. 12/497,653 -
`Advisory Action dated August 27, 2014
`Prosecution History of U.S. Patent Application No. 12/497,653 -
`Express Abandonment dated November 25, 2014
`RESERVED
`Ex. 1037
`Ex. 1038 Hirano et al., A New Three-Dimensional Multiport Memory for
`Shared Memory in High Performance Parallel Processor System,
`1996 International Conference on Solid State Devices and Materials,
`August 26, 1996.
`Concept One CVD System Process Specifications from Novellus
`Ex. 1039
`Ex. 1040 Wolf et al., Processing for the VLSI Era, Volume 1 - Process
`Technology (1986).
`Ex. 1041 U.S. Patent No. 3,508,980 to Jackson et al., issued April 28, 1970
`Ex. 1042 U.S. Patent No. 3,044,909 to Shockley, issued July 17, 1962
`Fahey et al., Stress-induced dislocations in silicon integrated circuits,
`Ex. 1043
`IBM J. Res. Develop. Vol. 36, No. 2, March 1992
`Ex. 1044 Hass et al., Physics of Thin Films: Advances in Research and
`Development (1966)
`
`Ex. 1032
`
`Ex. 1033
`
`Ex. 1034
`
`Ex. 1035
`
`Ex. 1036
`
`iv
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`

`
`Ex. 1045
`
`Ex. 1048
`
`Ex. 1053
`
`Ex. 1057
`
`Petition for Inter Partes Review
`Patent No. 8,907,499
`EerNisse, E.P., Stress in thermal SiO2 during growth, Appl. Phys.
`Lett. 35(1), July 1, 1979
`Ex. 1046 Klokholm, Erik, Delamination and fracture of thin films, IBM J. Res.
`Develop., Vol. 31, No. 5, September 1987
`Ex. 1047 U.S. Patent No. 4,948,482 to Kobayashi et al., issued August 14,
`1990
`Isobe et al., Dielectric Film Influence on Stress-Migration, June 12-
`13 IEEE VMIC Conference (1990)
`Ex. 1049 Van de Ven, et al., Advantages of Dual Frequency PECVD for
`Deposition of ILD and Passivation Films, June 12-13 IEEE VMIC
`Conference (1990)
`Ex. 1050 U.S. Patent No. 5,160,998 to Itoh et al., issued November 3, 1992
`Ex. 1051 Garrou, Philip, Polymer Dielectrics for Multichip Module Packaging,
`Proceedings of the IEEE, Vol. 80, No. 12, December 12, 1992
`Ex. 1052 Grief et al., Warpage and Mechanical Strength Studies of Ultra Thin
`150MM Wafers, IEEE/CPMT Int’l Electronics Manufacturing
`Technology Symposium (1996)
`Tatsuno, Sheridan, Japan’s Push into Creative Semiconductor
`Research: 3-Dimensional ICs, Solid State Technology, March 1987
`Ex. 1054 Akasaka, Yoichi, Three-Dimensional IC Trends, Proceedings of the
`IEEE, Vol. 74, No. 12, December 1986
`Ex. 1055 Hayashi, Yoshihiro, Evaluation of Cubic (Cumulatively Bonded IC)
`Devices, 9th Symposium on Future Electron Devices, November 14-
`15, 1990
`Ex. 1056 Williams et al., Future WSI Technology: Stacked Monolithic WSI,
`IEEE Transactions on Components, Hybrids, and Manufacturing
`Technology, Vol. 16, No. 7, November 1993
`Crowley et al., 3-D Multichip Packaging for Memory Modules, MCM
`’94 Proceedings, 1994
`Ex. 1058 Malinak, David, Memory-Chip Stacks Send Density Skyward,
`Electronic Design, August 22, 1994
`Ex. 1059 Kuhn et al., Interconnect Capacitances, Crosstalk, and Signal Delay
`in Vertically Integrated Circuits, IEEE 1995
`RESERVED
`
`Exs. 1060-
`1066
`Ex. 1067 U.S. Patent No. 5,208,782 to Sakuta, issued May 4, 1993, Priority
`date February 9, 1990
`RESERVED
`
`Exs. 1068-
`1069
`
`v
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`

`
`Petition for Inter Partes Review
`Patent No. 8,907,499
`Ex. 1070 Abbot et al., IBM T.J. Watson Research Center, “Durable Memory
`RS/6000 Design,” IEEE 1994
`Ex. 1071 Kleiner et al, “Performance Improvement of the Memory Hierarchy
`of RISC-systems by Application of 3-D Technology,” IEEE 1996
`RESERVED
`Ex. 1072
`Ex. 1073 U.S. Patent 5,731,945 to Bertin, issued March 24, 1998, Priority date
`February 22, 1995
`RESERVED
`Ex. 1074
`Ex. 1075 U.S. Pat. No. 5,270,261 to Bertin, issued December 14, 1993, Filing
`date October 23, 1992
`Terao et al., Purposes of Three-Dimensional Circuits, IEEE Circuits
`and Devices Magazine, November, 1987
`
`Ex. 1076
`
`vi
`
`

`
`Petition for Inter Partes Review
`Patent No. 8,907,499
`
`I.
`
`INTRODUCTION
`
`Samsung Electronics Co., Ltd.; Micron Technology, Inc.; and SK hynix Inc.
`
`(collectively, “Petitioner”) request inter partes review (“IPR”) of claims 1 and 49
`
`of U.S. Patent No. 8,907,499 (“the ’499 patent”) (Ex. 1001), which, on its face, is
`
`assigned to Elm 3DS Innovations, LLC (“Patent Owner”). This Petition presents
`
`several non-cumulative grounds of invalidity that the U.S. Patent and Trademark
`
`Office (“PTO”) did not consider during prosecution. These grounds are each
`
`reasonably likely to prevail, and this Petition, accordingly, should be granted on all
`
`grounds and the challenged claims should be cancelled.
`
`II. MANDATORY NOTICES UNDER 37 C.F.R. § 42.8
`Real Parties-in-Interest: Samsung Electronics Co., Ltd.; Samsung
`
`Semiconductor, Inc.; Samsung Electronics America, Inc.; Samsung Austin
`
`Semiconductor, LLC; Micron Technology, Inc.; Micron Semiconductor Products,
`
`Inc.; Micron Consumer Products Group, Inc.; SK hynix, Inc.; SK hynix America,
`
`Inc.; Hynix Semiconductor Manufacturing America, Inc.; and SK hynix Memory
`
`Solutions, Inc.
`
`Related Matters: Patent Owner has asserted the ’499 patent against
`
`Petitioner in Elm 3DS Innovations, LLC v. Samsung Elecs. Co., No. 1:14-cv-01430
`
`(D. Del.); Elm 3DS Innovations, LLC v. Micron Tech., Inc., No. 1:14-cv-01431 (D.
`
`Del.); and Elm 3DS Innovations, LLC v. SK hynix Inc., No. 1:14-cv-01432 (D.
`
`1
`
`

`
`Petition for Inter Partes Review
`Patent No. 8,907,499
`Del.). Patent Owner has also asserted related U.S. Patent Nos. 7,193,239;
`
`7,474,004; 7,504,732; 8,035,233; 8,410,617; 8,653,672; 8,791,581; 8,629,542;
`
`8,841,778; 8,496,862; 8,928,119; and 8,933,570 in one or more of these actions.
`
`Petitioner has already requested inter partes review of the following patents:
`
`7,193,239 (IPR2016-00388 and IPR2016-00393); 7,504, 732 (IPR2016-00395);
`
`8,629,542 (IPR2016-00390); 8,035,233 (IPR2016-00389); 8,410,617 (IPR2016-
`
`00394); 8,653,672 (IPR2016-00386); 8,796,862 (IPR2016-00391); 8,841,778
`
`(IPR2016-00387); 8,928,119 (IPR2016-00687); and 7,474,004 (IPR2016-00691).
`
`And Micron Technology, Inc. and SK hynix Inc. have already requested inter
`
`partes review of 8,791,581 (IPR2016-00703 and IPR2016-00706). Petitioner is
`
`also concurrently filing another IPR petition on other claims of the ‘499 patent.
`
`Counsel and Service Information: Lead counsel is John Kappos (Reg. No.
`
`37,861), O’Melveny & Myers LLP, 610 Newport Center Drive, 17th Floor,
`
`Newport Beach, CA 92660, Tel.: 949.823.6900, Fax: 949.823.6994, email:
`
`jkappos@omm.com; and backup counsel is Naveen Modi (Reg. No. 46,224), Paul
`
`Hastings LLP, 875 15th St. N.W., Washington, D.C., 20005, Tel.: 202.551.1700,
`
`Fax: 202.551.1705, email: PH-Samsung-ELM-IPR@paulhastings.com; and Jason
`
`Engel (Reg. No. 51,654), K&L Gates LLP, 70 W. Madison St., Suite 3100,
`
`Chicago, IL 60602, Tel.: 312.807.4236, Fax: 312.827.8145, E-mail:
`
`jason.engel.PTAB@klgates.com. Petitioner consents to electronic service.
`
`2
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`

`
`Petition for Inter Partes Review
`Patent No. 8,907,499
`III. PAYMENT OF FEES UNDER 37 C.F.R. § 42.15(a)
`The PTO is authorized to charge all fees due at any time during this
`
`proceeding, including filing fees, to Deposit Account No. 50-2862.
`
`IV. GROUNDS FOR STANDING
`Petitioner certifies that, under 37 C.F.R. § 42.104(a), the ’499 patent is
`
`available for IPR, and that Petitioner is not barred or estopped from requesting IPR
`
`of the ’499 patent on the grounds identified.
`
`V.
`
`PRECISE RELIEF REQUESTED
`
`Petitioner respectfully requests review of claims 1 and 49 of the ’499 patent,
`
`and cancellation of these claims as unpatentable, in view of the following grounds
`
`under 35 U.S.C. § 103:
`
`Ground 1: (a) U.S. Patent No. 5,627,106 (“Hsu”), in combination with U.S.
`
`Patent No. 5,354,695 (“Leedy ’695”), renders obvious claim 1; and (b) Hsu in
`
`combination with Leedy ’695 and U.S. Patent No. 5,208,782 (“Sakuta”) renders
`
`obvious claim 49; Ground 2: (a) U.S. Patent No. 5,731,945 (“Bertin ‘945”) in
`
`combination with Leedy ‘695 and U.S. Patent No. 5,162,251 (“Poole” ) renders
`
`obvious claim 1; (b) Bertin ‘945 in combination with Leedy ‘695, Poole and
`
`Sakuta renders obvious claim 49.
`
`3
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`

`
`Petition for Inter Partes Review
`Patent No. 8,907,499
`In the event the Board adopts alternative constructions discussed below in
`
`Parts VII and IX, Petitioner submits the following additional grounds under 35
`
`U.S.C. § 103:
`
`Ground 3: (a) Hsu in combination with Japanese Patent Pub. H3-151637
`
`(“Kowa”) (Ex. 1007)2, renders obvious claim 1; and (b) Hsu in combination with
`
`Kowa and Sakuta renders obvious claim 49 Hsu; Ground 4: (a) Bertin ‘945 in
`
`combination with Leedy ‘695 renders obvious claim 1 under 35 U.S.C. § 103; (b)
`
`Bertin ‘945 in combination with Leedy ‘695 and Sakuta renders obvious claim 49.
`
`On its face, the ’499 patent claims a priority date of April 4, 1997.
`
`Therefore, for purposes of this proceeding, and without conceding that the claims
`
`are entitled to this date, Petitioner has assumed a priority date of April 4, 1997.
`
`Sakuta issued on May 4, 1993, Poole issued on November 10, 1992, Leedy ’695
`
`issued on October 11, 1994, and Kowa published on June 27, 1991. Therefore,
`
`these references are prior art at least under 35 U.S.C. § 102(b). Hsu was filed on
`
`May 6, 1994, and issued on May 6, 1997, and is therefore prior art at least under 35
`
`U.S.C. § 102(e). Bertin ‘945 has a priority date of February 22, 1995, and issued
`
`on March 24, 1998, and is therefore prior art at least under 35 U.S.C. § 102(e).
`
`
`
` 2
`
` Ex. 1007 includes the Japanese version of Kowa (id. at 1-5), an English
`
`translation (id. at 6-12), and an affidavit required by 37 C.F.R. §42.63(b).
`
`4
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`

`
`Petition for Inter Partes Review
`Patent No. 8,907,499
`
`VI. THE ’499 PATENT
`A. Technical Background
`ICs are typically fabricated on a thin slice of silicon (a wafer) and
`
`“singulated” into individual devices (dice). Ex. 1002 at ¶17. A basic two-
`
`dimensional (“2D”) IC has a single, active circuit layer mounted in a package in a
`
`single plane. Id. Since the IC’s creation in 1958, designers have worked to
`
`improve computing power and efficiency of electronic structures. Id. at ¶20.
`
`IC designers have long thinned and polished substrates to create thin
`
`electronic circuits that could fit in ever-smaller devices. Id. at ¶21. Designers have
`
`also long relied on vertical interconnections to connect different vertical levels
`
`within an IC. Id. at ¶22. While reliability has always been a concern, many of the
`
`processes used in the fabrication of silicon ICs impose stress on silicon substrates
`
`that unacceptably affect the yield. Id. 2at ¶23. Consequently, substantial efforts
`
`have been made to study and improve stress management, including the use of low
`
`tensile stress materials and stress balancing. Id. at ¶¶24-37. By 1996, it was well
`
`known to thin and polish wafers, use TSVs to electrically connect layers in an IC,
`
`and to manage stress. Id. at ¶38; see also id. at ¶¶21-37.
`
`As performance enhancement through miniaturization became more
`
`challenging, three-dimensional (“3D”) IC development became one way to
`
`improve efficiency. Id. at ¶39. The benefits of 3D ICs have been known for over
`
`5
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`
`Petition for Inter Partes Review
`Patent No. 8,907,499
`30 years. Id. at ¶¶40-44. Not surprisingly, IC designers carried 2D techniques into
`
`3D designs; these techniques included thinning and polishing (id. at ¶¶45-46),
`
`TSVs to connect active device layers (id. at ¶¶44, 47-51), and stress management
`
`(id. at ¶¶44, 51).
`
`B. Overview of the ’499 Patent
`The ’499 patent generally describes “stacked integrated circuit memory.”
`
`Ex. 1001 at 1:7-8, 3:3-16. The ’499 patent describes “two principal fabrication
`
`methods,” which generally include the steps of thinning substrates, bonding
`
`substrates to form a vertical stack, and forming vertical interconnections passing
`
`through the substrates. Id. at 7:26-11:5. According to the ’499 patent, a
`
`semiconductor substrate is thinned by a grinding and polishing (or smoothing)
`
`process to a thickness of less than 50 µm, but explains that other well-known
`
`thinning techniques can instead be used. Id. at 9:12-41, 10:49. Additionally, the
`
`specification and claims of the ’499 patent recite the use of low tensile stress
`
`dielectrics, which the specification acknowledges was described years prior to the
`
`earliest alleged priority date of the ’499 patent by the named inventor in Leedy
`
`’695. See, e.g., id. at 8:54-9:4, Claim 4. Ex. 1002 at ¶¶ 60-74.
`
`The ’499 patent also discusses various well-known, memory-specific
`
`features and functions of a “3DS Memory Device Controller.” For example, the
`
`’499 patent discusses the ability to perform “internal test (self-test) of the various
`
`6
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`
`Petition for Inter Partes Review
`Patent No. 8,907,499
`memory array blocks.” Ex. 1001 at 12:26-29. This testing includes
`
`“programmable (dynamic) assignment of unique addresses corresponding to the
`
`various gate-lines of each memory array block on each layer.” Id. at 12:31-34. By
`
`performing this testing, the ’499 patent describes that its 3DS memory circuit can
`
`then reconfigure (i.e., perform “sparing” on) the “addresses of gate-lines that fail
`
`after the 3DS memory circuit is in use in a product.” Id. at 12:34-39.
`
`C. Level of Ordinary Skill in the Art
`One of ordinary skill in the art the time of the alleged invention of the ’499
`
`patent would have had at least a B.S. degree in electrical engineering, material
`
`science, or equivalent thereof, and at least 3-5 years of experience in the relevant
`
`field, e.g., semiconductor processing. Ex. 1002 at ¶¶58-59. Petitioner submits the
`
`declaration of Dr. Paul D. Franzon (Ex. 1002), an expert in the field of the ’499
`
`Patent (Ex. 1002 at ¶¶1-14), and Dr. Franzon’s CV (Ex. 1003) herewith.
`
`VII. CLAIM CONSTRUCTION
`An unexpired claim subject to IPR receives the “broadest reasonable
`
`construction in light of the specification of the patent in which it appears.” 42
`
`C.F.R. § 42.100(b).3 The Board may consider prosecution histories when
`
`
`
` 3
`
` The ’499 patent may expire during this proceeding. After expiration, the claims
`
`should be construed according to the Phillips v. AWH Corp. standard applicable in
`
`7
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`

`
`Petition for Inter Partes Review
`Patent No. 8,907,499
`determining the broadest reasonable construction of a claim. See, e.g., Microsoft
`
`Corp. v. Proxyconn, Inc., 789 F.3d 1292, 1298 (Fed. Cir. 2015). For purposes of
`
`this proceeding, Petitioner proposes constructions for the term(s) identified below.
`
`Any remaining terms should be given their plain and ordinary meaning according
`
`to the “broadest reasonable construction” standard. Because the claim construction
`
`standard in this proceeding differs from the standard applicable to a district court
`
`litigation, Petitioner expressly reserves the right to argue in district court for a
`
`different construction for any claim term in the ’499 patent.
`
`A.
`
` “substantially flexible monocrystalline semiconductor layer”
`(Claim 1)
`
`In light of the specification and intrinsic record of the ’499 patent, the
`
`broadest reasonable construction of “substantially flexible” when used to modify
`
`“semiconductor layer” is “a semiconductor layer that has been thinned to a
`
`thickness of less than 50 μm and subsequently polished or smoothed.”
`
`Acting as his own lexicographer, the Applicant defined “substantially
`
`flexible” in the specification, which states: “Grind the backside or exposed surface
`
`of the second circuit substrate to a thickness of less than 50 μm and then polish or
`
`
`
`district court. 415 F.3d 1303 (Fed. Cir. 2005). Under the Phillips standard, the
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`challenged claims are unpatentable for the same reasons set forth herein.
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`8
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`Petition for Inter Partes Review
`Patent No. 8,907,499
`smooth the surface. The thinned substrate is now a substantially flexible
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`substrate.” Ex. 1001 at 9:16-19; see also id. at 3:18-21, 4:35-37.
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`The Applicant confirmed this definition during prosecution of the ’499
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`patent. The Examiner objected to certain claims for including the term
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`“substantially flexible” as indefinite for failing to “clearly set for[th] the metes and
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`bounds of the patent protection desired.”4 Ex. 1018 at 4. The Applicant overcame
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`the objection by arguing that “substantially flexible” is unambiguous because it is
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`“clearly explained in the specification”:
`
`With respect to the language “substantially flexible,” the meaning of
`this phrase as used in the claims is clearly explained in the
`specification including, for example, at page 18, lines 1-3. As
`described in this passage, a semiconductor substrate is caused to be
`substantially flexible by thinning it to 50 microns or less and polishing
`or smoothing the thinned semiconductor substrate to relieve stress.
`The phrase “substantially flexible” is used in the claims consistent
`with this description, which is unambiguous.
`
`Ex. 1019 at 9; Ex. 1020 at 18:1-3; see also Ex. 1021 at 2; Ex. 1022 at 2.
`
`
`
` 4
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` Petitioner reserves the right to challenge the validity of the claims under 35
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`U.S.C. § 112 as indefinite for “failing to inform, with reasonable certainty, those
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`skilled in the art about the scope of the invention.” Nautilus, Inc. v. Biosig Instr.,
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`Inc., 134 S.Ct. 2120, 2124 (2014).
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`Petition for Inter Partes Review
`Patent No. 8,907,499
`Accordingly, the Applicant clearly and unmistakably set forth a definition of
`
`the term “substantially flexible” when used to modify a semiconductor layer or
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`substrate and expressed an intent to define the term. See Tempo Lighting, Inc. v.
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`Tivoli, LLC, 742 F.3d 973, 977-78 (Fed. Cir. 2014). Similarly, these clear and
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`unmistakable statements by the Applicant limit the scope of the term. See In re
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`Katz Interactive Call Processing Patent Litigation, 639 F.3d 1303, 1324 (Fed. Cir.
`
`2011). Therefore, the proper construction of this term, when used to modify a
`
`semiconductor layer, under the broadest reasonable construction, is “a
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`semiconductor layer that has been thinned to a thickness of less than 50 μm and
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`subsequently polished or smoothed.”5
`
`Moreover, “substantially flexible” is a term of degree that must be construed
`
`to have an objective standard of measurement, because the term would otherwise
`
`be indefinite, as the Examiner found during prosecution of the ’499 patent. See Ex.
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`1018 at 4; Ex. 1002 at ¶¶77-80. The Board has consistently found similar claim
`
`
`
` 5
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` Any argument that Petitioner’s proposed constructions for the “substantially
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`flexible” terms ignore the doctrine of claim differentiation should be rejected
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`because the doctrine cannot overcome the Applicant’s unambiguous statements
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`made during prosecution. See Seachange Int’l, Inc. v. C-COR, Inc., 413 F.3d
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`1361, 1369 (Fed. Cir. 2005).
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`10
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`Petition for Inter Partes Review
`Patent No. 8,907,499
`language to be terms of degree. See, e.g., MedShape Inc. v. Cayenne Med., Inc.,
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`IPR2015-00848, 2015 WL 5453171, *5 (P.T.A.B. September 14, 2015)
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`(“substantially different”). Claims that recite a term of degree are indefinite unless
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`the patent specification “provide[s] ‘some standard for measuring that degree.’”
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`Id. at *5 (citing Seattle Box Co. v. Industrial Crate & Packing, Inc., 731 F.2d 818
`
`(Fed. Cir. 1984)). Here, the intrinsic record provides only a single standard for
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`determining whether a substrate is “substantially flexible”—whether the thickness
`
`of the substrate after thinning is less than 50 µm and then polished or smoothed.
`
`See Ex. 1001 at 9:16-19, 3:18-21, and 4:35-37; Ex. 1019 at 9. Accordingly, under
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`the applicable claim construction standard, Petitioner’s proposed construction
`
`should be adopted because it sets forth the only reasonable standard for measuring
`
`a term of degree that would otherwise render the claims indefinite.
`
`Petitioner believes Patent Owner may propose an unreasonably broad
`
`construction of this term, such as (i) “a semiconductor layer that has been thinned
`
`to a thickness of less than 50 μm,” or (ii) “a semiconductor layer that has been
`
`thinned to a thickness of 150 μm or less.” Under either of these constructions, the
`
`challenged claims would still be unpatentable in view of the prior art discussed
`
`herein because it teaches or suggests thinning semiconductor substrates to a
`
`thickness of less than 50 µm.
`
`
`
`
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`Petition for Inter Partes Review
`Patent No. 8,907,499
`“substantially flexible structure” (claims 1, 49)
`
`B.
`The broadest reasonable construction of “substantially flexible” when used
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`to modify a “structure” is “a structure having a semiconductor substrate that has
`
`been thinned to a thickness of less than 50 μm and subsequently polished or
`
`smoothed, and where the dielectric material used in processing the semiconductor
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`substrate must have a stress of 5×108 dynes/cm2 tensile or less.”
`
`For example, the specification explains that each “circuit layer is a thinned
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`and substantially flexible circuit with net low stress, less than 50 μm and typically
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`less than 10 μm in thickness” (Ex. 1001 at 4:33-40), and that “[t]he thinned
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`(substantially flexible) substrate circuit layers are preferably made with dielectrics
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`in low stress (less than 5×108 dynes/cm2).” Id. at 8:58-63.
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`During prosecution of related applications, the Applicant elaborated further
`
`to distinguish prior art. For example, during prosecution of U.S. Patent
`
`Application Nos. 12/497,652 and 12/497,653, which share the same specification
`
`as the ’499 patent, the Applicant stated that “substantially flexible” when used to
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`modify integrated circuit layer requires two features: (i) “the semiconductor
`
`material must be sufficiently thin, e.g., 50 microns or less,” and (ii) “the dielectric
`
`material used in processing the semiconductor material must be sufficiently low
`
`stress,” which, “[a]s set forth in the present specification, stress of 5 x 108
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`Petition for Inter Partes Review
`Patent No. 8,907,499
`dynes/cm2 or less has been demonstrated to satisfy this requirement.” Ex. 1023 at
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`28; see also supra Ex. 1019 at 9.
`
`The Applicant confirmed this definition in a September 26, 2013 Response,
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`stating that “a substantially flexible semiconductor substrate is a necessary but not
`
`a sufficient condition for a substantially flexible circuit layer,” because, “[f]or a
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`circuit layer to be substantially flexible, Applicant has found that the dielectric
`
`material must have low tensile stress, for example, 5 x 108 dynes/cm2 tensile.” Ex.
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`1021 at 2-3. See also Ex. 1019 at 9.
`
`Accordingly, the Applicant clearly and unmistakably set forth a definition of
`
`the term “substantially flexible” when used to modify an integrated circuit
`
`structure and expressed an intent to define the term. See Tempo, 742 F.3d at 977-
`
`78. Similarly, these clear and unmistakable statements by the Applicant limit the
`
`scope of the term. See Katz, 639 F.3d at 1324. Therefore, the broadest reasonable
`
`construction of “substantially flexible” when used to modify “structure” is “an
`
`integrated circuit having a semiconductor substrate that has been thinned to a
`
`thickness of less than 50 μm and subsequently polished or smoothed, and where
`
`the dielectric material used in processing the semiconductor substrate must have a
`
`stress of 5×108 dynes/cm2 tensile or less.” See supra Ex. 1023 at 28; Ex. 1019 at 9.
`
`Moreover, as discussed above, “substantially flexible” is a term of degree
`
`that must be construed to have an objective standard of measurement—like set
`
`13
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`Petition for Inter Partes Review
`Patent No. 8,907,499
`forth in Petitioner’s proposal—because the term would otherwise be indefinite. See
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`MedShape Inc., 2015 WL 5453171 at *5.
`
`Petitioner believes Patent Owner may propose an unreasonably broad
`
`construction of this term, such as (i) “structure having a semiconductor substrate
`
`that has been thinned to a thickness of less than 50 μm, and where the dielectric
`
`material used in processing the semiconductor substrate must have a stress of
`
`5×108 dynes/cm2 tensile or less,” or (ii) “structure having a semiconductor
`
`substrate that has been thinned to a thickness of 150 μm or less.” Under either of
`
`these constructions, the challenged claims would still be unpatentable in view of
`
`the prior art discussed herein, because the prior art teaches or suggests thinning
`
`semiconductor substrates to a thickness of less than 50 µm and the use of dielectric
`
`material having a stress of 5×108 dynes/cm2 tensile or less.
`
`VIII. DETAILED EXPLANATION OF GROUNDS UNDER THE
`BROADEST REASONABLE CONSTRUCTIONS
`A. Overview of the Prior Art References
`U.S. Patent No. 5,627,106 (“Hsu”) (Ex. 1008)
`1.
`Hsu relates generally to a “method of connecting three-dimensional
`
`integrated circuit chips using trench technology.” Ex. 1008 at Abstract, 1:8-11.
`
`Hsu describes the application of 3