by D. R. Cote
`S. V. Nguyen
`W. J, Cote
`S. L. Pennington
`A. K. Stamper
`D. V. Podlesnik
`
`Low-
`temperature
`chemical vapor
`deposition
`processes and
`dielectrics for
`microelectronic
`circuit
`manufacturing
`at IBM
`
`Significant progress has been made over the
`past decade in iow4emperature plasma-
`enhanced and thermal chemical vapor
`deposition (CVD). The progress has occurred
`in response to the high demands placed on
`the insulators of multilevel microelectronic
`circuits because of the continuing reduction
`In circuit dimensions. High-aspect-ratio gap
`filling Is foremost among these demands,
`which also include lower processing
`temperatures and improved dielectric
`planarizatlon. This paper reviews the history
`of interlevel and intermetal dielectrics used in
`
`microelectronic circuit manufacturing at IBM
`and the current status of processes used In
`IBIUI manufacturing and development lines, and
`describes the challenges for future memory
`and logic chip applications.
`
`Introduction
`There are a number of techniques available to deposit
`insulators in microelectronic circuit fabrication, but
`chemical vapor deposition (CVD) is by far the most
`important. We discuss both thermal and plasma-enhanced
`CVD [1-9]. Processing temperatures below 800°C are
`
`^Copyright 1995 by International Business Machines Corporatioo. Copying in printed fom^ for private use is permitted without paymenr of royalty provided Ebat (1) each
`reproduction is done without alteration and (2) thsj&umai reference and IBM copyright notice are included on the first page. The title and abstract, but no otlier portions, of
`this paper may be copied or distributed royalty free without further permission by computer-based and other information-service systetns. Permission to repiMish any other
`portion of this paper must be obtained from the Editor.
`
`437
`
`MtB-8646/95/$3.00 « 189S IBM
`
`IBM J. RES. DEVELOP. VOL. 39 NO. 4 JULY 1995
`
`D. R. COTE ET AL.
`
`Elm Exhibit 2133
`Samsung, Micron, SK hynix v. Elm
`IPR2016-00706
`
`

`
`After metal deposition/
`patterning/etching
`
`After oxide deposition
`
`After oxide planarization
`
`Typical process sequence for a multilevel interconnection structure
`fabricated by subtractive etching of the metal followed by oxide
`deposition and planarization. It is critical that the oxide fill the
`gaps between the metal lines without the formation of voids.
`
`required to maintain shallow junction depths [10] and avoid
`agglomeration of transition metal silicides used either in
`silicided junctions or as part of the gate conductor [11-13].
`For the Al(Cu)-based interconnect layers, processing
`temperatures below 450°C are required, since the metal
`degrades rapidly above this temperature, forming voids
`and hillocks [14].
`Among the insulators used are silicon dioxide and doped
`silicate glasses. They are easily patterned by reactive
`ion etching (RIE) and can possess good chemical and
`mechanical stabilities. Such films can also exhibit
`moderately low dielectric constants and very high
`electrical resistivities. It is more difficult to deposit high-
`quality CVD oxide films at low temperatures [1], because
`by-products of the chemical reaction, i.e., hydrogen,
`water, and hydroxyl groups, can be incorporated into the
`film. These by-products can reduce the device performance
`and stability. The presence of water increases the
`dielectric constant and thus decreases circuit speed
`[6, 15]. Water also aggravates hot-carrier-induced device
`degradation by diffusing into the gate oxide [16]. Hydrogen
`and absorbed water also make the insulator less dense or
`can outgas from the insulator during subsequent thermal
`steps, causing a change in film stress. This stress change
`in the insulator can lead to cracking or delamination
`[17]. Clearly, insulator quality must be very high for
`reliable device performance, stability, and mechanical
`integrity.
`
`438
`
`Originally, the primary source material for low-
`temperature CVD insulators was silane [18], since it
`oxidizes easily at temperatures less than 500°C.
`Silane has been used in low-temperature atmospheric
`pressure chemical vapor deposition (APCVD) of
`oxide [19], phosphosilicate glass (PSG) [20, 21] and
`borophosphosilicate glass (BPSG) [22], and in plasma-
`enhanced chemical vapor deposition (PECVD) of oxide
`[23] and nitride [24] layers. CVD of oxide layers by the
`reaction of tetraethoxysilane (TEOS) and oxygen was
`reported as early as 1961 [25, 26]. TEOS was subsequently
`used in semiconductor manufacturing in high-temperature,
`low-pressure chemical vapor deposition (LPCVD)
`applications, but the use of TEOS as a source for PECVD
`was not common until the late 1980s [27]. The PECVD
`TEOS oxide films have much better step coverage than
`silane-based oxide films; this improvement in step
`coverage was fully exploited for gap-fill applications.
`APCVD [28] and later subatmospheric chemical vapor
`deposition (SACVD) [29] of oxide layers by the reaction of
`TEOS and ozone also showed a dramatic improvement in
`gap filling (or simply "gap fill") compared to the silane-
`based APCVD processes, making APCVD and SACVD
`extendible to sub-half-micron applications.
`
`We discuss two primary applications for low-
`temperature CVD of insulators: 1) as an interlevel
`dielectric (ILD) for the passivation of the polysilicon gate
`conductor in field-effect transistor (PET) devices, and 2) as
`an intermetal dielectric (IMD) between aluminum/copper
`or tungsten interconnects. Low-temperature CVD of
`dielectrics for final passivation is not covered in this
`paper. Once the coverage and thickness of the insulators
`(typically PECVD oxide, PECVD nitride, and polyimide)
`have been optimized, the remaining issues at this level
`are mainly chip/packaging interactions [30, 31].
`Insulators for multilevel interconnections are commonly
`deposited by CVD on top of metal layers that have been
`patterned with reactive ion etching (RIE). Typically, oxide
`deposition is followed by partial planarization using
`spun-on-glass [32-34] or resist etch-back techniques
`[32, 35-37] and more recently by global planarization with
`chemical-mechanical polishing (CMP). A typical process
`sequence is shown in Figure 1. The oxide must fill the
`spaces between the metal lines without leaving voids. If
`the voids are exposed during the subsequent planarization
`or during the patterning of the next wiring level, metal will
`easily deposit into the void and form an electrical short.
`Filling these spaces is difficult when they approach sub-
`half-micron size.
`Another technique used to build a multilevel
`interconnection structure is known as the "damascene"
`technique. In this technique, an oxide is deposited on a
`planar surface and the wiring level is patterned (by
`lithography and etching) into the oxide, forming trenches.
`
`D. R. COTE ET AL.
`
`IBM J. RES. DEVELOP. VOL. 39 NO. 4 JULY 1995
`
`Elm Exhibit 2133, Page 2
`
`

`
`Metal is then deposited and subsequently removed by
`CMP, using the oxide as a polishing stop. The metal
`remains only in the patterned trenches in the oxide
`[38-40]. The damascene technique is illustrated in Figure 2.
`With this technique, the oxide does not have to fill the
`gaps between the metal lines; the burden of gap fill lies on
`the metal, not the oxide. Currently, tungsten is the only
`metal being used in damascene processing in IBM
`manufacturing. Since the resistivity of tungsten is
`approximately three times higher than that of aluminum,
`the damascene process is used only for applications where
`line resistance is not critical. Because it is expected that
`aluminum-based lines formed by RIE will be the mainstay
`for current and future logic generations, dielectric gap fill
`will remain a key requirement.
`In addition to filling gaps between metal lines, low-
`temperature insulators must also fill spaces between
`polysilicon gate conductor lines in a circuit containing
`MOSFET devices. The spaces between the gate conductor
`lines are usually smaller than those found in the upper
`wiring levels, and thus more difficult to fill. The aspect
`ratios (height of the line divided by the distance between
`the lines) are typically two to four times larger for the gate
`conductor level. Doped silicon oxide films such as PSG
`and BPSG [15] are the preferred insulators for polysilicon
`gate conductor lines. The general process steps include
`film deposition followed by thermal densification, reflow,
`and either sacrificial etch-back or CMP processes. The
`phosphorus provides protection against mobile ion
`contamination [41, 42]. In addition, phosphorus- and
`boron-doped oxides provide high etch selectivity to nitride
`and undoped oxide, making such oxides desirable materials
`for etching [43]. Most significantly, boron and phosphorus
`doping in BPSG allows the use of low-temperature reflow
`for improved gap fill and planarization. An additional
`advantage of PSG and BPSG is that they polish 1.5-3
`times more rapidly than undoped films, making it cost-
`effective to use CMP.
`A primary concern for ultra-large-scale integrated
`(ULSI) circuit fabrication is process-induced damage to the
`gate oxide. Such damage leads to significant device yield
`loss [44] and reliability problems [45]. Rakkhit et al. [46]
`have shown that process-induced damage is cumulative as
`wafers are processed through the BEOL (back end of line).
`Since advanced integrated circuit fabrication typically
`involves many plasma-based processes, it is of the utmost
`importance to isolate and minimize all levels of charge
`damage throughout the process flow. Charge build-up and
`damage effects have been reported for plasma etching
`[47-51] and plasma deposition [44, 45, 51-53].
`As an example, we describe the gate oxide degradation
`in 64Mb DRAM product chips due to PECVD PSG
`process-induced charge damage, along with our
`methodology for isolating, fixing, and eliminating the
`
`After oxide
`patterning/etching
`
`After metal deposition
`
`After metal planarization
`
`Typical process sequence for multilevel interconnection structure
`fabricated using the damascene technique. Note that the metal,
`not the oxide, must now fill the gaps.
`
`charge damage. Reduced device damage in advanced
`deposition technology such as electron cyclotron
`resonance (ECR) and helicon plasma deposition is also
`discussed.
`In addition to conventional CVD silicon nitride and
`oxide films [3-9], there are many other CVD dielectric
`films (and associated processes) being studied for advanced
`ULSI applications. We present some recent advanced
`CVD processes that are being explored for quarter-micron
`complementary metal oxide semiconductor (CMOS) circuit
`fabrication. There are other dielectric materials being
`examined for future applications, such as organic
`dielectrics for copper interconnects [39]. However,
`such topics are beyond the scope of this paper.
`
`Historical perspective
`We discuss the evolution of interlevel and intermetal
`dielectrics using dynamic random access memory (DRAM)
`chips as the vehicle. For both logic and memory devices
`and circuits, a significant driving force behind recent
`technological advances has been the need to fulfill more
`demanding gap-fill requirements. This discussion is meant
`to be a survey of the main processes used by IBM, and
`therefore is not all-inclusive.
`
`• Early-generation DRAM (64Kb, 256Kb, and 1Mb)
`products
`For early-generation DRAM product chips, a variety of
`techniques were used to deposit passivation dielectrics.
`
`439
`
`IBM J. RES. DEVELOP. VOL. 39 NO. 4 JULY 1995
`
`D. R. COTE ET AL.
`
`Elm Exhibit 2133, Page 3
`
`

`
`nitride/spun-on polyimide passivation because of the then-
`unacceptable particulate levels and low deposition rates
`associated with bias-sputtered quartz processing. For the
`1Mb DRAM product, use was made of polysilicon rather
`than Al(Cu) gates, allowing more flexibility in the choice of
`the gate insulator. PSG was deposited onto production
`wafers at atmospheric pressure using phosphine, silane,
`and oxygen as the reactants and subsequently reflowed at
`high temperature, conditions similar to those reported by
`Kern [54]. Since the 1Mb DRAM product was designed
`with only a single level of metal at a pitch (line plus space)
`of 3.0 fim, PECVD nitride followed by spun-on polyimide
`sufficed as the metal passivation.
`
`• 4Mb DRAM product
`The reduction in device dimensions from the 1Mb to 4Mb
`DRAM product chips caused major changes for both
`interlevel and intermetal dielectric processes. Shallower
`source/drain junctions reduced the overall thermal budget
`and limited subsequent heat treatments to below 900°C.
`The requirements to fill the narrow spaces between
`the gate conductor lines, and better planarization,
`drove the migration to a different doped glass for the
`polysilicon-metal interlevel dielectric. To modify the 1Mb
`PSG process to reflow at a lower temperature, it would
`have been necessary to increase the concentration of the
`phosphorus. Corrosion of metal and device performance
`was a concern because of the possibility of phosphoric
`acid formation at high phosphorus concentrations [55].
`Therefore, in order to obtain good reflow at a lower
`temperature (SOOT), PSG was replaced with BPSG for
`the 4Mb DRAM product chips. BPSG was deposited at
`atmospheric pressure using silane, oxygen, diborane, and
`phosphine as the reactants. This process was compatible
`with the salicide gate conductor and filled the submicron
`spaces easily. Although reflowed BPSG provided sufficient
`local planarization, there were defect problems associated
`with the low-temperature BPSG deposition and 800°C
`reflow. The main problem was hydrolysis of boron oxide in
`the BPSG, which resulted in the appearance of boric acid
`crystals on the wafer surface and prompted further
`changes in the planarization process. Eventually, the
`BPSG was capped with a thermal silane oxide, then
`planarized using CMP. The advent of oxide CMP opened
`the door for important developments in low-temperature
`dielectric gap fill, since planarization was no longer a
`deposition issue.
`
`A different approach was required to fill the spaces
`between the metal lines for the 1.9-/im pitch (line = 0.9 fim,
`space = 1.0 fim) with a reliable insulator. CVD nitride
`and polyimide could not adequately fill the spaces between
`the metal lines and left voids. Also, nitride has a high
`dielectric constant, leading to an increase in coupling
`capacitance. Bias-sputtered quartz was ruled out as a
`
`(a)
`
`After oxide planarization
`
`Al/Cu metal lines
`(b)
`
`After metal deposition
`
`Large metal-filled void
`
`(c)
`
`tS<^%i!t>'s'to#^-^ r;
`(a) SEM cross section of structure containing PECVD oxide
`deposited by the reaction of silane and nitrous oxide; an
`intervening void is the result of the poor step coverage associated
`with the process, (b) Schematic of the structure after planarization
`and (c) after metal deposition, indicating likelihood of an intralevel
`metal short due to the presence of a void.
`
`Beginning with the 64Kb DRAM chip, bias-sputtered
`quartz and spun-on polyimide were used to insulate the
`Al(Cu) gate from the next (and final) level of metal wiring.
`For the 256Kb DRAM product, use was made of a CVD
`
`440
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`D. R. COTE ET AL.
`
`IBM J. RES. DEVELOP. VOL. 39 NO. 4 JULY 1995
`
`Elm Exhibit 2133, Page 4
`
`

`
`metal passivation candidate because of the aforementioned
`limitations of deposition rate and high particulate levels.
`The step coverage of the available APCVD silane oxide
`films was poor, causing voids to be formed between the
`metal lines. PECVD oxide deposited by the reaction of
`silane and nitrous oxide also had poor step coverage, as
`shown in Figure 3(a). The PECVD silane oxide is a
`nonconformal film (i.e., less oxide is deposited on the
`vertical sidewalls than on the horizontal surfaces), and
`there is a considerable amount of cusping, giving it a
`"breadloaf" profile. As the deposition progresses, it
`pinches off, leaving a large void or "keyhole" between
`the metal hnes. The void might be opened up during the
`subsequent planarization and/or via etch of the dielectric,
`as shown in Figure 3(b). CVD metal, e.g., tungsten, can
`easily fill such an exposed void, creating a likely pathway
`for shorting, as shown in Figure 3(c).
`Therefore, an innovation in intermetal dielectric
`processing was required in order to fill the smaller spaces
`of this new DRAM generation. In 1983, planarization of
`silicon nitride and PSG argon by sputter-etching was
`reported [56]. Although the sputter-etching was used as a
`final planarization step in this particular process, it became
`clear that sputter-etching thinner oxides over smaller
`features would taper the sidewalls and thus open structures
`for easier dielectric filling. The idea of dielectric deposition
`followed by argon sputter-etch and a second dielectric
`deposition for gap fill was conceived' and was later
`described in the literature [57, 58].
`
`"Dep-etch"process for intermetal dielectric gap filling
`The dep-etch process (deposition followed by argon
`sputter-etching) can be illustrated with a simple three-step
`sequence. Sputter-etching in argon physically removes
`oxide from all surfaces by ion bombardment. Faceting
`occurs, since the sputter-etching rate depends on the angle
`of argon ion incidence and is faster at the top corner of the
`oxide. Backscattering results in the deposition of a small
`amount of the oxide on the sidewalls, as shown in Figures
`4(a) and 4(b). For optimum filling, the reduction of oxide
`thickness should be about 10% of the height of the line.
`The taper should extend from the top of the oxide to the
`bottom of the oxide that lies between the lines. Sufficient
`oxide should be deposited so that the sputter-etching does
`not extend to the corners of the underlying lines; the oxide
`thickness should be about five times that removed by
`sputter-etching. The etching tapers the sidewalls to the
`bottom of the gap such that the final deposition fills the
`space easily [Figure 4(c)].
`The dep-etch process fills the narrow spaces but does
`not leave a planar surface. In many applications, it is
`
`1 W. J. Cote, unpublished internal communication, IBM Corporation, Essex
`Junction, VT, February 1984.
`
`After PECVD TEOS oxide deposition
`
`After sputter-etching in argon
`
`••:••.
`
`..
`
`'
`
`.
`
`•
`
`'•••
`
`' ; « 4 } i . f ^ . * . K . v « - . * ;i
`
`tluee-step
`a
`formcU b)
`section of PECVD
`cross
`SEM
`dcp-ctch-dep process: (a) PECVD oxide after deposition, (b)
`argon sputter-etching, and (c) a second PECVD oxide deposition.
`The samples used for (a) and (b) were decorated with KOH; that
`used for (c) was highUghted with 7;1 buffered HF to deUneate the
`etched layer and redeposited oxide on the sidewalls.
`
`necessary to globally planarize the dielectric prior to
`fabricating the next metal wiring level. For example,
`planarity is important when fabricating tungsten studs.
`
`441
`
`IBM J. RES. DEVELOP. VOL. 39 NO. 4 JULY 1995
`
`D. R. COTE ET AL.
`
`Elm Exhibit 2133, Page 5
`
`

`
`Relative thickness
`6
`5
`4
`3
`2
`1
`
`—•
`
`Typical experimental profiles (shown schematically) of SB-
`deposited THCVD TEOS-ozone oxides of different thicknesses in
`the vicinity of the edge of a metal line. The use of a thicker oxide
`results in a shallower slope after etch-back. From [50], reproduced
`with permission.
`
`since nonplanar areas in the oxide are filled with tungsten
`after metal CMP or etching by RIE. Therefore, the
`intermetal dielectric for the initial version of the 4Mb
`DRAM product evolved into a three-step dep-etch
`process: a dep-etch-dep of PECVD silane oxide followed
`by oxide CMP for planarization. (See below for comments
`regarding the later version of the product.)
`
`% 16Mb DRAM product
`For almost a decade, dep-etch multistep sequences have
`been the primary means to eliminate voids between
`minimum-space lines. Initially, the dep-etch process
`was demonstrated at IBM using PECVD silane oxide
`deposition on one tool and argon sputter-etching on a
`separate tool. During the early manufacturing of the 4Mb
`DRAM product, this multistep process was implemented
`in a single-chambered batch tool. Since the tool was not
`automated from a loading and cleaning perspective,
`multistep processing in the same chamber was difficult.
`It became evident that the use of a multichamber cluster
`tool would improve cycle time because of its automated
`handling features, and would reduce defect density
`(because of chamber dedication for deposition and argon
`sputtering processes). Therefore, a clustered tool was
`sought to meet the dielectric fill requirements for the 4Mb
`DRAM product and beyond. In 1987, a single-wafer,
`multichamber cluster tool [59] capable of performing both
`deposition and etching processes was introduced into the
`16Mb DRAM (125-mm-diameter wafers) development line
`and soon afterward into the 4Mb DRAM (200-mm-diameter
`wafers) manufacturing line.
`
`442
`
`This single-wafer cluster tool also made possible the
`development of a high-quality TEOS-based PECVD oxide.
`
`This came about because a single-wafer chamber permits
`the use of relatively high power densities, which in turn
`facilitates complete reaction of the TEOS and oxygen to
`silicon oxide. Early attempts at TEOS-based silicon oxide
`deposition in batch tools resulted in the formation of low-
`quality oxides, mainly because of the use of lower power
`density levels. TEOS-based PECVD oxide provided a
`marked improvement in film conformaHty over silane-
`based PECVD films (about 15-20%).
`Additionally, low-temperature, thermally deposited
`TEOS films deposited by the reaction of TEOS and ozone
`at 40-60 torr could be deposited in the same chamber.
`We refer to this process as the thermal (THCVD)
`TEOS-ozone process, although it is sometimes referred
`to in the literature as the low-pressure (LPCVD)
`TEOS-ozone process. THCVD TEOS-ozone films
`showed excellent results in step coverage: nearly 100%
`conformality [1]. Silicon oxide films deposited by
`organosilicon and ozone precursors have been reported
`since 1971 [28], but several years were required before the
`process became more widely accepted, since the quality
`of the films obtained was not as good as that of those
`obtained using PECVD TEOS. THCVD TEOS-ozone
`films have lower deposition rates and higher wet-etching
`rates, and exhibit tensile stresses compared to PECVD
`films [1]. In addition, THCVD TEOS-ozone films are
`more hygroscopic than PECVD films. Nevertheless, their
`excellent conformality made them desirable for gap filling
`and therefore warranted further testing for an intermetal
`dielectric application.
`
`intermetal
`
`A PECVD TEOS/TEOS-ozone "sidewall spacer"
`dielectric process
`The tighter pitch for the 16Mb DRAM product (1.4-/Ltm
`pitch, line width = 0.6 iim, line spacing = 0.8 /un) placed
`a high demand on the intermetal dielectric process. An
`improved intermetal dielectric process developed using
`both the CVD and etching capabilities of the cluster tool
`was implemented in the 16Mb DRAM process [60]. By
`using both PECVD and THCVD TEOS-ozone oxide fUms
`with argon sputter-etching and anisotropic oxide etching, a
`high-quality, void-free, partially planarized intermetal
`dielectric was developed. The first two steps in the
`intermetal dielectric process include a PECVD TEOS
`oxide layer that is deposited over the underlying wiring
`layer and subsequently faceted by argon sputter-etching. The
`PECVD TEOS oxide is in compressive stress (=1.0 x 10
`dynes/cm^). Moderately compressive oxide films are
`desirable for passivating and insulating layers because they
`resist cracking and minimize stress-induced voiding in the
`Al(Cu) interconnect layers [61]. Next, a thick layer (at
`least 5000 A thick) of THCVD TEOS-ozone oxide is
`deposited and fills the gaps. Since the electrical and
`
`D. R. COTE EX AL.
`
`IBM J. RES. DEVELOP. VOL. 39 NO. 4 JULY 1995
`
`Elm Exhibit 2133, Page 6
`
`

`
`Metal
`
`7
`
`a) After post 1st metal patterning
`
`d) After THCVD oxide deposition
`
`PEC\?D oxide
`
`i^T^vir
`
`b) After initial PBCVD oxide deposition
`
`e) After oxide etchback
`
`THCVD oxide
`
`THCVD oxide
`
`PECVD oxide
`
`c) After argon sputter-etching
`
`f) After final PECVD oxide deposition
`
`j
`I
`
`Summary of the PECVD TEOS/THCVD TEOS-ozone "sidewall spacer" intermetal dielectric process. From [60], reprodticed with
`permission.
`
`physical properties of THCVD TEOS-ozone oxide are
`generally poorer than those of PECVD TEOS oxide, it is
`desirable to remove most of the film with an anisotropic
`CF^/Oj etch-back. All of the THCVD TEOS-ozone oxide
`is removed from the horizontal surfaces; it is left in the
`minimum spaces and as spacers on the sidewalls of the
`metal lines. These sidewall spacers determine the slope of
`the dielectric over metal lines: An increase in the initial
`THCVD TEOS-ozone oxide thickness produces shallower
`slopes after etch-back, as shown in Figure 5. The final
`layer of PECVD TEOS oxide completes the total desired
`intermetal dielectric thickness. This intermetal dielectric
`process provides a smoothed, but not planar, surface
`between the first- and second-metal layers. Since the
`dielectric is not planarized, the slope of the dielectric over
`the metal lines is critical. If the dielectric slope is too
`steep, metal "stringers" form in the valleys between the
`metal lines when the next metal wiring level is etched,
`causing electrical shorts. A summary of the intermetal
`dielectric process sequence is shown in Figure 6.
`
`Dep-etch PSG for polysilicon-metal interlevel dielectric
`The use of titanium silicide junctions in the 16Mb DRAM
`product placed restrictions on the passivation process.
`Reflow temperatures for PSG and BPSG (greater than
`lOWC and 800°C, respectively) are high enough to cause
`agglomeration of the titanium silicide [11]. Instead, PSG
`could be deposited by PECVD (with TEOS, oxygen,
`and trimethylphosphite) in the multichamber tool and
`incorporated in a dep-etch process, permitting the use
`of PSG to fill the gaps. The availability of oxide CMP
`eUminated the need tor reflow. The 16Mb DRAM interlevel
`dielectric process became a low-temperature PECVD PSG
`dep-etch in the multichamber tool, followed by CMP
`planarization [62].
`The 16Mb DRAM product required the use of a five-step
`dep-etch-dep-etch-dep to fill the critical gaps between
`gate conductor lines. The first PSG deposition thickness
`was determined by the maximum thickness that did not
`pinch off the smallest gap. This was followed by an argon
`sputter-etching that tapered the PSG to the corner of the
`
`443
`
`IBM J. RES. DEVELOP. VOL. 39 NO. 4 JULY 1995
`
`D. R. COTE ET AL.
`
`Elm Exhibit 2133, Page 7
`
`

`
`SEM cross sections illustrating a five-step dep-etcli of PECVD PSG on a silicon trench monitor: (a) Sample decorated with KOH to
`decorate the silicon, (b) Sample decorated with 7:1 buffered HF to indicate the dep-etch layers and proximity of each layer to the comer of
`the structure. The first two layers must be sputter-etched nght to the comer of the structure m order to achieve desired gap fiUing.
`
`.H|
`
`•*" itiniffilii' 1 «« 1
`
`i^
`
`i k . t^
`
`^ ^ ^^
`
`Spacings
`(jam) 0.20 0.25
`Aspect 3.0
`2.4
`ratios
`
`0.30
`2.0
`
`0.35
`1.7
`
`0.40
`1.5
`
`0.45
`i.3
`
`0.55
`1.1
`
`0.65
`0.9
`
`corner of the gate conductor. The clustered interlevel
`dielectric process also includes a thin PECVD silicon
`nitride film deposited before the PSG by the reaction of
`silane, nitrogen, and ammonia at 480''C. This nitride acts
`as a mobile ion and diffusion barrier. An illustration of a
`five-step dep-etch of PECVD PSG (without a nitride
`barrier) is shown in Figure 7.
`
`'-M
`
`Five-step dep-etch of PECVD PSG over the gate conductor. This
`SEM was taken of a sample containing different gate conductor
`spaces in order to ascertain when voids begin to form. Voids are
`formed in spaces less than 0.45 ^m wide.
`
`gate conductor. This sequence was repeated: The second
`PSG deposition was again kept tliin enough to avoid
`closing the smallest gap, and then faceted again to the
`
`444
`
`% 64Mb DRAM product
`Even a five- or seven-step PECVD PSG dep-etch process
`will not flu in the sub-quarter-micron minimum spaces
`between the gate conductor lines in the 64Mb DRAM
`product. Though the nominal aspect ratio is 3:1, design
`rules allow a worst case of 5:1. Large voids form in the
`PSG for spaces less than 0.45 fim, as indicated in Figure 8.
`Figure 9 shows how these voids cause problems in the
`subsequent damascene metal wiring. The first step in
`damascene wiring fabrication is to planarize the PSG with
`CMP. Next, an undoped oxide is deposited on top of the
`PSG, patterned with resist, and etched. Since the PSG
`void is close to the top of the PSG surface, the void can be
`intersected during the etching (there is an over-etch into
`the PSG). The CVD tungsten used for the metal wiring fills
`
`D. R. COTE ET AL.
`
`IBM J. RES. DEVELOP. VOL. ,19 NO. 4 JULY WW
`
`Elm Exhibit 2133, Page 8
`
`

`
`/^.•;xx<X'X---v-,"%"^\-
`
`PECVD PSG
`
`PECVD PSG
`
`Titanium silidde
`
`Tungsten
`
`Undoped PECVD oxide
`
`Polysilicon
`
`PECVD PSG
`
`Metal lines
`
`(e)
`
`Schematic of how a PSG void between gate cotiductor hnes causes a short to form: (a) after five-step PECVD PSG dep-etch process; (b)
`after PSG planarization and intermetal dielectric deposition, (c) after patterning (via hthography and RIE); (d) after tungsten CVD and CMP,
`filling the void as well. The SEM in (e) shows an actual metal short formed in the PSG void. The oxide that normally surrounds and isolates
`the metal lines has been removed to reveal the short.
`
`j
`I
`
`445
`
`IBM J. RES. DEVELOP. VOL. 39 NO. 4 JULY 1»5
`
`D. R. COTE ET AL.
`
`Elm Exhibit 2133, Page 9
`
`

`
`0.85
`
`0.7
`
`SACVD PSG
`
`PECVD PSG
`
`Intralevel shorts yield as measured on a comb/serpentine test
`structure for an SACVD PSG dielectric vs. a five-step PECVD
`PSG dep-etch dielectric. Each bar represents one wafer; all
`wafers were from the same lot.
`
`'^iil^»*=
`
`, - ^ ^- s<^p!'\ /if^fe-.
`
`SEM cross section of layer formed by a three-step SAPSG/argon
`sputter/PECVD PSG fill sequence. Small buried voids have formed
`in the PSG. The heights of the voids in the very small spaces
`depend on the sidewall angle of the gate conductor line. The more
`vertical the line, the taller the void.
`
`the opened void and causes an intralevel short. Figure 9
`includes an SEM micrograph of an actual intralevel short
`formed in a PSG void.
`
`• A phosphorus-doped TEOS-ozone process for interlevel
`dielectric fill
`TEOS-ozone CVD processes produce better gap fill than
`PECVD processes [1]. Also, higher deposition pressures
`improve gap fill for TEOS-ozone processes [28, 29]. As
`expected, a thermal TEOS-ozone process for producing
`PSG results in better gap fill than does a PECVD process.
`A phosphorus-doped TEOS-ozone film deposited at 600
`
`446
`
`torr—SACVD PSG—was developed [63] for the 64Mb
`DRAM interlevel dielectric. The process became one
`involving a multistep PSG sequence consisting of a thin
`SACVD PSG deposition to fill the minimum spaces,
`followed by an argon sputter-etching step to facet the film
`in the larger spaces. The SACVD PSG was then capped
`with a thick deposition of PECVD PSG and planarized by
`CMP. The above sequence was chosen to minimize the use
`of SACVD PSG, since moisture absorption is a known
`concern for TEOS-ozone films unless the films are
`densified or capped with a PECVD film [64]. The intralevel
`shorts yield for the SACVD PSG fill is significantly higher
`than for the five-step PECVD PSG process, as indicated in
`Figure 10. Physical failure analysis of the electrical fails
`confirmed that the shorts for the five-step PECVD PSG
`process were due to voids in the PSG.
`SACVD PSG fills the high-aspect-ratio structures for the
`64Mb DRAM sufficiently, but not without the formation
`of small buried voids between the minimum-space gate
`conductor lines, as shown in Figure 11. The voids form
`when sidewall angles are greater than 82-84°. It is
`important to note that these small voids are not a problem
`if they are buried deeply enough (at least 2000 A below
`the top of the gate conductor), because of the fabrication
`technique for the contacts to gates and diffusions for the
`64Mb DRAM product chips. The contacts are borderless
`with respect to the gates and diffusions, a key design
`feature that permits formation of a dense array of storage
`cells [65, 66] {about 40% DRAM cell area is saved). The
`contacts (tungsten studs) are fabricated using a sacrificial
`polysilicon mandrel process [67]. Contact holes are etched
`in the polysilicon mandrel, the holes are filled (deposition
`+ CMP) with tungsten,