Purposes of Three-Dimensional Circuits
`Akira Terao and Fernand Van de Wiele
`
`Introduction
`
`Three-dimensional (3-D) circuitry is a recognized con­
`cept. With the advent of silicon-on-insulator (SOI) tech­
`nologies, this idea is being realized using techniques such
`as laser recrystallization of polysilicon, which allows fab­
`rication of active devices stacked in two or more layers.
`Since silicon is a well-known microelectronic material,
`progress has been very fast and some laboratories have al­
`ready succeeded in producing three-dimensional circuit
`cells [l]-[3].
`In order to focus activity and rationally optimize prod­
`ucts, technologists need to know the types of circuits re­
`quired. This paper examines the problem from several
`points of view and tries to answer three fundamental ques­
`tions: (1) What are the main advantages of 3-D circuitry?
`(2) What kind of circuits will yield best advantages? (3)
`Which technological problems have priority?
`
`Topology and Metrology
`
`It is commonly believed that three-dimensionality will
`give rise to entirely new circuits that could never be real­
`ized in two dimensions. We can see immediately from very
`simple considerations that this is, unfortunately, not true.
`Given any 3-D network, it is easy to give a two-dimen­
`sional (2-D) representation of it with the help of normal
`projection [Fig. 1(a)]. But, in most cases, this figure will
`contain some crossings between branches, creating unde­
`sirable contacts. However, we observe that only intersec­
`tions between two branches are actually inevitable, while
`crossings between more branches can always be decom­
`posed into several binary crossings [Fig. 1(b)]. This implies
`that any circuit, however complex, can be realized in 2-D,
`if two wires are allowed to cross without contact [Fig. 1(c)].
`This is precisely the case with conventional integrated cir­
`cuits—at a minimum, polysilicon and aluminum intercon­
`nection layers isolated from each other are present on any
`VLSI (very large scale integrated) (MOS) circuit. In fact,
`this could be considered to be a 2.5-D circuitry.
`We come to the conclusion that, from a topological point
`of view, three-dimensionality offers no gain compared to
`present structures. Consequently, advantages of 3-D cir­
`cuits are found only in improvements of existing 2-D cir­
`cuits. However, these improvements could make possible
`circuits that were unrealizable because of practical limita­
`tions such as circuit size.
`A. L. Rosenberg [4] has proven by means of network
`theory that embedding of intricated networks is simplified
`by three-dimensionality. The gain in density for these cir­
`cuits is illustrated in Fig. 2. Obviously, the occupied vol­
`ume is smaller and the interconnection lengths are shorter
`in 3-D than in 2-D. Another example of evident improve­
`ment is given by circuits wherein a series of operations is
`performed simultaneously on each element of a matrix (Fig.
`3). A well-known application of this type among 3-D re-
`
`(a) normal
`in two and three dimensions:
`Interconnection
`Fig. 1
`projection onto a 2-D plane, (b) multiple-wire
`crossing decomposed
`into
`several binary crossings and (c) cube of random crossings,
`realizable in
`2-D if crossing without connection
`is possible.
`
`searchers is the photomatrix with an integrated processor
`for each pixel.
`An increase of packing density leads to a decrease of
`parasitic capacitances and, hence, to an increase in speed.
`Thus, three-dimensional circuits are serious candidates for
`high-speed applications, combined with a sophisticated in­
`formation path.
`
`Architecture
`
`The complexity of a network, mentioned previously, can
`be measured by its "fractal dimension," which is its in­
`trinsic dimension, independent of any practical embed­
`ding in 2- or 3-D. This concept can be described as follows.
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`NOVEMBER 1987
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`It is clear that a circuit with a higher fractal dimension D
`needs a more sophisticated interconnection network and
`is easier to conceive in a 3-D structure than in 2-D. Thus,
`3-D circuitry is especially advantageous for highly parallel
`architectures (parallel multiplier, image or signal proces­
`sor, . . .) and hence, again, for high-speed applications.
`Independent of the preceding discussion, a practical limit
`exists to the number of contact pads Ρ or the number of
`wires that can be bonded on a small chip. From this point
`of view, the best-suited circuits are those whose fractal di­
`mension is 1 and parallelism 0: P 0 = k · G° = const. Three-
`dimensional circuits are thus penalized, since they multi­
`ply G by the number of layers without increasing the num­
`ber of contact pads. One solution proposed to this problem
`is the use of external contacts without pads, i.e., sensors.
`Again, photomatrices appear to be good candidates for
`3-D integration.
`A second solution lies in multiplexing the input/output
`(I/O) operations. This is, of course, in opposition to the
`concept of highly parallel architecture. A fair compromise
`can be achieved using short I/O operations combined with
`long parallel computations. Such circuits need to be com­
`plete enough to operate for a long time without contact to
`external circuits. This increases the size of the system in­
`tegrated on a single chip and, hence, the number of
`gates G.
`A further increase of G leads to another reduction of P.
`This appears somewhat inconsistent with Rent's rule, but
`is explained very simply. As size increases, a system pro­
`cesses more and more information in its operations and
`needs less information from the external world. Therefore,
`the apparent parallelism of the circuit is reduced, although
`the internal parallelism can be very high, that is, several
`circuits with many I/Os can be assembled into a larger one
`needing few I/Os. This tendency has been pointed out by
`Ferry [5], who noticed that while the parallelism of pre­
`vious circuits was near two-thirds, recent large circuits have
`a much smaller value, about 0.21. He calls the earlier cir­
`cuits highly partitioned ones, and the latter functionally
`partitioned ones.
`Three-dimensional circuitry is thus well suited to very
`large systems. Parallelism in those large systems can be
`achieved by two means: 3-D arrangement of 2-D parts [Fig.
`4(a)] or 2-D arrangement of 3-D modules [Fig. 4(b)]. Of
`course, in both cases, the final product looks like a super­
`position of 2-D SOI layers, but conceptually, a photomatrix
`with built-in digitizer circuits and memory, for example,
`can be considered more like an array of vertical modules.
`Any combination of the two structures is also possible, for
`example, a photomatrix with a digitizer circuit for each
`pixel and a selection circuit for the whole [3]. Note that the
`
`(a) 3-D
`of circuits:
`arrangement
`functional
`Fig. 4 Alternate
`arrangement of 2-D circuits and (b) 2-D arrangement of 3-D circuits.
`
`IEEE CIRCUITS AND DEVICES MAGAZINE
`
`of a collection of binary connections
`Implementation
`Fig. 2
`more densely packed in 3-D.
`
`that become
`
`Fig. 3 A higher packing density for parallel operation
`3-D
`configurations.
`
`is obtained by
`
`Geometrically, we characterize a 3-D object by its vol­
`ume V and its external surface S, and the following relation
`between these two quantities: S = kV 2^3. Drawing a par­
`allel between geometrical objects and networks, we can re­
`late the volume V to the number G of active elements or
`gates, and the outer surface S to the number of contacts
`with the external world or the number ( P 3 ) of contact pads.
`The preceding relation then becomes: P 3 = /cG 2 / 3. The same
`argument holds for the surface S and the perimeter L of
`2-D objects, leading to the following relations: L =
`/ c S 1 /2
`and P 2 = /cG 1 / 2. Generalizing, we obtain the following re­
`lation, known as Rent's rule: P D = kGv, where ρ is the de­
`gree of parallelism of the circuit and it is between 0 and 1,
`given by ρ = 1 - 1/D, where D is the fractal dimension.
`When a new dimension is added to a circuit, it can be used
`to replace the time dimension, allowing previously multi­
`plexed operations to be done simultaneously on a vector,
`thus increasing the parallelism p.
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`two types of architecture could require quite different con­
`ception methodologies. Thus, it is easier to make the ver­
`tical interconnection sites in the top and the bottom layers
`meet in small 3-D cells, while design of 2-D modules is
`more customary.
`
`Yield
`
`Realization of large systems gives rise immediately to the
`problem of yield. From this point of view, we compare
`3-D circuits to their unstacked 2-D equivalents. The yield
`of a usual 2-D circuit can be written as η 2 = η p\ * T)t, where
`77ph is the yield of each photolithography (the most critical
`step), m the number of masks, and η ί the yield of all other
`technological steps, primarily due
`to accidents during
`manufacture.
`For a 3-D equivalent, consisting of L layers with surface
`SIL and GIL active elements per layer, the yield is η 3 =
`Vph ' Vt ' Vsou where r / S OI is the yield of technological steps
`for the upper layer and is lower than rj,. But
`is compa­
`rable to ry ph of 2-D equivalent, for it accounts for the same
`total area S. rjph can even be greater since large areas of
`photolithography are divided into several smaller ones.
`Three-dimensional circuits are, in this sense, an alternative
`to wafer scale integration.
`Three-dimensional circuits are also an alternative to di­
`mensional scaling. Problems of resolution, technology, and
`electrical characteristics ultimately limit scaling, but stack­
`ing of layers allows further integration. Again, we see that
`3-D possibilities are suited to very large systems. How­
`ever, we note that, in contrast to normal scaling, power
`consumption is not reduced, other than the reduction due
`to the decrease of parasitic capacitances already men­
`tioned.
`The problem of yield ultimately forces the use of redun­
`dant and reconfigurable circuits, wherein defective parts
`are replaced by changing the interconnection network with
`the aid of fuses or logical circuits, for instance [6]. Again,
`3-D circuitry is an advantage since those circuits need both
`increased space and sophisticated networks. Examples are
`a usual 2-D circuit with an additional active layer of spare
`modules and interconnection networks or entirely parallel
`double-layer circuits with some vertical comparison blocks
`generating error codes.
`
`Summary
`
`The advantages of three-dimensional circuitry are a re­
`duction of interconnection length for high- (fractal) dimen­
`sional circuits and resulting in an increase of operation
`speed and a decrease of power consumption. The in­
`creased integration scale further reinforces this effect by
`reducing the number of space- and time-consuming de­
`vices, such as output buffers and buses. Three-dimen­
`sional circuits are particularly interesting for very large,
`complex, and complete systems having high-dimensional
`structure and/or including high-dimensional modules in
`high-speed applications. Therefore, technological devel­
`opments for three-dimensionality must pursue high per­
`formance at the same time.
`
`References
`
`[1] S. Akiyama, S. Ogawa, M. Yoneda, N. Yoshii, and Y. Terui,
`''Multilayer CMOS Device Fabricated on Laser Recrystallized
`Silicon Islands," 1EDM Tech. Dig., pp. 352-355, Dec. 1983.
`[2] Y. Inoue et al., "A Three-Dimensional Static RAM," IEEE
`Electron Device Lett., vol. EDL-7, pp. 327-329, May 1986.
`[3] K. Mitsuhashi, "Etch Back Planarization Technique and Its
`Application to Multilayer Devices," Proc. 4th FED Symp., pp.
`251-267, July 1985.
`[4] A. L. Rosenberg, "Three-Dimensional VLSI: A Case Study,"
`/. Ass. Comput. Mach., vol. 30, pp. 397-416, July 1983.
`[5] D. K. Ferry, "Interconnection Lengths and VLSI," IEEE Cir­
`cuits and Devices Mag., vol. 1, pp. 39-42, July 1985.
`[6] W. R. Moore, "A Review of Fault-Tolerant Techniques for the
`Enhancement of Integrated Circuit Yield," Proc. IEEE, vol. 74,
`pp. 684-698, May 1986.
`
`Akira Terao
`
`Akira Terao received the degree in applied physics engineering
`from the Catholic University of Louvain, Louvain-la-Neuve, Bel­
`gium, in 1985. Currently, he is pursuing a Ph.D. degree in the
`Microelectronics Department of that university. His research in­
`terests are in selective laser recrystallization of SOI and 3-D inte­
`gration. He is a Research Assistant for the National Fund for Sci­
`entific Research, Belgium.
`
`Fernand Van de Wiele .
`
`Fernand Van de Wiele received the M.S. degree in mathematics
`and physics, and the Ph.D. degree from the University of Ghent,
`Ghent, Belgium, in 1959, 1961, and 1965, respectively.
`He was associated with the University of Ghent as an Assistant
`in Research in ionic crystals. Since 1966, he has been a Professor
`at the Catholic University of Louvain, Louvain-la-Neuve, Bel­
`gium, and Head of the Section of Physics and Electronics of Semi­
`conductor Devices in the Microelectronics Department.
`
`NOVEMBER 1987
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