United States Patent
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`Bertin et al.
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`[19]
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`[54] Tl-[REE DIIWENSIONAL MULIICHIP
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`PACKAGE ME’;-gong op FABRICATION
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`US005270261A
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`[in Patent Number:
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`[45] Date of Patent:
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`5,270,261
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`Dec. 14, 1993
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`5,064,77l 11/ l99l Solomon ................... 148/DIG. 135
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`5,071,792 12/1991 Van Vonno et al
`...... 437/974
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`437/974
`2/1992 Delgado etal.
`5,091,331
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`5,162,254 11/1992 Usui et al. ................. 148/DIG. 135
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`”"’?’“’>’ E’‘‘'’"’f'‘’’—B'‘‘‘’¥ 5' H°‘?"‘
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`Assistant Exammer—Kevin M. Picardat
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`Attorney, Agent, or Firm—Heslin & Rothenberg
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`[57]
`Ansrmcr
`A fabrication method and resultant three-dimensional
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`multichip package having a densely stacked array of
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`semiconductor chips interconnected at least partially by
`means of a plurality of metallized trenches are dis-
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`closed. The fabrication method includes providing an
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`integrated circuit chip having high aspect ratio metal-
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`lized trenches therein extending from a first surface to a
`second surface thereof. An etch stop layer is provided
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`proximate the termination position of the metallized
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`trenches with the semiconductor substrate. Next the
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`integrated circuit device is affixed to a carrier such that
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`the surface of‘the supporting substrate is exposed and
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`substrate is thinned from the integrated circuit deyice
`until exposing at least some of the plurality of metallized
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`erein.
`ec nca con c can
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`the active layer of the integrated circuit chip via the
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`::”;;::‘hm°‘h°d and ‘h‘ ’°5““““‘ m“m°hip P“°k"‘g° “’°
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`15 Claims, 8 Drawing Sheets
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`Assignee:
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`Inventors: Claude L. Bertin; Pm! A. Flmr, Sn,
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`both of South Burlington; Howard L.
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`Halter, Oolchester; Gordon A. Kelley,
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`Jr” Essa Junction; wmem B_ “'1
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`dc, Hoe"! Jericho; Funds R_
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`White, Essex, all of Vt.
`International Business Machines
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`C0|'P0|'fli0fl, Afmonh N-Y-
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`A L N _, 965 728
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`_pp
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`Flkdi
`Oct 23v 1992
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`Rellled U5» APP1l°“|0n D3“
`Division of 5“, No_ 750,041, sep, 13, 1991, pat N9,
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`5,202,754.
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`3: %5 """""""""""""""""""
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`437/225; 437/974; 148/’DIG. 135’
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`437/203, 209’ 228’ 974;
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`148/DIGJ35
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`[75]
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`R°f°"°“°°5 Clted
`U.S. PATENT DOCUMENTS
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`9/1986 Yasumoto et a1. .................. 437/zos
`4,612,083
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`..........
`4,818,728 4/1989 Rai et al.
`437/974
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`4,879,258 ll/1989 Fisher .......
`437/974
`4,902,641
`2/1990 Koury, Jr.
`437/974
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`MICRON ET AL. EXHIBIT 1075
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`MICRON ET AL. EXHIBIT 1075
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`U.S. Patent
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`Dec. 14, 1993
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`Sheet 2 of 8
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`MICRON ET AL. EXHIBIT 1075
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`MICRON ET AL. EXHIBIT 1075
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`U.S. Patent
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`Dec. 14, 1993
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`MICRON ET AL. EXHIBIT 1075
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`U.S. Patent
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`Dec. 14, 1993
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`Sheet 5 of 8
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`MICRON ET AL. EXHIBIT 1075
`Page 6 of 14
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`US‘. Patent
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`Dec. 14, 1993
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`Sheet 6 of 3
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`MICRON ET AL. EXHIBIT 1075
`Page 7 of 14
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`U.S. Patent
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`Dec. 14, 1993
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`5,270,261
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`M.N/S_HBMYWSNEDEGAROTS
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`MICRON ET AL. EXHIBIT 1075
`Page 9 of 14
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`1
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`THREE DIMENSIONAL MULTICHIP PACKAGE
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`METHODS OF FABRICATION
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`5,270,261
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`10
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`This application is a division of application Ser. No.
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`07/760,041, filed Sep. 13, 1991, now U.S. Pat. No.
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`5,202,754.
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`BACKGROUND OF THE INVENTION
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`1. Technical Field
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`The present invention relates in general to high den-
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`sity electronic packaging which permits optimization of
`the number of circuit elements to be included in a given
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`volume. More particular, the present invention relates
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`to a method for fabricating a three-dimensional multi-
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`chip package having a densely stacked array of semi-
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`conductor chips interconnected at least partially by
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`means of a plurality of metallized trenches in the semi-
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`conductor chips.
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`2. Description of the Prior Art
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`Since the development of integrated circuit technol-
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`osy. computers and computer storage devices have
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`been made from wafers of semiconductor material com-
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`prising a plurality of integrated circuits. After a wafer is
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`made, the circuits are typically separated from each
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`other by dicing the wafer into small chips. Thereafter,
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`the chips are bonded to carriers of various types, inter-
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`connected by wires and packaged. Along with being
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`time consuming, costly and unreliable, the process of
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`physically attaching wires to interconnect chips often 30
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`produces undesirable signal delays, especially as the
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`frequency of device operation increases.
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`As an improvement over this traditional technology,
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`stack or packages of multiple semiconductor chips have
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`become popular, e.g., reference U.S. Pat. No. 4,525,921,
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`entitled “High-Density Electronic Processing Pack-
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`age—Structure and Fabrication.” FIG. 1 depicts a typi-
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`cal semiconductor chip stack, generally denoted 10,
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`consisting of multiple integrated circuit chips 12 which
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`are adhesively Secured together. A metallization pattern
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`14 is provided on one or more sides of stack 10 for chip
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`interconnections and for electrical connection to cir-
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`cuitry external to the stack. Metallization pattern 14
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`includes both individual contacts 16 and bussed
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`contacts 18. Stack 10, with metallization 14 thereon, is
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`positioned on the upper surface 21 of a substrate 20
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`which has its own metallization pattern 22 thereon.
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`Although superior to the more conventional technique
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`of individually placing chips on a board, substrate or
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`multichip carrier, both in terms of reliability and circuit
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`performance, this multichip stack approach is still sus-
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`ceptible to improvement in terms of density and reduc-
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`tion in the length of chip wiring. Obviously, any im-
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`provements in such package characteristics will pro-
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`duce a lower cost, lower power higher density, reliabil-
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`ity and thereby providing better performing device.
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`SUMMARY OF THE INVENTION
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`Briefly described, the present invention comprises in
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`one aspect a multichip packaging method which in-
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`cludes the
`step of providing an integrated circuit
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`device having a first, upper surface and a second, lower
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`surface in substantially parallel opposing relation. The
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`device, which may comprise a semiconductor chip or
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`wafer, has an active layer adjacent to the first surface
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`and a substrate adjacent to the second surface. The
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`device further
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`trenches therein which extend from the first surface
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`through the active layer and partially into the substrate.
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`At least some of the plurality of metallized trenches are
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`in electrical contact with the active layer of the inte-
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`grated circuit device. The packaging method further
`includes affixing this integrated circuit device to a car-
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`rier such that the second surface thereof is exposed,
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`allowing the thinning of the substrate of the integrated
`circuit device until exposing at least some of the plural-
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`ity of metallized trenches therein. Electrical contact can
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`thus be made to the active layer of the integrated circuit
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`device via the exposed metallized trenches. Additional
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`integrated circuit devices are preferably added to the
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`stack in a similar manner. As each layer of circuit de-
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`vices is added electrical contact to at least some of the
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`exposed metallized trenches of the previous layer is
`made. In another aspect of the present invention, a
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`novel multichip package system, resulting from applica-
`tion of the above processing method, is provided. Spe-
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`cific details of the method and the resultant package are
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`described in detail and claimed herein.
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`The present
`invention advantageously produces a
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`multichip package having high integrated circuit den-
`sity. Wiring solutions are presented for very dense
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`packaging I/O connects, and three-dimensional vertical
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`and horizontal wiring is discussed. Further, techniques
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`to limit the power dissipation of particular functions in
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`a dense multichip package are provided. In accordance
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`with the processing approach of the present invention,
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`a multiple chip package can be created in the same
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`space previously required for a single integrated circuit
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`chip. Further, fabrication of the individual wafers/chips
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`to be assembled into the multichip package remains
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`consistent with high volume wafer manufacturing.
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`The subject matter which is regarded as the present
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`invention is particularly pointed out and distinctly
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`claimed in the concluding portion of the specification.
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`The invention, however, both as to organization and
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`method of practice, together with further objects and
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`advantages thereof, may best be understood by refer-
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`ence to the following detailed description taken in con-
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`junction with the accompanying drawings in which:
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`FIG. 1 is an exploded perspective view of a basic
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`prior art multichip package;
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`FIGS. 2a & 2b illustrate the difference in packaging
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`density between a multichip package fabricated in ac-
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`cordance with existing techniques (FIG. 2a) and a mul-
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`tichip package fabricated pursuant to the present inven-
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`tion (FIG. 2b);
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`FIGS. 3a-31' are partial cross-sectional elevational
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`depictions of structures obtained at various processing
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`steps in accordance with one multichip package fabrica-
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`tion embodiment pursuant to the present invention;
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`FIGS. 4a—4d depict various electrical lead wiring
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`options from or through an integrated circuit device
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`pursuant to the present invention;
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`FIGS. 5a & 5b illustrate the different requirements in
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`access surface wiring for DRAM and SRAM configu-
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`rations for a multichip package constructed in accor-
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`dance with existing techniques (FIG. 5a) and for a mul-
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`tichip package constructed in accordance with the pres-
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`ent invention (FIG. Sb); and
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`FIG. 6 graphically depicts an example of the different
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`integrated circuit packaging densities obtainable using
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`Small Outline J Lead (SOJ), Cube (FIG. 1) and that
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`produced in the present
`invention packaging tech-
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`niques.
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`45
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`MICRON ET AL. EXHIBIT 1075
`Page 10 of 14
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`4
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`upon active layer 54. Layer 54 may comprise any con-
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`ventional bipolar, CMOS, NMOS, PMOS, etc., cir-
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`cuitry.
`Pursuant to the invention, a standard wafer is modi-
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`fied during manufacture by placing a buried etch stop
`53 below the surface of the substrate. The etch stop can
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`comprise an N+layer 53 in a P substrate 52 or a P+
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`layer 53 in an N substrate 52, both of which can be
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`fabricated by any one of several means known to those
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`skilled in the art.
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`Shown in exaggerated size in FIG. 3b are thin, deep
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`trenches 62 defined in integrated circuit device 50.
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`Trenches 62 are configured to extend slightly through
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`etch stop layer 53 into substrate 52. In a preferred em-
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`bodiment, deep trenches 62 will each have a high aspect
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`ratio of approximately 20:1, which means, for example,
`that thin trenches 62 will preferably have a width of 1
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`micrometer for a 20 micrometer deep trench. (As de-
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`scribed below, the high aspect ratio trenches 62 will
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`ultimately advantageously serve to define very small
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`interconnect dimensions.) Trenches 62 can be fabri-
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`cated pursuant to the techniques described in U.S. Pat.
`No. 4,717,448, entitled: "Reactive Ion Etch Chemistry
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`for Providing Deep Vertical Trenches in Semiconduc-
`tor Substrates,” which is hereby incorporated herein by
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`reference. Deep trenches 62 are positioned in the inte-
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`grated circuit device 50 where electrical through con-
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`nections between devices are desired once the multichip
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`package is assembled.
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`The trench sidewalls are oxidized to provide isolation
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`from the bulk silicon (such that the trenches can be used
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`for wiring without shorting the devices), with doped
`polysilicon or other conductor 64 (see FIG. 3c). The
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`device, including wiring levels, can next be completed
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`using standard processing techniques, with the layout of
`the devices (circuits) being modified so that the area 61
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`(see FIG. 3:!) where polysilicon filled trenches are posi-
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`tioned remains clear of circuitry and wiring embedded
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`within completed oxidation/connecting metallization
`layer 63.
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`Referring to FIG. 32, deep trenches 62 are next
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`reetched to remove polysilicon plugs 64, using tech-
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`niques known in the art. The trenches 62 are then filled
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`with an appropriate metal 66, e.g., tungsten Au, Cu,
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`aluminum or other suitable metal, by a chemical vapor
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`deposition CVD process, plating or other appropriate
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`means. Metallized trenches 66 will extend at
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`slightly through etch stop layer 53. Contact pads 68 of
`gold, copper or other appropriate metal are then depos-
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`ited so that they will interconnect the appropriate wir-
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`ing (not shown) on the chip to the vertically disposed
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`wiring 66 in trenches 62. The integrated circuit chips
`are then tested, thewafers diced and the good chips are
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`selected. Alternatively, the wafers may be left undiced
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`depending upon the processing path chosen. If suffi-
`cient redundancy is built into thestructure so as to
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`produce essentially a 100% yield of good chips then the
`wafers will remain undiced. Whether the wafers are to
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`be diced or remain undiced, however, they are prefera-
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`bly first mechanically thinned, for example, to at least
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`375-400 micrometers (15 mils) i.e., if not already ac-
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`complished.
`Assuming that the chips are separated, the first inte-
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`grated circuit chip 50 to be incorporated into the multi-
`chip package is flipped over and bonded to a suitable
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`carrier 70 such that the protective surface 63 of chip 50
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`is disposed adjacent the upper surface 71 of carrier 70
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`(see FIG. 3]). Chip 50 is adhesively bonded to carrier 70
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`5,270,261
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`3
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`DETAILED DESCRIPTION OF THE
`
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`INVENTION
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`the present invention comprises a
`Broadly stated,
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`method for improving the circuit density in a multichip
`package, such as stack 10 depicted in FIG. 1. FIG. 2a
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`depicts a conventional multichip stack 30 having two
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`chips, chip 1 and chip 2. Each chip has an active layer
`32 which extends within the chip a distance “x", and an
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`overall thickness “y” from an upper surface 31 to a
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`lower surface 33 thereof. Chip thickness “y” is at least
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`an order of magnitude greater than active layer thick- '
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`ness “x". For example, typically thickness “x” is within
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`the range of 5-20 micrometers, while thickness “y” is
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`more conventionally in the range of 750-850 microme-
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`ters (30 mils). However, recently the practice is to re-
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`duce thickness "y” by mechanical thinning of the sub-
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`strate in each chip to approximately 375-425 microme-
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`ters (15 mils) prior to assembly of the package. Notwith-
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`standing this mechanical reduction, the volume of the
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`useful active silicon, e.g., active layers 32, remains much
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`less than that of the total silicon. This is because the
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`silicon substrate still continues to be used for mechani-
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`cal support of layer 32 of the chip during processing.
`In comparison with the package of FIG. 2a, the semi-
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`conductor chips in a package processed pursuant to the
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`present invention have only a thin layer of substrate for
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`support of the active layer, which is illustrated in FIG.
`2b wherein two thin semiconductor chips, chip 1 and
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`chip 2, are shown. These chips are stacked in ‘a package
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`40. The active layer 42 of each chip in package 40 has a
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`thickness “x'" which, as shown, is a significant portion
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`of the chip thickness “y’”. This is in contrast to the large
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`size disparity between thickness "x” and thickness “y"
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`for the conventional package of FIG. 2a. By way of 35
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`example, thicliness “x'” may be in the 5-20 micrometers
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`range, while the overall thickness “y"‘ of each device
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`may be only 20 micrometers or less. This means that
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`when the chips are combined in a stack configuration a
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`significantly denser electronic package is produced than
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`is possible using previous stacking techniques for sepa-
`rate integrated circuit chips. In essence, processing in
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`accordance with the present invention advantageously
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`eliminates most of the excess silicon substrate in a sili-
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`con device after bonding of the device to a growing
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`multichip package.
`One example of a package fabrication process pursu-
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`ant to the present invention is described below with
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`reference to FIGS. 3a—3i.
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`Referring first to FIG. 3a, processing begins with a
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`semiconductor device 50 (preferably comprising a wa-
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`fer) having a substrate 52 and an active layer 54, which
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`is typically positioned at least partially therein. (Layer
`54 may be totally or partially defused into substrate 52
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`and/or partially or totally built up from substrate 52
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`using conventional semiconductor processing tech-
`niques known to those skilled in the art.) Layer 54 is
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`adjacent to a first, upper planar surface 56 of device 50.
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`A second, lower planar surface 58 of device 50 is posi-
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`tioned substantially parallel to first planar surface 56. A
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`dielectric layer 60, for example, SiO2, is grown over
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`active layer 54 of device 50. Although variable, sub-
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`strate 52 thickness will
`typically be approximately
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`750-850 micrometers (15 mils) prior to creation of a
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`multichip package.
`In comparison,
`the thickness of 65
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`active layer 54 may be in the range of 4-6 micrometers,
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`while the thickness of insulating layer 60 will vary, e.g.,
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`with the number of metallization levels already built
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`MICRON ET AL. EXHIBIT 1075
`Page 11 of 14
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`

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`5,270,261
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`S
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`by use of a suitable adhesive material 73, such as a poly-
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`imide. (As an alternative to carrier 70, chip 50 could be
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`bonded to a base integrated circuit chip (not shown)
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`which would have contacts mirroring the positions of
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`pads 68 of device 50 and a thickness sufficient to sup-
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`port the package, at least during assembly. Joining of
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`integrated circuit chip 50 to such a base chip could be
`by Au to Au thermal comprwsion bonding or other
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`suitable means.)
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`Next, the exposed second surface 58 of chip 50 (FIG.
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`3}) is etched in a suitable selective chemical etch such as
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`ethylenediamine, pyrocatechol, water solution, or 200:1
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`nitric acid/I-IF solution. See copending U.S. Patent
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`Application entitled “Three Dimensional Semiconduc-
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`tor Structure Formed from Planar Layers," Ser. No.
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`656,902, filed Feb. 15, 1991, Continuation of Ser. No.
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`427,679, filed Oct. 26, 1989. The chemical etch is selec-
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`tive so that etching ceases when etch stop layer 53 is
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`reached (FIG. 3g). Further, the etchant is selected so as
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`not to etch metal 66 deposited within deep trenches 62.
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`The chemical etch removes only the silicon wafer down
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`to etch stop 53 (see FIG. 3g). As shown in FIG. 3h, an
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`appropriate photo-definable polyimide 80 or other
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`bonding compound is then applied and etched to par-
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`tially reveal the metallized trenches 66 in chip 50. Prior
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`to complete curing of the polymer, Au is plated electro-
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`lessly and selectively on the metallized trench connec-
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`tions to form pads 82. If aluminum is used to metallize
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`the trenches, a suitable diffusion barrier (not shown),
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`such as Cr, is plated on the Al prior to An plating. The
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`stacking process is repeated by the respective addition
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`of integrated circuit devices (see, e.g., FIG. 31) one on
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`top of the other, each having its active layer positioned
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`adjacent to the last thinned exposed surface of the stack
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`with contact pads 68 contacting at least some of the
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`exposed metallized trenches 66 therein. Bonding of each
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`chip layer is such that the polymer and Au to Au bond-
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`ing preferably take place simultaneously.
`Should full wafer stacking be used, the process is
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`essentially the same. The wafers are subsequently diced
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`into separate multichip packages at an appropriate point
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`in the process, either when the package is complete or
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`when the cumulative yield is such as to make further
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`stacking uneconomical.
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`It will be observed that a significant advantage is
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`attained pursuant to the fabrication process set forth,
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`i.e., the elimination of excess silicon substrate material
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`from the separately constructed integrated circuit de-
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`vices as the multichip package is assembled, without
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`interfering with the active silicon layers thereon. The
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`removed silicon is single crystal silicon and the fabrica-
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`tion of individual
`integrated circuit devices remains
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`consistent with high volume semiconductor wafer man-
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`ufacturing. As described below, multichip packages
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`constructed pursuant
`to this processing technique
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`achieve the greatest possible silicon volumetric density
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`for separately fabricated integrated circuit devices. The
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`device thicknesses are adjusted to more closely reflect
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`the active surface and depth actually used so that pack-
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`age density is more closely linked to feature depth.
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`FIGS. 4a—4d depict several examples of integrated
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`circuit chip connection options for a multichip package
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`constructed pursuant to the present invention. In FIG.
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`4a, horizontal connecting leads 92 extend to a planar
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`side surface 94 of chip 90 to provide electrical connec-
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`tion between side surface 94 and selected pads 96 on the
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`surface of chip 90. Once multiple chips are assembled in
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`a stack, at least some of which may include horizontal
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`6
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`extending leads 92, a pattern of metallization can be
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`deposited on the edge surface of the stack to define
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`connects to individual electrical pads in the chip, and-
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`/or multiple selected electrical pads located on one or
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`more of the integrated circuit chips.
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`By utilizing the metallized trench approach of the
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`present invention, multiple layers of integrated circuit
`chips, such as chip 90, can be vertically interconnected
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`via metallized trenches, e.g., trenches 98 in FIG. 4b.
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`Trenches 98, constructed as described above in connec-
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`tion with FIGS. 3a—3i, are positioned to extend through
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`the respective chip 90. Alternatively, a mixture of verti-
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`cally and horizontally extending interconnecting leads
`can be used. In such a mixed interconnecting circuitry
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`application, the horizontal leads 92 can extend to one or
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`more edge surfaces 94 of the chip 90 (FIG. 4c), and/or
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`only extend between selected pads in a single chip
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`(FIG. 4a’). The scale of wirability between integrated
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`circuit chips in the multichip package is believed to
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`comprise a significant improvement over state of art
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`package wiring. The dimensions of the vertical inter-
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`connections between integrated circuit chips are at least
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`an order of magnitude smaller than any prior “gross”
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`vertical connection wiring technique.
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`One factor to consider in devising a horizontal/verti-
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`cal interconnection scheme is the amount of space that
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`will be available on the edge surfaces of the completed
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`multichip package. FIG. 5a partially depicts several
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`semiconductor chips 100 arranged in a conventional
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`multichip package. Each chip 100 has several electrical
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`leads 102 extending therefrom to at least one side sur-
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`face of the package. Traditionally, T-shaped electrical
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`junctions are formed in the access plane (i.e., at least one
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`planar side surface of the multichip package having the
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`pattern of chip interconnecting metallization thereon
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`(not shown)), to provide good electrical junctions with
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`the leads brought out to that side surface from the re-
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`spective integrated circuit chips 100. This is accom-
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`plished by depositing conductor pads 104 of uniform
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`size on top of the access plane so that each pad inter-
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`sects with an end of an electrical lead 102 brought out
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`from the respective integrated circuit chips 100.
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`In many applications, planar side wiring is in, the form
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`of stripes (or buses) 105 extending perpendicular to the
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`planes of the chips. Each stripe 105 crosses the junctions
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`between a plurality of chips where it makes electrical
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`contact with the T-shaped junctions on the chips. In
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`many other applications, unique I/O junctions 106 are
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`required for making individual contacts on separate
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`integrated circuit chips 100. In the multichip DRAM,
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`SRAM, EPROM, or other integrate circuits or combi-
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`nation thereof package of FIG. 5a, sufficient space is
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`available on the chips for readily providing these I/0
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`contacts 106 within the access plane. For example, typi-
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`cal spacing between adjacent T-junctions of the same
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`integrated circuit chip is approximately 0.05 millimeters
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`(2 mils), while T-junction spacing between adjacent
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`chips is approximately 0.375 millimeters (15 mils).
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`Examples of access plane sizing for both DRAM and
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`SRAM multichip packages assembled pursuant to the
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`present invention are depicted in FIG. 5b. As shown,
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`the spacing between electrical leads 110 brought out
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`from adjacent
`integrated circuit chips 112 in both
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`DRAM and SRAM configurations is significantly re-
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`duced from the spacing between these leads in FIG. 5a.
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`For example,
`in a DRAM application, such spacing
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`may be approximately 20 micrometers (0.02 millime-
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`ters) and for a SRAM application, spacing may drop
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`MICRON ET AL. EXHIBIT 1075
`Page 12 of 14
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`8
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`Another measure of storage density leverage is to
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`estimate the storage density for packages of approxi-
`mately