United States Patent
`Bertin et al.
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`[19]
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`[11] Patent Number:
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`[45] Date of Patent:
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`5,731,945
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`Mar. 24, 1998
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`US00573 1945A
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`[54] MULTICHIP SEMICONDUCTOR
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`STRUCTURES WITH CONSOLIDATED
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`CIRCUITRY AND PROGRAMMABLE ESD
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`PROTECTION FOR INPUTIOUTPUT NODES
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`Inventors: Claude Louis Berlin. South
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`Burlington; Erik Leight Hedberg.
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`Essex Junction; James Maro Leas.
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`South Burlington; Steven Howard
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`Voldman. Burlington. all of Vt.
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`International Business Machines
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`Corporation. Armonk. N.Y.
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`Assignee:
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`Appl. No.: 778,399
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`Filed:
`Jan. 2, 1997
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`Related US. Application Data
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`Division of Ser. No. 537,451, Sep. 22, 1995, and a continu-
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`ation-in-part of Ser. No. 392,461, Feb. 22, 1995.
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`Int. Cl.“ ..................................................... .. H0211 3/22
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`U.S. Cl. ............................................... 361/111; 361/91
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`Field of Search ................................ 361/56. 91. 111.
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`361/212. 220. 717. 735. 799
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`“A Chip—on—Chip DSP/SRAM Multichip Module" K.L. Tai
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`et a1.. 1995 International Conf. on Multipchip Module (SPIE
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`vol. 2575). pp. 466-471. (1995).
`
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`“Active Silicon Chip Carrier”. D.J. Bodendorf et al.. IBM
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`Technical Disclosure Bulletin. vol. 15 No. 2. (Jul. 1972).
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`“A GaAs on Si PLL Frequency Synthesizer IC using Chip on
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`Chip Technology". S. Sekine et al.. IEEE 1994 Custom
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`Integrated Circuits Conference (Cat. No. 94CH3427—2). pp.
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`563-565. (1994).
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`Primary Exarm'ner—Jeff1'ey A. Gafiin
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`Assistant Examiner——Sally C. Medley
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`Attorney; Agent, or Firm——Heslin & Rothenberg. RC.
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`ABSTRACT
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`[5 7]
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`Multichip semiconductor structures with consolidated cir-
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`cuitry are disclosed. along with programmable electrostatic
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`discharge (ESD) protection circuits for chip input/output
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`(I/O) nodes. The multichip structures include a first semi-
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`conductor chip having a first circuit at least partially pro-
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`viding a first predetermined circuit function. and a second
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`semiconductor chip electrically and mechanically coupled to
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`the first semiconductor chip. The second semiconductor
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`device chip has a second circuit
`that at
`least partially
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`provides a circuit function to the 1'lISt circuit of the first
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`semiconductor chip. In one embodiment. the first semicon-
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`dudor chip comprises a memory array chip. while the
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`second semiconductor chip comprises a logic chip wherein
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`at least some peripheral circuitry necessary for accessing the
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`memory array of the memory array chip resides within the
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`logic chip. This allows the removal of redundant circuitry
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`from identical chips of a multichip structure. Also disclosed
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`is removing. adding or balancing ESD circuit loading on
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`input/output nodes of a multichip stack. Various techniques
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`are presented for selective removal of ESD circuitry from
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`commonly connected I/O nodes. Any circuitry interfacing
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`with an external device may be rebalanced at the multichip
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`level using this concept.
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`18 Claims, 10 Drawing Sheets
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`References Cited
`
`
`U.S. PATENT DOCUMENTS
`
`
`
`2/1979 Benin et al.
`..............................
`4,139,935
`
`
`
`
`
`4/1980
`'
`.
`4,198,696
`
`
`
`
`6/1984
`4,456,803
`8/1986
`
`
`4,608,592
`
`
`6/1987
`4,677,520
`2/1988
`4,727,410
`
`1/1990
`4,894,706
`6/1990
`
`
`
`4,937,471
`
`
`
`206/331
`5/1991
`5,012,924
`
`
`
`361/56
`6/1993
`5,218,506
`.. 437/209
`12/1993
`5,270,261
`
`
`
`361/56
`8/1994
`5,341,267
`
`
`
`361/91
`10/1994
`5,359,211
`
`
`
`
`.................. 257/679
`.
`5,477,082 12/1995
`
`
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`
`
`
`
`OTHER PUBLICATIONS
`
`
`“Partitioning Function and Packaging of Integrated Circuits
`
`
`
`
`
`
`for Physical Security of Data”. IBM Technical Bulletin, vol.
`
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`
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`
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`
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`32 No. 1 (Jun. 1989).
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`MICRON ET AL. EXHIBIT 1073
`Page 1 of 20
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`U.S. Patent
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`Mar. 24, 1998
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`Sheet 1 of 10
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`5,731,945
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`MICRON ET AL. EXHIBIT 1073
`Page 2 of 20
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`Mar. 24, 1998
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`Sheet 2 of 10
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`5,731,945
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`MICRON ET AL. EXHIBIT 1073
`Page 3 of 20
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`Mar. 24, 1998
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`Sheet 3 of 10
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`5,731,945
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`CACHE (L1
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`
`wsmucn N QUEUE
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`INSTRUCTION DECODE
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`
`BUS UNIT
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`DRIVE/RECEIVE ems
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`ALU
`REGISTER FILE
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`EXECUTION UNIT
`MICROCODE
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`MICRON ET AL. EXHIBIT 1073
`Page 4 of 20
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`U.S. Patent
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`Mar. 24, 1993
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`Sheet 4 of 10
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`5,731,945
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`COMMON
`u/o NODE
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`MICRON ET AL. EXHIBIT 1073
`Page 5 of 20
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`U.S. Patent
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`Mar. 24, 1998
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`Sheet 5 of 10
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`5,731,945
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`MICRON ET AL. EXHIBIT 1073
`Page 6 of 20
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`U.S. Patent
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`Mar. 24, 1993
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`Sheet 6 of 10
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`5,731,945
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`[/0 NQDE
`PR8%%%HpN
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`
`SELECTION
`NODE
`PROTECTION
`
`CIRCUIT
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`SELECTION
`NODE FOR
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`PROTECTION
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`LOW LEAKAGE
`LOW
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`CAPACHANCE
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`I/O NODE
`PROTECNON
`
`cmcmT
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`SELECTION
`
`NODE
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`PROTECTION
`CIRCUIT
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`SELECTION
`NODE FOR
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`PROTECTION
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`MICRON ET AL. EXHIBIT 1073
`Page 7 of 20
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`U.S. Patent
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`Mar. 24, 1993
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`Sheet 7 of 10
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`5,731,945
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`PROTECHON
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`CRCWT
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`SELECUON NODE
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`I/O
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`NODE
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`o
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`SELECHON
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`NODE
`PROT.CKT.
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`P—SUBSTRATE
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`MICRON ET AL. EXHIBIT 1073
`Page 8 of 20
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`U.S. Patent
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`%914’2T.m
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`Sheet 3 of 10
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`5,731,945
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`REMOVED M
`PROTECT
`CIRCUITS
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`MICRON ET AL. EXHIBIT 1073
`Page 9 of 20
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`U.S. Patent
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`4.,2L3M
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`8991
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`Sheet 9 of 10
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`MICRON ET AL. EXHIBIT 1073
`Page 10 of 20
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`U.S. Patent
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`Mar. 24, 1993
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`Sheet 10 of 10
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`5,731,945
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`-goo..---..-_---
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`MICRON ET AL. EXHIBIT 1073
`Page 11 of 20
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`1
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`MULTICHIP SEMICONDUCTOR
`
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`STRUCTURES WITH CONSOLIDATED
`
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`
`CIRCUITRY AND PROGRAMMABLE ESD
`
`
`
`
`PROTECTION FOR INPUT/OUTPUT NODES
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`CROSS-REFERENCE TO RELATED
`
`APPLICATION
`
`This application is a division of application SCI. No.
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`08/532.451 filed Sep. 22. 1995 which application is now
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`pending. and a continuation-in-part of a commonly assigned.
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`co-pending U.S. patent application Ser. No. 081392.461.
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`filed Feb. 22. 1995. entitled “Multichip Semiconductor
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`Structures With Interchip Electrostatic Discharge Protection.
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`and Fabrication Methods Therefore.”
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`TECHNICAL FIELD
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`This invention relates in general to fabrication of three-
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`dimensional multichip structures. and more particularly. to
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`consolidation of circuit functions within such structures.
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`e.g.. involving circuitry for protecting the integrated circuit
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`chips from electrostatic discharges or other potentially dam-
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`aging voltage transients occurring during the fabrication or
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`subsequent handling and testing of a single chip. multiple
`chips or a three-dimensional multichip structure.
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`BACKGROUND ART
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`Semiconductor structures comprising three-dimensional
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`arrays of chips have emerged as an important packaging
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`approach. A typical three-dimensional electronic structure
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`consists of multiple integrated circuit chips having main
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`planar surfaces adhesively secured together to form a mono-
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`lithic structure (referred to as a “stack” or “cube"). A
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`metallization pattern is often provided directly on one or
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`more edge surface of the multichip stack for interconnecting
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`the chips and for electrical connection of the stack to
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`external circuitry. This exposed metallization pattern can
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`include both individual
`inputloutput (I/O) connects and
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`bussed connects.
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`Electrostatic discharge (ESD) is a phenomenon known to
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`degrade or destroy discrete electronic components. In
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`particular. given the decreasing size of circuit features with
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`ever improving process technology. static electricity. can
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`destroy or substantially harm many of today’s integrated
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`circuits. Triboelectric charges are produced anytime two
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`surfaces are separated and if at least one of the surfaces is a
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`nonconductor. then a static electric charge is produced. This
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`is a natural phenomenon and only causes a problem if the
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`static charge is allowed to discharge or induce a charge into
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`the integrated circuit. Such an ESD event can occur very
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`pervasively to a point of several thousand volts. The dis-
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`charge occurs very rapidly and the usual failure or degra-
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`dation is caused by the gasification of metal within the
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`device resulting in the gasified metal becoming deposited
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`along a trace of the discharge path.
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`The damage following each electrostatic discharge event
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`may be instantly catastrophic. Often times. however. the
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`integrated circuit does not totally fail. but rather. remains
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`operable with a latent defect that will ultimately result in
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`premature failure. Such events can also alter the operating
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`characteristics of the integrated circuit. thereby resulting in
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`unsatisfactory and often unpredictable operation. Electro-
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`static discharge between inputloutput connects of a serni-
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`conductor device chip can occur. for example. from human
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`handling, automated circuit testing or during packaging of
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`discrete integrated circuit chips.
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`10
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`5,731,945
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`2
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`It has now been discovered that during three-dimensional
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`multichip fabrication. an ESD failure can occur chip—to-chip.
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`for example. during side surface processing of the cube
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`whenever a voltage potential is established between two
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`adjacent chips. This can lead to arcing from the transfer
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`metal pins of one chip to the substrate or transfer metal pins
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`of the adjacent chip resulting in an electrostatic discharge
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`event. An ESD event can also be generated during testing of
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`a multichip semiconductor stack between the testing tool
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`and stack metallization or an integrated circuit chip substrate
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`within the structure. which can subsequently result in a
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`chip—to-chip ESD event.
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`Most. if not all. known electrostatic discharge protection
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`networks operate in connection with a single semiconductor
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`device chip. Since electrostatic discharge suppression cir-
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`cuitry can comprise ninety (90%) percent of the load on an
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`input/output node. there is a need in the art for optimization
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`of such circuitry within a three-dimensional multichip struc-
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`ture. More generally stated.
`there exists a need in the
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`multichip packaging art for an approach to optimizing
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`performance of the three—dimensional structure by deleting
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`or consolidating redundant circuitry. The concepts. circuits
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`and methods presented herein address this need.
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`DISCLOSURE OF THE INVENTION
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`Briefly described. the invention comprises in a first aspect
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`a multichip semiconductor sn'ucture which includes a first
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`semiconductor device chip and a second semiconductor
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`device chip electrically and mechanically coupled together.
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`The first semiconductor device chip includes a first circuit at
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`least partially providing a first predetermined circuit
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`function. while the second semiconductor device chip has a
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`second circuit that at least partially provides a circuit func-
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`tion to the first circuit of the first semiconductor device chip.
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`As an extension of this concept. a multichip semiconductor
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`structure comprising multiple memory array chips and a
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`logic chip is provided. The multiple memory array chips
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`have parallel main surfaces. and are stacked such that a
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`planar main surface of each memory array chip is parallel
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`and structurally coupled to a planar main surface of an
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`adjacent memory array chip. thereby defining a multichip
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`stack. ‘The multichip stack includes a side surface and an end
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`surface. The logic chip. which is disposed at the end surface
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`of the stack and is electrically coupled to each memory array
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`chip in the stack. includes a peripheral circuit function that
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`is necessary for operation of each memory array chip of the
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`multiple memory array chips such that without said periph-
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`eral circuit function. said memory array chips are non-
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`functional.
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`In another aspect. the invention comprises a multichip
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`structure having a first semiconductor device chip and a
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`second semiconductor device chip. The first semiconductor
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`device chip includes a first input/output (I/O) node and a first
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`IJO circuit element. while the second semiconductor device
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`chip includes a second I/0 node. The first I/O circuit element
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`is designed to have an electrical connection to the first I/O
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`node. A conductor electrically interconnects the first I/0
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`node and the second I/O node. thereby defining a common
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`I/O connection. The electrical connection between the first
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`I/O circuit element and the first
`I/O node of the first
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`semiconductor device chip is open circuited such that the
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`first I/O circuit element is unconnected to the corrunon I/O
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`connection.
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`In a further aspect. the invention comprises a multichip
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`structure including a first semiconductor device chip and a
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`second semiconductor device chip. The first semiconductor
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`MICRON ET AL. EXHIBIT 1073
`Page 12 of 20
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`5,731,945
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`3
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`device chip has a first input/output (I/0) node and a first I/O
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`circuit element. while the second semiconductor device chip
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`has a second I/O node. First means are provided for selec-
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`tively electrically coupling the first I/O circuit element to the
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`first I/O node. A conductor electrically interconnects the first
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`I/O node and the second I/O node to define a common I/O
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`connection. Thus. the first I/O circuit element of the first
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`semiconductor device chip may be selectively electrically
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`coupled to the common I/O connection.
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`In a still further aspect. a method is presented for fabri-
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`cating a multichip semiconductor stack having inputloutput
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`(I/O) nodes with electrostatic discharge protection. The
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`method includes: providing a plurality of semiconductor
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`device chips each having an integrated circuit connected to
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`an I/O node and an electrostatic discharge suppression
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`circuit with an electrical connection to the I/O node; lami-
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`nating the plurality of integrated circuit chip such that a
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`planar main surface of each semiconductor device chip is
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`parallel and structurally coupled to a planar main surface of
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`an adjacent semiconductor device chip. thereby defining a
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`multichip stack having a side surface; establishing a con-
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`ductive pattern on the side surface of the multichip stack. the
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`conductive pattern electrically connecting to each of the I/O
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`nodes from the plurality of semiconductor device chips. at
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`least some. of the I/O nodes being electrically connected at
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`a common I/O node; and open circuiting the electrical
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`connection between the electrostatic discharge suppression
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`circuits and the respective I/O node of at least one semi-
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`conductor device chip connected to the common I/O nodes.
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`thereby customizing the electrostatic discharge protection
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`coupled to the common I/O node.
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`To summarize. disclosed herein are semiconductor struc-
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`tures with numerous novel features and advantages over the
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`existing art. First. through selective consolidation of redun-
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`dant circuitry of a plurality of substantially identical chips
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`into a single chip in a multichip stack. overall stack perfor-
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`mance is improved since signal delay through redundant
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`networks is eliminated. For example. output data from a
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`dynamic random access memory (DRAM) chip in a DRAM
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`stack must travel through two sets of oif—chip drivers, one set
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`on the DRAM chip itself. and another set on a logic endcap
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`in communication with external stack circuitry. Elimination
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`of the redundant otf-chip driver can improve performance by
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`as much as 2 nanoseconds. Further. unlike a conventional
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`DRAM chip. operational functions and memory array con-
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`figurations defined at a separate logic chip can be readily
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`converted to any specific application requirement by either
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`redesigning the logic chip or replacing the logic chip with
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`another design. Each memory array chip may principally
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`comprise a memory array. array decoders. bit switches and
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`sense amplifiers. which greatly enhances array utilization.
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`With such complexity reduction. manufacturing and testing
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`can also be simplified. Thus. universal three-dimensional
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`memory array stacks can be created with synchronous
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`operation. input/output width. power rating. power supply.
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`signal levels and other applications specific features defined
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`at an interchangeable logic chip.
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`Another feature of the invention is the reduction or
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`balancing of loading of I/O pads of a multichip structure.
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`Since electrostatic discharge suppression circuitry can com-
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`prise up to ninety (90%) percent of capacitive loading on I/O
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`pads. this concept centers on the elimination or redisl:ribu—
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`tion of ESD circuitry within a multichip structure. However.
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`any circuitry interfacing with an external device could be
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`rebalanced at
`the multichip package level. The concept
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`applies to bussed I/O pads. as well to single I/O pads. In
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`application. only one ESD circuit may be required to protect
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`4
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`all receivers electrically connected by a bussed I/O pad. This
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`single circuit could be disposed in any of the interconnected
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`chips or on a separate chip which interacts with external
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`circuitry. for example. an endcap chip. Further. any number
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`of techniques may be employed for open circuiting redun-
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`dant electrostatic discharge circuitry.
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`BRIEF DESCRIPTION OF DRAWINGS
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`These and other objects. advantages and features of the
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`present invention will be more readily understood from the
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`following detailed description of certain preferred embodi-
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`ments of the invention. when considered in conjunction with
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`the accompanying drawings in which:
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`FIG. 1a is a plan view of one embodiment of a memory
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`array chip for use in a multichip semiconductor structure in
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`accordance with the present invention;
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`FIG. 1b is a perspective view of a multichip semiconduc-
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`tor structure incorporating a plurality of memory array chips
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`of FIG. la;
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`FIG. 2a is an alternate embodiment of a memory array
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`chip for use in a multichip semiconductor structure in
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`accordance with the present invention;
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`FIG. 2b is a schematic of a multichip semiconductor
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`structure incorporating a plurality of memory array chips of
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`FIG. 2a;
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`FIG. 2c is a block diagram of typical microprocessor chip
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`functions;
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`FIG. 2d is a partial perspective View of a multichip
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`semiconductor structure comprising memory array chips.
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`microprocessor function chips and application specific inte-
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`grated circuit (ASIC) chips;
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`FIG. 3 is a partial perspective view of a multichip
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`semiconductor structure selectively employing protection
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`circuitry in accordance with the present invention;
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`FIG. 4 is a schematic of the capacitive loading on the
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`common input/output (I/O) node interconnecting chips k—l
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`to k+2 of FIG. 3;
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`FIG. 5 is a partial perspective view of a multichip
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`semiconductor structure employing electrically “remov-
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`able” protect circuitry in accordance with the present inven-
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`tion;
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`FIG. 6 is a partial perspective view of an alternate
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`embodiment of a multichip semiconductor structure
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`employing electrically removable protect circuitry pursuant
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`to the present invention;
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`FIG. 7a is a schematic of an integrated circuit chip having
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`selectable I/0 protection circuiny employing a switch con-
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`trollable via a protect deselect node;
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`FIG. 7b is a schematic of an integrated circuit chip having
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`selectable I/O protection circuitry employing a pass gate
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`switch controllable via a protect deselect node;
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`FIG. 8 is a partial structural. partial circuit diagram for
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`one embodiment of the integrated circuit chip of FIG. 7b,-
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`FIG. 9 is a schematic of a common I/0 node of a
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`multichip semiconductor structure having 11 chips electri-
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`cally connected thereto. each chip with a separate protect
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`circuit;
`FIG. 10 is a schematic of a common I/O node of a
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`multichip semiconductor structure having 11 chips electri-
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`cally connected thereto. wherein in chips have open cir-
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`cuited connections to the protect circuits such that
`the
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`circuits are isolated from the common I/O node;
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`FIG. 11 is a schematic of an I/O node having a single
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`integrated circuit chip electrically connected thereto;
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`MICRON ET AL. EXHIBIT 1073
`Page 13 of 20
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`

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`5,731,945
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`5
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`FIG. 12 is a schematic of the single chip I/0 node of FIG.
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`11. wherein multiple protect circuits. for example from other
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`chips in a multichip structure. are electrically connected to
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`the node to enhance protection at said node;
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`FIG. 13 depicts a single in-line memory module (SIMM)
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`card with multiple memory modules; and
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`FIG. 14 depicts a SIMM card with multiple memory and
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`application specific integrated circuit (ASIC) modules.
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`BEST MODE FOR CARRYING OUT THE
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`INVENTION
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`Generally stated as a first concept the present invention
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`comprises the identification and removal of redundant
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`peripheral circuitry from identical integrated circuit chips of
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`a multichip structure. (As used herein. the phrase “multichip
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`structure” generally refers to multichip “stacks” or “cubes”.
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`as well as to conventional multichip modules (MCMs). i.e..
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`if not otherwise specified.) By way of example. peripheral
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`circuitry on dynamic random access memory (DRAM) chips
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`is needed to read. write and refresh the memory cells. as well
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`as to provide industry standard or custom operation. oif-chip
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`driving and package adaptability. Array utilization is
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`referred to in the art as the measurement of memory array
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`area to total chip area which includes the peripheral circuitry
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`area. Stacking of standard DRAM chips to create a multichip
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`semiconductor stack results in redundancy of many periph-
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`eral functions and circuitry. Reducing this redundancy is
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`proposed herein in order to increase array utilization within
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`the memory chips.
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`More particularly. by moving peripheral (also referred to
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`as input/output (I/0)) circuitry functions from the memory
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`drips to a separate logic chip in the multichip semiconductor
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`structure. the peripheral circuits can be eliminated from the
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`individual memory chips. Examples of such I/O function
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`circuitry would include circuits for the row address strobe!
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`column address strobe (RAS/CAS) function. the memory
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`read/write controls. refresh controls. oif-chip drivers. protect
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`devices and bonding pads. As set forth above. consolidating
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`this circuitry for all memory chips in a single logic chip can
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`significantly enhance performance of the resultant structure.
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`Another concept presented herein is the selective
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`removal. addition or balancing of electrostatic discharge
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`(ESD) circuit loading on external inputloutput (I/0) nodes or
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`pads of a multichip semiconductor stack. The selective
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`removal of ESD circuitry from a particular input/output
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`node within a single integrated circuit chip is also contem-
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`plated. As one example. it may be desirable to reduce
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`loading on one or more pins of a packaged integrated circuit
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`chip. Removal of the ESD circuitry from a pin is significant
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`since ESD circuitry can comprise up to ninety (90%) percent
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`of the capacitive load on a pin. This concept of unloading]
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`loading external I/O nodes applies to a single chip. and to
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`any multichip structure. including stacks. MCMs. cards and
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`boards. Further. essentially any circuitry interfacing with an
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`external device may be rebalanced at the multichip package
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`level using this concept.
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`The structures and methods in accordance with the
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`present invention are described in greater detail below with
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`reference to FIGS. 1a—l4. wherein the same or similar
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`reference characters are used throughout multiple figures to
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`designated the same or similar components. In FIG. 1a, a
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`memory array chip 10 is shown to comprise a memory array
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`12 wherein word decoders 14 split the array for center-
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`tapped wordlines. Along one edge 18 of chip 10 are disposed
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`bit switches. sense amplifiers and drivers 16 for the memory
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`array. Circuitry 14 & 16 is referred to herein as the “memory
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`6
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`access circuitry.” Note from this figure that the conventional
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`peripheral (or input/output) circuit functions. such as the
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`RAS/CAS functions. memory readlwrite controls. refresh
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`controls. otf—chip drivers and protect devices. are assumed to
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`have been transferred to a second semiconductor chip to be
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`packaged with memory chip 10 within a multichip semi-
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`conductor structure (FIG. lb). Chip 10 is thus configured for
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`maximum memory array 12 density.
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`FIG. 1b depicts a multichip semiconductor stack 20
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`comprising a plurality of memory array chips 10 having
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`aligned edge surfaces 18. An endcap chip 22 is disposed at
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`one end of stack20 and conductive patterning 26 is provided
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`on at least one side surface 24 of the multichip semicon-
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`ductor stack to electrically connect the memory chips of the
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`stack to the endcap chip 22. Chip 22 may comprise a logic
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`chip containing (in one embodiment) all input/output (I/O)
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`circuit functions for the memory. chips 10 in the stack
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`Disposition of the bit switches. sense amps and drivers along
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`edge surface 18 of each memory chip results in a beneficial
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`layout from a performance standpoint in that transmission
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`distances are reduced Alternatively. these structures could
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`be disposed in the middle of the memory arrays (FIG. 2a)
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`and then brought out to edge surface 18 via conventional
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`transfer wirings. As a variation. note that the pa-ipheral
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`circuit functions removed to the endcap chip could be
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`disposed on a logic chip located anywhere within the stack.
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`Operationally. complementary metal oxide semiconduc-
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`tor (CMOS) level signals are driven down the stack 20 from
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`the logic endcap chip 2 to the word decoders of the
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`individual memory chips. where the signals are latched via
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`a word enable buffer. After sense amplifiers have set. the bit
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`switches along the chip edges are opened in response to the
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`incoming bit address. Data is driven back up the stack to the
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`logic endcap chip 22. and hence off stack to external
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`circuitry. This structure has many advantages over pre-
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`existing stack technology. For instance. memory array I/O
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