MICRON ET AL. EXHJBIT 1058
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`Page 1 of 7
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`AUGUST 22, l99WOL 42, NO. 17
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`. . 47
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`Ifcfilnlil-Yllgg HIGH-SPEED MODEMS: THEY'RE NOT JUST FOR DATA ANYMORE .
`Innovative modem technologies pump data, fax, and voice-mail at blazing
`speeds. Just how do they get those 114 kbits on that 3—kHz line?
`FEE?” MEMORY-CHIP STACKS SEND DENSITY SKYWARD .
`.
`. 69
`um: Vertical integration of silicon allows packaging of extre
`mely dense system
`memory_in tiny volumes.
`} j(
`flpylmgglggg BUILD A POWERFUL HOSTDSP INTERFACE .
`.
`. 77
`Dual-port memory combines the ease and cost of FlF‘0s with the datapath
`capability of custom hardware.
`
`__;__ .
`DEBUGGING SYSTEMS: GETTING THE PIECES TO WORK TOGETHER . . . 87
`Fixing errors in embedded systems calls for teamworl<—and tools.
`DEBUGGING: ENTERPRISE INSTRUMENTATION .
`.
`. 93
`Locating real-time bugs in embedded systems is especially tricky while
`integrating hardware and software.
`
`DEBUGGING FOR REAL TIME: HARD CHOICES .
`.
`. 101
`Because every tool has an effect on the system, knowing yo.ur tools is the best
`defense.
`
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`'”"‘f""'“7' INTEGRATED CONTROLLER SUITS LASER PRINTERS .
`.
`. I53
`IMMMIW IC includes DRAM/ROM control, DMA, parallel port, interrupt controller,
`counter—timer, configurable I/O bus, and programmable I/O lines.
` ?.
`
`
`rzuzcrxoxic IJEIGN (IJSPS 172-080; ISSN 0013-4972) is published twice monthly except for 3 issues in lltayonnd 3 issues in October by
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`MICRON ET AL. EXHIBIT 1058
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`Page 2 of 7
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`COVER FEATURE
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`VERTICAL INTEGRATION OF SILICON
`ALLOWS PACKAGING OF EXTREMELY DENSE
`SYSTEM MEMORY IN TINY VOLUMES.
`MEMORY-CHIP STACKS
`
` Stacking memory ICs vertically has other
`benefits besides the density gains. The close
`
`physical proximity of the chips significantly
`
`reduces the system delay associated with in-
`
`terconnect capacitance and pc—board trace
`
`length. Speed is increased while power re-
`
`quirements and operating temperatures are
`
`reduced compared with horizontal layouts.
`
`CMI has leveraged its chip-stacking tech-
`
`nology into an initial pair of pror.lu<:t families.
`
`ELEC1‘!!0NIlI[)ESlGlvl[jEl
`A U(}US’l‘ 22, 199-1
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`MICRON ET AL. EXHIBIT 1058
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`Page 3 of 7
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`SEND DENSITY S
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`DAVID MALINIAK
`
`any aspects of board de-
`sign, such as timing, ther-
`mal issues, and manufac-
`turability, require innova-
`tive thinking. But
`if
`there’s one aspect of board
`design that’s relatively predictable, it's the
`layout, which is done in the X and Y dimen-
`sions. Chips are, almost without exception,
`placed side by side in some arrangement,
`even if the board is double-sided or flexible.
`This constant of board design, however, is
`the great limiter of a board’s packaging den-
`sity. And nowhere is this limitation more glar-
`ing than in the layout of system memory,
`where row upon row of DRAMs sprawl
`across vast expanses of pc board like some
`silicon suburban development.
`But the push is on to shrink systems, and
`the traditional layout concepts are becoming
`an extravagance. Over the years, there have
`been a number of attempts at exploiting the
`third dimension in board layout. Chips have
`been stood on their edges and sandwiched to-
`gether and there have been attempts atstack-
`ing them vertically. But until now, such
`schemes have been either too expensive or
`the yields have been poor. In some cases, the
`density achieved wasn't worth the effort.
`With the development of its technology for
`vertical integration of memory wafers, wafer
`segments, and individual die, Cubic Memory
`Inc. (CMI), Scotts Valley, Calif., has shot-
`tered the density barrier (Fig. 1). Instead of
`the 40-to—80-Mbyl.e/in.“ storage densities pos-
`sible with conventional packaging—-using 16-
`Mbit memories in smaltoutline J-lead pack-
`ages (SOJS) or two-sided thin s1nall~outline
`packages (TSOPs)—CMI claims the ability to
`achieve densities of a gigabyte or more per
`cubic inch.
`
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`~
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`..~
`-»
`-
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`v
`I. INSTEAD OF THE 4040-80-Mbyte/in.’storIgedeI1sities
`possible with conventional packaging (Ming I6-Mhlt memories in
`S0.ls or two-sided 'I‘SOPs), Cubic Memory Inc. (CM!) claims the
`ability to achieve densities of a gigabyte or more per cubic inch.
`
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`1\/HCRON ET AL. EXHIBIT 1058
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`Page 4 of 7
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`.7“ _ .
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`_..... 4._>-__¢____:._ _?_j.
`flaunt
`MEMORY-CHIP STACKS
`
`'
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`
`
`non-oxidizing metal surface for the
`the
`takes advantage of
`One
`layer-to-layer interconnections.
`PCMCIA-card format for adding
`Whole wafers, segments of wa-
`workstation-quantity memory to
`‘
`fers, or individual die can be
`Pentium-based portables,
`'
`'
`J! stacked. In addition, multi-
`while the other works with-
`.
`ple silicon technologies can
`in the DRAM SIMM format.
`; be mixed in the same stack
`Both merely hint at the tech-
`(Fig. 3). Other components
`nology's potential, which is
`I can be placed on top of the
`not necessarily limited to "
`silicon stack as well.
`stacking of memory alone.
`For the small—hole and
`There are actually three ‘,
`VIP processes, standard
`separate technologies for .
`wafers can be used without
`vertical integration, each of
`need for any custom silicon.
`which is suitable for differ-
`Individual chips can be se-
`ent applications. The three
`lected by the control circuit-
`processes are referred to as
`ry. The vertical chip-to-chip
`the large-hole process, the -'
`distance is variable from
`small-hole process, and the
`0.003 to 0.010 in., depending
`Vertical
`Interconnect Pro-
`on the application and densi-
`cess (VIP). Common to each '
`ty required.
`process is a vertical silicon -,
`The vertically integrated
`interconnect and a patented '-
`stacks are attached directly
`compliant
`interconnect
`scheme.
`to pc boards. Tests on whole
`wafers and wafer segments
`The first two processes,
`have shown a 15% reduction
`known as the large- and
`in power consumption and a
`small-hole processes, use a v
`20°C lower continuous oper-
`patented, pyramid-shaped :
`ating temperature when
`via through the silicon (Fig.
`:
`compared to identical cir-
`2). The small opening on the ~
`cuits operating in conven-
`top of the pyramid pene-
`tional plastic packages.
`trntes on the circuit side and
`Originally, the large-hole
`the large opening comes
`process was developed to al-
`through the back side of the
`low stacking of complete 6-
`silicon, where the intercon-
`in. DRAM wafers. The pyra-
`nect makes contact with a
`mid-shaped holes are filled
`number of circuit elements
`with a mesh of fine gold-
`on the silicon immediately
`plated wire. The wires form
`below. This interconnect
`a mushroom shape on the
`method takes up no space,
`circuit side of the wafer, and
`as all pins fan out under the
`the other ends of the wire
`silicon stack instead of tak-
`are compressed and con-
`ing up large areas around
`tained in the pyramid base.
`the perimeter of the active
`When the wire-filled base of
`silicon, as is done with con-
`the pyramid of one wafer is
`ventional packaging. In ad-
`brought into contact with
`dition,
`this method allows
`the top of another wafer, the
`the individual circuit ele-
`mushroom-shaped “fuzz
`ments to be easily isolated
`button” is captured by the
`for testing up until the final
`base of the pyramid. All of
`stack assembly.
`the wires are then contained
`The VIP process is a less
`and a compressive gold-to-
`expensive extension of the
`gold contact is formed be-
`small-hole process and does
`.4 tween the circuit elements
`not require the pyramid—
`2. BOTH THE small- and lugc-hole processes use:pyrarniui-
`of both wafers. The result is
`v
`shaped via through the sili-
`f shaped via through the silicon to make the vertical
`a very reliable, fully compli—
`'
`-’
`con. Instead, gold intercon-
`neet traces and vertical-in— ‘_._3
`interconnections. The small opening on the top of the pyramid
`ant, reworkable intercon-
`terconnect pads are deposit-
`;_;‘
`penetrates on the circuitsidc and the large opening comes through
`nect that supports intercon-
`ed over insulating layers of ‘
`the back side of the silk-.on,where the interconnect makes contact
`nections in both the horizon-
`polyimide. The gold traces
`witlinnnmberofcircuitelementson thesilicouimmediatelybelow.
`tal and vertical directions.
`ELECTRONIC DESIGN
`AUGUST 22, 1994
`.
`
`interconnection
`provide horizontal
`of the die on a single layer or seg-
`ment, and the gold pads provide a
`
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` on bottom) so that the verti-
`
`interconnect is accom-
`cal
`plished within a bond-pad
`area and on conventional
`bond-pad pitches.
`The small-hole process in-
`corporates one level of dis-
`cretionary wiring for every
`layer of silicon in the stack.
`Each die also has the neces-
`sary
`control
`signals
`brought out so that the con-
`trol circuitry can address
`each chip uniquely.
`Silver—filled epoxies are
`used for the compliant con-
`ductive material. These
`
`segments of waters, or individual
`3.
`die can he suckul. In addition. multiple silicon technologies can be
`mixed in the same stack. Other components can he placed on top of
`the silicon stack as well.
`
`
`
`'l‘he “1'uzz-button" inter-
`connect does, however, re-
`quire a custom mask set.
`And the holes are large by
`semiconductor standards:
`150 pm at the top and 1000
`pm at the base. This inter-
`connect technology is still
`used in some applications.
`The small-hole process
`was developed as a refine-
`ment of
`the large-hole,
`“fuzz—hutt.on” technology to I
`allow interconnects on stan-
`dard
`semiconductor-die
`bonding pads without the
`need for a specialized struc-
`tu re. In this method, off-the
`shelf memory wafers can be
`used without the need for the semi-
`conductor manufacturer to run a
`custom mask set.
`In this case, the hole-making pro-
`
`cess is similar to the fuzz-button pro-
`cess, but the dimensions change. The
`wafers are thinned and the holes are
`small enough (25 pm on top, 120 pm
`
`proven materials are the
`same ones that have been
`used for years by semiconductor
`manufacturers as a die-attach medi-
`um. CMI has developed a proprietary
`application method for the dispens-
`
`
`
`_,
`
`anufacturers of lap-
`top/notebook comput-
`ers are forever facing
`the
`challenge
`of
`squeezing desktop performance
`into an easy—to-transport pack-
`age. In the RISC-workstation are-
`na,
`the problem intensifies, be
`cause many of the Unix-based ap-
`plications demand tremendous
`amounts of memory to execute
`quickly.
`Just such a problem was faced
`by designers of the SPARCbook
`III at Tadpole Technology plc,
`Cambridge, U.K.,
`explains
`George Grey, the group chief/ ex-
`ecutive officer. The need for an al-
`ternative to the standard DRAM
`single-in-line memory module
`(SIMM), which peaks in capacity
`at 32 Mby tes, led Tadpole to team
`with Cubic Memory Inc. (CMI) to
`develop higher—density SlMMs.
`By taking advantage of CMI's
`vertical
`interconnect process
`(VIP), designers at Tadpole and
`CMI defined an extension to the
`standard DRAM SIMM that will
`initially provide 64 Mbytes of stor-
`age (organized as 16 Mwords by
`36 bits, which includes byte-parity
`hits). F'urthermore, CMI expects
`to double the capacity to 128
`
`Mbytes per SIMM by late 1994,
`and still keep the SlMlV[ lieight: to
`just 1 in.
`One of the first steps designers
`had to take to enhance the SIMMs
`was to expand the address range.
`They added one more address line
`and two additional row-address-
`strobe (RAS) lines by using sever-
`al pins that were previously no-
`connect pins on the SIMM. Some
`of the key issues that designers
`had to deal with, explains Dave
`Pedersen, V.P. of engineering at
`CMI, included the banking archi-
`tecture and capacitive loading ef-
`fects in highly-configured sys-
`tems. Fortunately, because the
`memory chips are mounted on top
`of each other, there are no pack-
`age loading effects. Also, typical-
`ly, only one bank of memory is
`turned on at a time, which mini-
`mizes thermal problems.
`Once the interface was defined,
`the memory structure was imple-
`mented using “stacks” of memo-
`ry layers. The memory stacks con-
`sist of eightrsegment layers (each
`segment can be thought of as a 2-
`Mword bank of-DRAM). The VIP
`scheme employs pyramid-shaped
`recesses on the outer edge of the
`chips. Then, when the chips are
`
`stacked, the contact etlges are ex-
`posed so that (ZOI1(.ll1('1'.lV(‘. epoxy
`easily fills the recesses and real-
`izes the connections.
`Each segment layer in the mem-
`ory stack consists of a monolithic
`piece of silicon that contains four
`2-Mword-by-8-bit DRAMs, thus
`forming a 32-bit-wide memory
`block. Complementing the 32-bit-
`wide stack is a second stack that
`
`provides the four parity bits for
`each word.
`After the stacks are assembled,
`they are mounted in the SIMM
`substrate. The substrate actually
`has a hole the size of a stack cut
`into it and the stack is then insert-
`ed into the substrate. The stack
`protrudes out of one side of the
`substrate by the amount of the
`difference in their thicknesses. In
`the case of the 128-Mbyte stacks,
`which stand 0.160 in. tall, they pro-
`trude 0.098 in. from the 0.062-in:
`thick substrate. That’s less than
`the height of a thin small-outline
`package. When coated with the
`sealing epoxy, the mechanical (lu-
`rability of the SIMMS is as good as
`previous-generation SI MM s that
`were populated with surface-
`mounted components.
`B Y DA VE‘ B URSKY
`_b...._?___.___..__.
`
`mELECTRONlC
`AUGUST 22, 199-1
`
`D E S
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`MICRON ET AL. EXHIBIT 1058
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`Page 5 of 7
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`ing and application of these epoxies
`for connection in both the hori‘/.ontal
`and vertical dimensions.
`Taking the process a step further,
`the VIP process makes
`high—volume automation a
`part of the manufacturing
`cycle. It’s also the lowest-
`eostmethod, because ituses
`asubset of the steps used in
`the small-hole process and
`does not require the pyra-
`mid-shaped hole through
`the silicon. The VIP process
`is suitable for stacking die
`and wafer segments that do
`not have a large number of
`interconnects to outside log-
`ic. It is not suitable, howev-
`er, for stacking whole wa-
`fers.
`In the VIP process, gold
`traces and vertical-intercom
`nect pads are deposited over
`insulating layers of polyi-
`mide. Then, the wafers are
`thinned and sawed into seg-
`ments. The segments’ edges
`M
`are beveled to allow vertical
`interconnection (Fig. 4). The "
`gold traces provide horizon-
`tal interconnection of the din _
`on a single layer or segment
`‘*-
`and provide layer- or seg-
`;
`ment-specific memory-ad
`'.
`dress decoding capability.
`Pins that are parallelable -
`are connected that way,
`which results in a reduction
`of pin count per layer of
`about 4:1. If the resulting ..,‘
`stack has ten layers,
`the 3
`overall reduction in pin ?_‘_-'
`countis about40:1. The gold
`bonding pads are exposed at
`the sides of the segments
`thanks to the 45° bevel cut
`
`.,
`--
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`3 -'
`; "
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`'
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`ductivity to enhance dissipation of - today, CM I is offering two forms of
`heat from the stack.
`memory modules for expansion of
`To leverage its chip-stacking tech-
`portable-system memory. One is the
`nology into products that are usable
`3DMemory family of 88-pin JEDEC
`memory modules in capaci-
`ties of 16, 32, 64, and 128
`Mbytes. These are targeted
`for use in portables with a
`Type I PCMCIA slot, and
`are especially meant for
`Pentium—based portables
`that are expected to be able
`to address 64 Mbytes of sys-
`tem memory or more by this
`fall’s Comdex show.
`In this implementation of
`the technology, a glimmer
`ofitspotcntialimpactcomes
`into focus. For manufactur-
`ers using conventional tech-
`nologies, volumetric space
`requirements limit portable
`add-in memory cards to one
`double-sided pc board using
`’l‘SOP packages. Typically,
`only 16 to '18 ICs will fit into
`the available space, so to re-
`ulizc
`the maximum 16
`_ Mbytes of storage, the man-
`ufacturer must use costly
`j 16-Mbit DRAMS. Here’s
`where the vertical—intep;ra-
`tion technology comes in.
`‘
`‘ With it, memory cards are
`built using the most cost-ef-
`:gl fective DRAMS available.
`4 The 16-Mbyte card conta.ins
`two stacks of four layers
`_ -' each. Each 2-Mbyte layer is
`' made up of four 4-Mbit
`DRAM die. The 32-Mbyte
`card increases the two
`» stacks to eight layers each.
`i This produces a 16-Mbit
`module with a 32-bit word.
`
`4. IN THE VIP PROCESS, gold traces and bonding pads
`are deposited over insulating layers of polyimide. Then, the wafers
`are thinned and their edges beveled to allow vertical
`interconnection. The gold traces provide horizontal
`interconnecfion of dieon a single layer or segment and provide
`layer or segmentspecifc niernory-mldrusu decoilc capability.
`
`V
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`__._
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`__ _.
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`.__
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`___._______-___,._..-______ ,,
`
`..
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`.
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`.
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`..
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`.
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`-__________
`
`MEMORNIHIP STACKS
`
`
`
`si|,,e,.r,“mp,,,y
`
`dd mm
`
`Pc board
`
`cm nmmmmsammu
`5".
`ha
`I
`I
`"°" "*9"
`
`-_
`Gold
`
`Pcmmh
`
`Up to 128 Mbytes is easily
`accommodated within the
`
`PCMCIA Type I form fac-
`tor.
`
`: It
`
`'
`
`-‘
`
`and are used for the layer-
`to—layer connections.
`A conductive silver-fillet]
`
`
`
`For memory-card manu-
`epoxy is used for both physi-
`facturers using convention-
`cal and electrical connection
`al packaging technologies,
`the volumetric space re-
`of the layers.'l‘hc same eon—
`quirements limit the cards
`ductive epoxy is used to con-
`toonedouble-sided pc board
`nect
`the stack to the pc
`using TSOPS. Only 16 to 18
`‘L 5. [N BOTH THE 88-pin JEDECmodnle and the Slims, the
`board. The stack is then on 1],
`capsulated with a casting .3 _i, memory stacks are not mounted to the curd'sinia-oaipcboardoa memory chips fit into the
`resin to provide protection ‘‘
`such. Rather, they are"flonted" inside holes that go through the
`available space, so to realize
`and mechanical durability.
`board and Attached at their pcriplirry by means of beam-style lends
`the maximum 16 Mbytes of
`The resin also provides
`consisting of ronductiveenory. They are then glolrtorr
`storage, the manufacturer
`some degree of thermal con» .42‘. ./ encapsulated on the reverse side to provide stability.
`must use cost] y 16-Mbit
`flflstiicriroraic ossicr:
`AUGUST 22, 199.4
`
`MICRON ET AL. EXHIBIT 1058
`
`Page 6 of 7
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`

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`MEMORY-CHIP STACKS
`
`j——?:
`
`DRAMs. In contrast, CMI's vertical
`integration technique offers its in-
`herent density advantages and en-
`ables cards with capacities of 16
`Mbytes and more to be built using 4-
`or 16-Mbit DRAMs.
`An interesting note on the con-
`struction of the cards is that the
`memory stacks are not mounted to
`the card’s internal pc board as such.
`Rather,
`they are “floated" inside
`holes that go through the board and
`attached at their periphery by means
`of beam-style leads consisting of
`conductive epoxy. (Fig. 5).
`For adding system memory to
`workstations and servers, CMI is of-
`fering a line of 3DMemory 64- and
`128-Mbyte DRAM SlMMs. Previous-
`ly, the maximum density of standard
`72~piII SlMMs has been 32 Mbytes
`(see “Putting memory stacks to
`work, "p. 57).
`The 64-Mbyte SIMMS are made
`from eight layers of 8-Mbyte wafer
`segments (each made from four 16-
`Mbit DRAM die) plus a four-layer
`stack of 16-Mbit die for parity. The
`128-Mbyte SIMMS will use 16 8-
`MByte layers, plus an eight-layer
`stack of 16-Mbit die for parity. The
`memory organization is 16 Mbytes
`by 36 bits for the 64-Mbyte SIMM
`and 32 Mbytes by 36 bits for the 128-
`Mbyte version. D
`-
`
`PRICE AND AVAILABILITY
`The .?DMemory 88-pin JEDEC memory
`modules will be sold to 0EMs as well as
`through. the reseller chmmel to end users.
`The llzitlllvyle modules are scliedrlled to
`sliip in Seplambev; mid at locla_I/‘s memory
`prices will have (1 .mg_ csled price of$9.95.
`The 32-, 84-, and I28-M 3/lo versions will lie
`available during the fourth quarter and
`pricing is projected at $1.995, 339.95, and
`$79.95 each, 1'aspecti'vcly.
`The 3DMem.o1'_I/ 72-pin SIMMI: will ini-
`tially be sold only to ()E'Ms. Al lodays
`memory prices, the 6'4-Mbyle SlMMs will
`cost .\‘.Y.<l9.U in sample lots aaul £35.99 in
`quanlimzs of 1000. The 128-Mbyte SlMMs
`will scllfor $799.9 (samples) and $719.9 (pro-
`duction quantities). Samples are avail-
`able wow and production quantities will
`be available dm-ing thefourth qua.rtrrr.
`Cubic Mcmory lm:., 2I”JImI's Way. Sculls
`Valley, CA 95066?‘ (408) 4-98-188?? fax (.608)
`138-1890
`CIRCLE 512
`
`How VALUABLE?
`HIGHLY
`MODERATELY
`
`534 SLIGHTLY
`
`CIRCLE
`533
`
`535
`
`eedy IMOS
`Our
`logic ls Bi News.
`But Wefe eeping
`It Quiet.
`
`It’s hard to keep the noise down on a
`development this big.
`But that’s exactly what we’ve done.
`Our new VHS (VHC comparable) series of
`LMOS logic not only offers high speed switching,
`but super-low noise besides.
`AC speed at HC levels, you might say.
`What’s Inore, its single-gate format makes for
`more board space. Along with increased design
`flexibility.
`So call us at 1-800-879-4963 to get in on
`a timely idea.
`Lightning-fast LMOS.
`Without the thunder.
`
`In Touch with Tomorrow
`TOSHIBA
`TDIHIBA AMERICA ILECTHDNIC CDMDUNENTE, INC.
`
`8L"l9‘J3 Toshiba Ann-rica Eloclronic CunIpoIieIIl~5. III?‘
`
`5l’D~93 U57!‘
`
`READER SERVICE 152 CALL ME
`READER SERVICE 183 FOR INFORMATION
`
`I
`
`
`
`ELECTRONIC Drsicnifl
`AUGUST 22.1994
`
`MICRON ET AL. Eifl-IIBIT 1058
`
`Page 7 of 7