9TH SYMPOSIUM ON FUTURE ELECTRON DEVICES
`_November 14-15. 1990 Makuhari. Chile. 139311 W 26?-272
`
`EVALUATION OF CUBIC (CUMULATWELY BONDED IC) DEVICES
`Yoshihiro I-IAYASHI
`Microelectrorlita Research laboratories, NEC Corporation
`1120, Shimokuzawa, Sagamihan Kaaagawa 219. Japan
`
`ABSTRACT
`
`cumulatively
`Thin film device layer bonding technology. referred as to
`fabrication.
`bonded-
`IC ( CUBIC )
`technology. has been developed for 3D—IC
`Advantages
`of the CUBIC technology are its ability to make device
`layers
`independently on
`the Si-substrates using a
`conventional
`IC fabrication
`process.
`the lack of heat damage during the device bonding process. and its
`short process turn around time.
`In this paper. concept of CUBIC technology
`and
`key process technologies involved are described in detail.
`and
`its
`application to future electron device fabrications will be discussed.
`
`INTRODQQTION
`
`In the field of system which consists of a large amount of electronic
`functional blocks.
`the packaging density has been the major impetus to
`the
`system performance improvement.
`A lot of technical approaches to attaining
`high packaging density have been proposedll-2].
`Among
`them is
`three
`dimensional
`IC fabrication. where several device layers are stacked in
`the
`vertical direction.
`(Silicon—On-Insulator)
`Three dimensional Ice are made by repeated S01
`To obtain the S01
`film.
`formation and device fabrication on the 501 film.
`and
`recrystallized by
`a polysilicon film on silicon dioxide is melted
`scanned laser beam or electron beam. However. serious problems in the
`3D-
`IC fabrication process. hereafter
`called as
`“beam
`recrystallization
`method“.
`are pointed out[3.4]. First. with
`increasing the
`number of
`stacking layers. quality control
`of the
`S01
`film becomes difficult.
`Second. underlying device layers suffer from heat-damage during upper layer
`device
`fabrication.
`Furthermore. a long process turn around time ( TAT
`)
`and
`low productivity also restrict mass production of
`3D—1Cs
`since
`the
`number of process steps extremely increases with the device layer.
`In
`this paper. a new SD-IC fabrication technolosyx
`referred to as
`( Cumulatively Bonded IC J
`technology is proposed. and
`its future
`CUBIC
`applications are described.
`
`gg Concept Q£ CUBIC teghnglggy
`
`The CUBIC
`1 illustrates the concept of CUBIC technologylfil.
`Figure
`involves
`the device thinning process and the device
`bonding
`technology
`process. First.
`the lat. 2nd and 3rd device layers are made
`independently
`on
`bulk Si substrates using a conventional
`IC fabrication process.
`Next.
`the
`silicon crystals underlying the
`2nd
`and
`3rd device
`layers
`are
`eliminated to obtain thin film devices. Then. vertical wirings
`are made
`for
`signal
`and
`power transmission from the front
`surface
`to
`the
`back
`surface
`of
`the
`thin film devices. Finally.
`the thin film devices
`are
`bonded mechanically and electrically.
`ordinary
`The CUBIC technology has a lot of advantages superior to the
`3D—lC fabrication technology using a beam recrystallization method. One of
`the most attractive advantages of the CUBIC technology is its ability to
`make the device layers independently on bulk Si—substrstea.
`thus shortening
`the process TAT of 3D—IC fabrication.
`The other
`advantage of
`the
`CUBIC
`technology
`is
`the
`lack of heat damage because of a
`low device
`bonding
`temperature.
`Thus.
`the CUBIC technology is expected to be
`applicable
`to
`the SD-IC fabrication having a large number of stacking device layers.
`
`
`
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`MICRON ET AL. EXHIBIT 1055
`Page 1 of 6
`
`

`
`9TH SYMPOSIUM ON FUTURE ELECTRON DEVICES
`blovernber ll-15. 1990 Makuhari. Chiba. Japan pp 257.272
`
`Key technologies
`
`how to
`the key issues are
`In order to realize the CUBIC technology.
`obtain thin film devices. make electrical path from the front
`surface
`to
`the
`back
`surface of the thin film devices.
`and make device—to-device
`electrical interconnections in the bonded structure.
`In this section.
`the
`technologies which were developed to solve these issues are described.
`
`3-1. Device thinning
`
`polishing
`preferential
`film devices were obtained using
`Thin
`techniqueI6.7] as shown in Figure 2. First. a backing substrate is adhered
`to
`the device
`surface of the silicon wafer.
`Then. most
`of
`silicon
`underlying the device layer is eliminated by grinding. and
`the
`residual
`part
`(50-locum)
`is removed by preferential polishing.
`The preferential
`polishing proceeds with the following two steps:
`{
`I
`) silicon reacts with
`the polishing liquid such as organic amine
`solution.
`producing
`silicon
`hydrate.
`and
`{
`2
`)
`the silicon hydrate is
`removed mechanically
`by
`a
`polishing pad.
`Since no reaction occurs between S102 and
`the polishing
`liquid.
`the polishing stops automatically at
`the LOCOS back surface[ Si02 3
`to give a thin film device.
`Figure 3 shows photographs of a NMOSFET formed
`on
`silicon substrate and the back—surface view of the thin
`film NMOSFET
`obtained.
`The
`thin film device layer. with the thickness
`of
`Zum. was
`mechanically stable because of the backing substrate support.
`
`3-2. Back surface wiring
`
`The electrical paths from the front surface to the back surface of the
`thin film device were made using the back surface wiring technology. After
`the preferential polishing { see Figure 3
`).
`the poly-Si
`and Mosi
`/Al
`patterns
`on
`the LOCOS front surface become visible from the
`LOCOS
`ack
`surface.
`thus
`enabling us to make the back surface patterns which
`are
`aligned with the front surface patterns. Namely.
`through-hole patterns and
`back surface H/Al wiring patterns are made on the LOCOS back surface.
`Figure
`4
`shows
`the patterns used
`for
`confirmation of electrical
`interconnection between
`the poly-Si wirings and the
`back
`surface H/A1
`wirings.
`The through—hole size was 2umx2um.
`The contact
`array obtained
`revealed an ohmic—contact property. an
`the cogtact resistance between
`the
`poly-Si and the U/Al wirings was 3x10’
`[ohm'cm ]
`
`3-3. Bump/pool Contact
`
`the
`using
`interconnections were made
`Device-to~device electrical
`The
`bonding
`as shown in Figure
`5.
`"bump/pool
`contact"
`technologyfa]
`mechanism is as the follows. At first.
`tungsten bumps. which are
`a
`high
`melting point
`conductive material. are formed
`on
`the polyimide-coated
`device
`layer.
`Au/In pools. where the alloy with low melting point
`is
`partially plugged
`in the polyimide film. are formed on the other device
`layer.
`These
`two layers are aligned by infrared microscopy with
`the
`w
`bumps
`Just over the Au/In pools.
`then heated above melting temperature
`of
`the Au/In alloy and put
`together.
`The device layers bond to each other due
`to the solid phase fixing force between the bumps and the pools. giving the
`device—to—device electrical interconnections.
`In addition.
`the polyimide to
`polyimide
`adhesion force helps the mechanical bonding between
`the device
`layers.
`fine-pitch
`making
`for
`advantageous
`is
`contact
`bump/pool
`The
`interconnection because the molten Au/ln alloy doesn't overflow during
`the
`bonding.
`The
`low bonding temperature below 400°C prevents
`the device
`layers from heat-damage.
`The third advantage is that
`the bump/pool contact
`has
`a stable bonding structure with not only horizontal but also vertical
`bonding tolerances.
`The horizontal and vertical
`tolerances are determined
`essentially by the resolving power of infrared microscopy and by the
`bump
`height. At
`the present
`time.
`the horizontal and vertical tolerances are of
`:3um and ;1.5um. respectively.
`electrical
`confirming
`for
`used
`Figure
`B
`shows
`the patterns
`interconnection between
`the Mosig/Al wiring and the W/Al wiring by
`the
`
`
`
`
`
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`MICRON ET AL. EXHIBIT 1055
`Page 2 of 6
`
`

`
`‘JTH SYMPOSIUM ON FUTURE EIJITRUN DEVICES
`November Id-I5. 1990 Makuhan‘. Chiba. Japan pp. 157.112
`
`the MoSi2;Al patterns on the one Si-
`technology. Here.
`contact
`bump/pool
`( Fig. 6(a)
`) were aligned with the W/Al patterns on
`the other
`substrate
`Si-substrate
`(
`Fig. 8(b} }.
`As shown in Figure 6{c).
`1.600
`links were
`electrically connected in the contact array with the bumps and the pools.
`The
`bump/pool contact revealed an ohmic contact pgoperty. and the
`contact
`resistance between the bump and the pool was 5x10’
`[ohm'cm ]
`
`1; Evaluation gnd applicgtion
`
`of
`
`layered
`active
`evaluate the CUBIC technology. a dual
`to
`In order
`layered
`device was fabricated.
`Figure 7 shows the steps for a dual active
`the
`device
`fabrication using CUBIC
`technology. which
`consists
`contact
`preferential polishing,
`the back surface wiring. and the bump/Pool
`technologies. First. NHOSFETB for the lat
`(
`lower } and the 2nd ( upper
`)
`layers
`are
`fabricated independently on silicon substrates.
`and
`then H
`bumps.
`the size of 2umx2um and the height of 2.0um. are fabricated on
`the
`MoSi2/Al wirings. After the backing substrate adhesion on the 2nd device
`layer
`( Fig.
`7(a) ).
`the silicon underlying the
`2nd
`device
`layer
`is
`removed
`by grinding and preferential polishing {
`Fig.
`7{b}
`3.
`Then.
`through-holes.
`the
`size of 3umx3um. back surface H/Al wirings
`and Au/In
`pools.
`the size of Bumxsum and the depth of 2.5um . are formed on the
`back
`surface ( Fig. Ttc) ).
`The thin film device obtained is used as a building
`block. Note that the pools on the back surface are electrically connected
`to
`the
`bumps. Next.
`the thin film NMOSFET for the 2nd layer
`is
`aligned
`over the bulk NMOSFET for the 1st
`layer using infrared microscopy. and then
`pressed together
`( Fig. 7{d)
`).
`The thin film NMOSFET
`is electrically
`interconnected to the bulk NMOSFET by the bump/pool contacts. Finally.
`the
`backing substrate
`and
`the adhesive on the 2nd
`NMOSFET
`are
`removed
`by
`etching ( Pig. 7(e)).
`active
`the dual
`photograph and schematic view of
`Figure
`B
`shows
`layered device obtained.
`The source and gate of the thin film NMOSFET
`(
`the
`2nd
`layer
`) were electrically interconnected to those of
`the
`bulk
`(
`NMOSFET
`the 1st layer )
`through the bump/pool contacts.
`The drains.
`on
`the other hand. were not connected each other.
`The drain currents of
`the
`thin film NMOSFET were lower than those of the bulk NMOSFET[9] as shown
`in
`Figure 9. Optimization of the preferential polishing will
`improve the thin
`film NMDSFET performance by reducing stress and/or crystal defects in
`the
`active
`silicon device area. Consequently.
`it is proved
`that
`the
`CUBIC
`technology
`is really applicable for making 3D—IC fabrication even
`though
`minor process refining is still needed.
`to
`Figure 10 illustrates application examples of the CUBIC technology
`as
`future
`electron device
`fabrications. Hulti-functional
`SD-IC such
`vertical stacking of memory and processor blocks will be realized with high
`production yield by using CUBIC
`technology
`( Fig.
`l0(a)
`).
`High
`performance multi
`layered
`IC will be fabricated by
`stacking thin film
`inter-CMOS devices as building blocks ( Figure l0(b)
`). since
`the
`inter-
`CMOS devices.
`in which
`PMOBFET is
`located above
`NMOSFET.
`have many
`advantages of latch-up-free structure and less photomasks required for
`ion
`implantation process steps[10].
`
`fig Sumary
`
`has
`CUBIC technology. which is a thin film device bonding technology.
`been developed.
`The
`thin film devices
`are made using preferential
`polishing technology.
`the vertical interconnections from the front
`surface
`of
`the
`thin film device to the back surface are made using back
`surface
`wiring technology. and the device—to—devica interconnections in the bonding
`structure are made by bump/pool contacts.
`device
`The
`advantages of CUBIC technology are its ability to make
`layers
`independently on
`bulk Si
`substrates
`using
`a
`conventional
`lC
`fabrication process.
`the lack of heat damage. and its short process
`TAT.
`Thus. CUBIC technology will be applicable to mass production of many
`kinds
`of 3D—lC possible.
`
`REFERENCES
`
`
`
`
`
`
`
`
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`
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`
`
`
`
`
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`O-l'DI"b-""§flJ{Kl--)|1‘-4UQ0i|El:l'|-|‘D|’J-UH
`
`11de I
`
`'D!-—"‘:'DQ.b—-r+(DflP.'—'r‘I‘-HO@{D"‘.\£fDf-‘ID-.'-'f|Hm
`
`
`
`
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`MICRON ET AL. EXHIBIT 1055
`Page 3 of 6
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`

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`!Tl'1-I SY!u1I>-‘USIUM ON FUTURE ELECTRO.\' DEVICES
`November I-1-15. I990 Makuhari.Chib:1. Japan pp. 357.173
`
`3. Samukawa et. 31.. 1990 VLSI Symp. Digest of technical paper. pp1(1990}.
`K. Hegge.
`IEEE Trans. Components. Hydrides end Manufacturing. Vol.
`No. 2. pp1'?D[19B9}.
`M. Koyanagi. Proc. 8th Symp. on Future Electron Devices. pp55[19B9).
`T. Kunio. et. 31.. 1989 IEDM Techn. Digest. pp83?(1989).
`'
`V. Hnyaehi. et. el.. 1590 Symp. on ULSI Techn.. Digest of Techn. Paper.op95
`90).
`T. Hamaguchi. et. ai.. 1985 IEDM Techn. Digest. pp6BB(l985].
`5. Made. et. 31.. Extended Abstract of the 6th intl. workshop on Future
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`Electron Devices. ppflltlflflfi).
`(B)
`Y. Heyaehi. et. all. Extended Abstracts (The 37th Spring Meeting. 1990}:
`The Japan Society of Applied Physics and Related Society. No. 2. pp593(1990).
`{9}
`S. Tekehashi. et. al.. Proc. 1990 IEEE SOS/S01 Technology Conference.
`in press.
`(10)
`T. Kunio. Proc. 7th Symposium on Future Electron Devices. pplQT(1988).
`
`technologies:
`
`Device thinning.
`
`Vertical wiring through
`the thinned device layers.
`-
`-
`Device-to«devI.ce alignment
`and bondi nz .
`
`2nd device
`
`3rd device
`,5‘.
`$eNeuvei'
`
`g ,\\V\\\\\\\.\'‘‘_
`1
`amende-
`“""5?«-§E%%fi'
`amzazyfii
`‘
`'
`///’///’£
`
`r E
`
`Concept of
`1
`Figure
`technologies involved.
`
`the CUBIC
`
`technology
`
`and
`
`the
`
`key
`
`HEEEEEEEE
`(I) Silicon reacts with
`polishing liquid euch
`an amine solution.
`forming silicon hydrate.
`The silicon hydrate is
`removed mechanically by
`the polishing pad.
`
`Figure 2 Device thinning Process using "preferential polishing".
`
`n.'\\\ax.-«.4 .
`‘-'6“--~.
`
`Back surface
`
`3 Photographs of (a) NMOSFET formed on a bulk Si-substrate
`Figure
`the back surface View of the thin film NMOSFET obtained by
`and
`(b)
`"preferential polishing‘.
`
`MICRON ET AL. EXHIBIT 1055
`Page 4 of 6
`
`

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`:S\'.\1i‘U:E1_‘\I UT‘; FL'TL!RE EU-.'i_"IRu.‘»' DI£\'|L'E:
`‘i'I'Ii
`Nuwlmtu-r 1-I-15. 1990 I\1akuhari.ChnI::1.Japan pp 3574?;
`
`HQ HEB EB
`
`_ ‘J 1-Ira-_
`
`Figure 4
`
`sequence of back—surface wirinfi process steps.
`
`Davmeiayer
`
`W bump
`
`AMI” 5300'
`
`I
`
`Dewcelayer
`
`TIIIIIIIIIIIIIII
`
`sectional
`cross
`Schematic
`5
`Figure
`interconnection using a bump/pool Contact.
`(0)
`
`views
`
`of
`
`device-to-device
`
`: HeSi2/Al
`
`RV-
`
`if
`SEM_pnotographs of (a) U bumps on M0512/A1 wiringsn
`{b} Au/In
`B
`Figure
`pools on w/Al wxrxngs. and (C) schematic cross sectional view and infrared-
`photograph
`of
`the device-to-device
`interconnections
`using
`bump/poo]
`COIIEBCES.
`
`
`
`
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`MICRON ET AL. EXHIBIT 1055
`Page 5 of 6
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`

`
`51TH 5'l':‘rll’0SlUM ON FUTURE EI.ECTRON DEVICES
`:\o-.'¢.-tuber I-H5. 1990 Makuharl. Chiba. .3393" DP. P.6'F~2'f2
`
`Device-to-Device
`Interconnecfion
`
`3 Through hole
`_
`___
`—__"E! , TI" :
`wee:-‘-’ Back surfafial
`Auiln P001
`
`__
`
`_
`
`U
`
`_
`
`}Thifi Film Device
`]-Bulk Si Device
`
`Sequence of the key process steps for a
`7
`Figure
`device fabrication using CUBIC technology.
`
`dual
`
`active
`
`layer-ed
`
`_ .-
`'
`_
`..
`Dual active layered device in which
`Figure 8
`8 thin film NMOSFET (the 2nd layer) is stacked
`on a bulk-NHOSFET (the lat layer);
`(a) photograph and lb] schematic diagram.
`
`Elect:-j_c31
`9
`Figure
`Pfflperties or the thin film
`NMOSE-‘ET(the 2nd layer) and
`the bulk NHOSFET (the 1st
`layer): L=1.5um. u=so.oum.
`
`’Processor
`
`7Mnflknhu —clos
`Imflao
`‘t
`
`electron device
`the CUBIC technology to future
`10 Application of‘
`Figure
`fabrication;
`ta) Multi-functional device.
`(b) Stacked inter-CMOS device.
`
`
`
`
`
`
`
`
`
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`MICRON ET AL. EXHIBIT 1055
`Page 6 of 6