Three-Dimensional IC Trends
`
`YOlCHl AKASAKA
`
`lnvited Paper
`
`VLSl will be reaching to the limit of minimization in the 7990s,
`and after that, further increase of packing density or functions
`might depend on the vertical integration technology.
`Three-dimensional (3-D) integration is expected to provide sev-
`eral advantages, such as 7) parallel processing, 2) high-speed o p
`eration, 3) high packing density, and 4) multifunctional operation.
`Basic technologies of 3-0 IC are to fabricate SO1 layers and to
`stack them monolithically. Crystallinity of the recrystallized
`layer
`in SO1 has increasingly become better, and very recently crystal-
`axis controlled, defect-free single-crystal area has been obtained in
`chip size level by laser recystallization technology.
`Some basic functional medels showing the concept or image of
`a future 3-0 IC were fabricated in two or three stacked active lay-
`ers.
`Some other proposals of subsystems in the application of 3-D
`issues for realizing practical 3-D lC,
`structure, and the technical
`Le., the technology for fabricating high-quality SO1 crystal on com-
`plicated surface topology, crosstalk of the signals between the
`stacked layers, total power consumption and cooling of the chip,
`will also be discussed in this paper.
`
`INTRODUCTION
`The ultimate IC structure of the future is thought to con-
`
`sist of stacked active IC layers sandwiched by insulating
`materials.
`Various devices or circuit functions, such as photosen-
`sors, logic circuits, memories, and CPUs, will be arranged
`in each active layer and, as a result, a remarkable improve-
`ment in packing density and functional performance will
`be realized.
`In 1979, it was reported that polysilicon deposited on in-
`sulator can be melted and recrystallized by laser irradiation
`[I] and that the crystal perfection of the layer can be ad-
`equate to allow the fabrication of devices.
`The quality of the recrystallized layer can be character-
`ized by carrier mobility. As shown in Fig. 1, the electron
`mobility reported so far has increased year by year and has
`attained a value comparable to bulk crystals. This improve-
`ment was a trigger for starting research and development
`Of 3-D ICs.
`A partial 3-D structure has already been tried for a dy-
`namic memory (DRAM) cell [2], [3]. For highdensity RAMS,
`
`1 1
`
`1
`
`o)
`
`8
`r
`1 0 0
`
`0 19m '79
`
`'80
`
`'81
`
`1
`
`0~ CW-LASER
`0 CW-EB
`A Zone Melting
`
`'e2 'e3
`
`Year
`Fig. 1. Progress of surface carrier mobility of MOSFET fab-
`laser; 0-electron beam; A-
`ricated on SO1 layer. 0-CW
`carbon strip heater.
`
`such as the CMbit DRAM, the area of the memory cell ca-
`pacitor is limited, so in order to increase the cell capaci-
`tance, a 3-D structure, i.e., a trench cell or a stacked ca-
`pacitor cell, has been tried. This partial 3-D structure will
`be used in 2-D VLSls within a few years.
`To achieve a breakthrough in the packing density of ad-
`vanced VLSls, it is reasonable to consider a 3-D structure,
`
`containing either partially or completely stacked active lay-
`ers. Fig. 2 shows a forecast of the development of 3-D ICs
`schematically, as 3-D technology progresses.This figurewas
`obtained from the 3-D IC Research Committee of the 3-D
`
`-
`
`-
`
`C
`
`Application 2 2-0 VLSl
`-
`
`Production
`
`Development for
`
`Manuscript received January 23,1986; revised August 8,1986.
`The author is with the LSI R & D Laboratory, Mitsubishi Electric
`Corporation, 4-1, Mizuhara, Itami, Japan.
`
`1 5 7 0
`
`Fig. 2. Forecast of progress of 3-D technology.
`
`PROCEEDINGS OF THE IEEE, VOL. 74, NO. 12, DECEMBER 1986
`
`-
`
`Year
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`1703
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`MICRON ET AL. EXHIBIT 1054
`Page 1 of 23
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`

`
`project directed by the MlTl of Japan. According to dis-
`cussion in the Committee, the basic technology for stack-
`ing active layers will be developed before 1990. With this
`
`technology, various kinds of circuits, such as high-packing-
`density memory, high-speed logic or image processors are
`expected to be designed and realized in a single chip be-
`tween 1990 and 2000.
`A 3-D IC for practical use is not available now, but func-
`tional models have been fabricated in stacked double or
`triple active layers demonstrating the concept of a future
`3-D IC.
`This paper describes SO1 process technology, which is
`the basic technology for fabricating 3-D structures, and the
`3-D devices which have already been fabricated in the lab-
`oratory. Features, problems, and trends in fabrication tech-
`
`nology as well as the design and architecture of 3-D devices
`will be discussed.
`
`the DRAMcell capacitor or the load resistor of a SRAM, will
`
`be stacked three-dimensionally similarly to the multilevel
`interconnections of today’s LSls. Fig. 3(c) shows 3-D inte-
`[5]. Load transistors
`gration performed at the transistor level
`cell are fabricated
`of a CMOS inverter of a CMOS static RAM
`in the upper layer to form a partial 3-D structure. The first
`3-D IC which has active elements or uses singlecrystal ma-
`terial in the stacked layer may havethe configuration shown
`in Fig. 3(c). Fig. 3(d) shows the stacked form of LSI layers in
`a complete 3-D structure, which is the final goal of the 3-D
`Project in Japan. In this structure, the degree of freedom
`in circuit or system design circuit layout, and the reliability
`of the interconnections are expected to be very high. This
`structure is one of the promising VLSI candidates of the
`future, and may represent a final configuration of VLSI.
`This paper will discuss mainly the trends in the kind of
`3-D structure shown in Fig. 3(d).
`
`3-D IC STRUCTURE
`Fig. 3 shows a typical basic structure of 3-D devices pro-
`posed by several researchers. Fig. 3(a) is a flip-chip, which
`is an attempt to realize the stacked 3-D form by chip as-
`sembly technology. This technology has already been used
`in computers as a connection between a group of single
`chips and a printed circuit board. In this technology, the
`number of connections are restricted by reliability and
`bump size constraints. Fig. 3(b) shows a new approach based
`on wafer process technology. The chips are attached face-
`to-face by pressure [4]. The minimum connection area is 10
`pm2, which is large compared with the device feature size
`(1-2 pm), but the number of connections will be greatly in-
`creased by this technology. Fig. 3(c) and (d) shows a mono-
`lithic 3-D structure. At first, the passive elements, such as
`
`FEATURES OF 3-D IC
`Although it is not well known what kinds of systems can
`best be realized in 3-D ICs as opposed to 2-D ICs, the ad-
`vantages expected for 3-D ICs are as follows:
`
`1) high packing density, or super large integration
`2) high speed
`3) parallel signal processing
`4)
`integration of many functions on a single chip.
`
`HIGH-PACKING DENSITY
`The fundamental advantage of 3-D integration, com-
`pared to 2-D integration, is in packing density. As the num-
`ber of integrated active layers increases, larger integration
`
`#2 CHIP
`
`VERTICAL /
`
`I MERCONNECTION
`
`BONDING PAD
`(a)
`
`P Substrate
`
`VERTICAL
`INTERCOFINECTION
`
`INSULATING
`LAYER
`
`(C)
`( 4
`Fig. 3. Basic concepts of 3-D device structure. (a) Two 2-D LSI connected by flipchip
`bonding. (b) Chip attachment by press. (c) Partially stacked structure in transistor level
`in monolithic 3-D IC. (d) Completely stacked LSI in 3-D monolithic structure.
`
`I
`
`I
`
`1704
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`PROCEEDINGS OF THE IEEE, VOL. 74, NO. 12, DECEMBER 1986
`
`MICRON ET AL. EXHIBIT 1054
`Page 2 of 23
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`

`
`INTEGRATION O F FUNCTIONS
`Integration of many functions is one of the special fea-
`tures of 3-D ICs. Each layer or set of several active layers can
`have its own function. At the device level, different types
`of devices, such as MOS and bipolar, and different char-
`acteristics provided by different process technologies, can
`be assigned to each active layer. It is possible to make use
`of these advantages for system design. Circuit selection
`(analog and digital) and the use of photosensors, light-emit-
`ting elements, and SAW devices can be implemented in a
`3-D chip. For example, it is possible to prepare a video sen-
`sor on the top layer, then an AID converter, ALU, memory,
`and CPU in the lower layers to realize an intetligent image
`processor in a multilayered 3-D structure.
`Optimization of system design becomes easy by the
`proper choice of the most suitable process and circuits for
`the corresponding active layer.
`SO; TECHNOLOGY (RECRYSTALLIZATION OF si)
`SO1
`There are three primary methods for fabricating
`structures: 1) solid-state epitaxial growth, 2) recrystalliza-
`tion of poly-Si by an energetic beam, such as a laser beam,
`an electron beam, or infrared light, and 3) buried SiOp for-
`mation in a Si crystal by oxygen implantation or anodic ox-
`idation.
`To fabricate 3-D ICs successfully, the wafer temperature
`during the crystallization should be kept low enough not
`
`to destroy or seriously change the performance of devices
`already fabricated in the lower layers. For this reason, laser
`or electron-beam recrystallization is thought to be suitable
`for 3-D IC fabrication. A laser or an electron beam with a
`diameter of around 100 pm is scanned across the wafer and
`
`selectively melts the poly-Si.The time that the poly-Si is mol-
`ten is on the order of several milliseconds, and the tem-
`perature of the substrate remains low.
`It is thought to be easier and more practical to recrys-
`tallize each small active area than to recrystallize a whole
`
`Laser Beam
`
`,O
`
`becomes possible. Input and output circuits which con-
`sume high electrical power are not required for every active
`layer. For instance, a IO-layer 3-D IC needs only one set of
`110 circuits. Accordingly, power dissipation per circuit
`function is extremely small in 3-D ICs compared to2-D ICs.
`Theoriginal advantages of integrated circuits, such as small
`size, light weight, and high reliability, are preserved even
`in 3-D IC structures.
`
`HIGH-SPEED PERFORMANCE
`High-speed performance is associated with shorter in-
`terconnection delay time and parallel processing. The in-
`crease of propagation delay due to a long interconnection
`line (higher resistivity, larger capacitance) is especially se-
`riousinthelatest2-DVLSIcircuits.Itispossibletoexchange
`signals between upper and lower active circuit
`layers
`through via holes in 3-D ICs. In 2-D ICs, the longest signal
`interconnection length becomes several toten millimeters,
`but in 3-D ICs the length between upper and lower layers
`is on the order of 1-2 pm. In addition, parasitic capacitance
`is considerably smaller in 3-D ICs, since the active elements
`are fabricated on the insulator. The transistor itself con-
`sequently exhibits excellent high-speed performance.
`For these reasons, twice the operating speed is possible in
`the best case of 3-D ICs. High-speed operation of SO1 dev-
`ices has been already verified by several pioneering res-
`earchers [6].
`signal transfer
`Shortening of interconnections and
`through vertical via holes in the 3-D configuration provides
`
`advantages for the design of large-scale systems. One of the
`restrictions on system design, that subsystems must be
`
`connected with the minimum number of connections pos-
`sible, may be mitigated. High-impedancedrivewill become
`possible, and the number of I/O buffers will be consider-
`ably decreased in a total system. The advantages will cause
`a major change in chip design and layout design.
`
`PARALLEL PROCESSING
`Parallel processing is expected to be realized more easily
`in 3-D structures. Several thousands or several tens of thou-
`sands of via holes are present in these devices, and many
`information signalscan be transferred from higher to lower
`layers (or vice versa) through them. The size of a via hole
`is 1-2 pm with present process technology. In 2-D LSls, the
`number of bonding pads which can be prepared on a chip
`limits the number of signals to be taken out. The maximum
`number of pads is now200-250 (Fig. 4). As a result of parallel
`processing, the signal processing speed of the system will
`be greatly improved.
`
`3 - D
`
`S T R U C T U R E
`
`2 - D
`
`S T R U C T U R E
`
`i
`I
`
`I
`I
`
`W I R I N G
`p a x 2 0 0 - - 2 5 0 P I N S
`V I A - H O L E
`Fig. 4. Wiring for parallel processing in 2-D and 3-D ICs.
`
`UnccmtroHed GB.
`C m o l k d G.B
`Fig. 5. Thermal profile in poly-Si under laser irradiation and
`thegeneration of grain boundaries in the recrystallized layer.
`The grain boundary was made visible by chemical etching.
`
`AKASAKA: THREE-DIMENSIONAL IC
`
`1705
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`MICRON ET AL. EXHIBIT 1054
`Page 3 of 23
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`

`
`POLY-SI CAP
`\
`
`0
`
`I
`
`-
`
`
`
`THERMAL FLOW
`Ti-ERMAL PROFILE
`
`SAMPLE -*
`
`SCAM I ffi
`OiROtTlON
`
`LASR BEAM
`
`--
`X-Y STAGE
`3
`0
`
`MOLTEN
`ZONE
`
`SINGLE
`CRYSTAL
`POLYCRYSTAL
`
`0
`
`SNGLE '
`CRYSTAL
`
`$-&-"I
`
`ELECTORCU
`
`DEFLECT
`COIL
`
`Y- DIRECTH
`
`DIRECTION 0
`
`ANTI-REFLECTING FILM
`
`RECRISTALUZEO SI
`
`WiNDOW
`
`63
`
`I
`
`BEAM
`
`~~
`
`Si-SBSTRATE
`
`SLSTRIPE
`
`'QUARTZ RATE
`
`POLY-Si
`
`SI02
`' U '
`THERMAL PROFILE 0
`
`0
`8
`Fig. 6. Various kinds of recrystallization methods to make a preferable thermal profile
`in the molten zone of the polysilicon. a) By the intensity profile of laser or electron-beam
`spot @ Beam profile change by using mask [8] (Stanford University, single crystal of 45
`pm X 50 am). @ Donut-type beam by oscillation mode modification [9] (Fujitsu, crystal
`of 600-nm length). 0 Beam-splitting type [IO] (NEC, crystallized area of 20 pm x 1 mm).
`@Double laser beams [Ill (Fujitsu, 20 pm; Matsushita, 1.8 mm). @ Electron-beam oscil-
`lation-oscillatory growth method [12] (AT&T Bell Labs., 50 pm x 50 pm). @ Quasi-linear
`electron beam (loshiba, Tokyo Institute of Technology, 300 pm). b) By patterning the an-
`tireflection thin film or absorption layer on the top of the polysilicon (selective recrys-
`tallization).@Stripe-patterned antireflecting thin film [I31 (CNET, Mitsubishi, 20pm x 400
`pm).@Patterned antireflectingthinfilm [14](Fujitsu).@Changing the reflectivity(m0ated
`island) [I51 (General Electric, 18 pm x 50 pm). @Indirect heating [I61 (Fujitsu, 20 pm X 60
`pm). 0 Double poly-Si layer recrystallization (Sharp). c) By modifying the heat transfer
`from molten zone of poly-Si. @Locos island (edge heating [I7 (TI, HP, Mitsubishi, Mat-
`sushita, Sharp, 10 pm X 50 pm). @Buried-stripe structure [I81 (NEC, 12 pm X 500 pm).
`@Relief structure of SiO, (control of thermal flow to a substrate) (Mitsubishi, 8 pm X 200
`pm). @Heat sink structure (Fujitsu).
`
`wafer. The basic concept of recrystallization of restricted
`active areas is to form two adjacent thermal peaks or a pe-
`riodic temperature profile, as shown in Fig. 5. Crystalliza-
`tion from one nuclei or polysilicon is possible by this
`
`method, and the crystal growth proceeds along the desired
`direction from one seed, realizing single-crystal growth of
`the desired area.
`Fig. 6 summarizes specific methods of realizing the pref-
`erablethermal profile in the molten zoneof the polysilicon:
`a) shaping the intensity profile in the laser or electron
`beam itself;
`
`b) obtaining a thermal profile by changing the energy
`absorption characteristics by patterning the antire-
`flecting thin film or absorption
`layer on the top of the
`polysilicon;
`c) changing the heat transfer selectively bythe material
`design of the sample structure.
`Crystal quality is evaluated by a variety of methods, such
`laser-Raman spectroscopy, and the etch-pit grid
`as TEM,
`method (observation of the pit figure which appears de-
`pending on the crystal axis after etching). More direct
`methods are to evaluate the carrier mobility and leakage
`
`1706
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`
`MICRON ET AL. EXHIBIT 1054
`Page 4 of 23
`
`

`
`process steps including the effects of thermal heat shock
`
`by energetic beam irradiation of the upper layers. We must
`use refractive metal or its silicide for interconnections of
`3-D ICs [20]. Doped polysilicon can also be used when the
`circuit design allows for the consequent low propagation
`speed.
`
`current of MOS transistors fabricated in the recrystallized
`area.
`The characteristics of a "good" transistor are quite com-
`parable with those of a bulk device. The problem is the vari-
`ation of the characteristics across a wafer, which is one or-
`der of magnitude larger than that of the bulk. This variation
`is primarily caused by two effects: crystal defects, such as
`small-angle grain boundaries; and poor or no control of the
`Via Holes
`crystal axis. In order to eliminate the crystal defects or to
`Fine patterning and etching of via holes to connect the
`lower their density, experimental techniques are being re-
`upper and lower active layers are more difficult compared
`
`fined by stabilizing the intensity of the energetic beam, scan
`with multilevel metallization in 2-D LSls because the aspect
`speed, and position accuracy. To gain more control of the
`ratio of the via hole increases to 2 or 3 (i.e., 1-pm square hole
`crystal axis, the so-called lateral-seeding method [;7 must
`with a height of 2-3 p n ) . Selective growth or deposition of
`be improved.
`conductive materials and an accurate etching technology
`are required forthefabrication ofvia holes in highlypacked
`3-D LSIS.
`
`OTHER PROCESS TECHNOLOGY REQUIRED FOR FABRICATING
`3-D ICs
`Planarization o f the Stacked Surface
`3-D stacked structures present problems for recrystalli-
`zation technology that are not encountered in the fabri-
`cation of simple SO1 structures [19].
`1) The insulator surface and the poly-Si surface, where
`crystal growth takes place, are not flat.
`2) Several kinds of materials with different thermal con-
`ductivities are stacked in acomplicated manner in the lower
`layers.
`Thesecharacteristics perturb the ideal thermal profileand
`hence disturb smooth crystal growth. To resolve problem
`I), surface planarization technology more accurate than that
`required for conventional 2-D LSls is required. Planariza-
`tion by reflow of silicate glass (PSG or BPSG), sputter etch-
`ing [20], spin-on-glass coating, and etch-back technology
`with an organic resist material [21] are used to planarize the
`surface within kO.1 pm. Fig. 7 shows the surface planar-
`ization obtained by etch-back technology [21].
`The technology needed to overcome problem 2) is not
`established. The methods mainly used are to overcome the
`fast heat transfer to the bulk by putting an antireflecting
`material selectively above
`the area of high thermal con-
`ductivity, or to have a thicker inter-insulating layer to re-
`duce the variations in heat transfer across the wafer [19].
`
`Interconnection Material
`The interconnection material must not be degraded by
`the heat treatment employed
`in subsequent fabrication
`
`(b)
`Fig. 7. SEM photographs of cross section of five-level poly-
`silicon structure. (a) Without planarization process. (b) With
`planarization process.
`
`sum
`
`Low-Temperature Processing
`Process temperatures should be lowered enough not to
`
`redistribute the impurities in the lower active layers already
`fabricated.
`Fig. 8 shows an S E M cross-sectional photograph and a
`schematic drawing of a 3-level, 3-D IC fabricated by using
`some of the technologies mentioned above [22].
`The first layer is fabricated by 3-pm NMOS technology in
`the bulk; the second layer by 3-pm CMOS technology in the
`Sol; and the third (Sol) layer by 3-pm NMOS technology.
`Each layer has its own interconnection and can be oper-
`ated independently. Each active layer is connected elec-
`trically through via holes, and signals can be transferred
`between the layers.
`Fig. 9 shows the TEG (lest
`Element Group) and the fab-
`rication masks used for testing the 3-D structural device.
`Fig. 10 summarizes the V-I characteristics and the carrier
`
`mobilityfor MOS transistors fabricated in threestacked lay-
`ers. The mobilities obtained in the second and third layers
`are slightly smaller than that of the bulk, but the difference
`of the mean value is rather small [22]. The mobility of the
`transistors which show good I-V characteristics is almost
`the same as that of the bulk. The problem is the large vari-
`ation of the mobility caused by the generation of grain
`boundaries in the active layer and by differences in the re-
`cyrstallized crystal axis, which is not closely controlled in
`this work.
`In future circuits, which may be operated with a power
`supply voltage of around 3 V, more accurate control of the
`threshold voltage will be required; hence, a method for
`crystal axis control, such as lateral seeding, must be de-
`veloped.
`
`FABRICATED FUNCTIONAL MODEL OF THE 3-D IC
`Several small-scale test devices have been fabricated in
`the laboratory. Fig. 11 shows an image processor, one of the
`model systems that might be realized with a 3-D IC. Because
`this kind of system is conventionally very heavy and mas-
`sive, its use has been limited. If the image processor with
`a proper level of intelligence could be realized in a single
`chip, the range of applications would be considerably wid-
`ened.
`We divided a model system tentatively into two parts and
`converted each to simplified functional models: a 10-bit lin-
`ear image sensor, which corresponds to the image sensor
`in a final 3-D device, and a 256-bit static RAM. [23], which
`
`AKASAKA: THREE-DIMENSIONAL IC
`
`1707
`
`MICRON ET AL. EXHIBIT 1054
`Page 5 of 23
`
`

`
`layer
`
`
`
`active
`
`
`
`3rd
`
`-
`--
`/oc(ivclclyw fi 1 Pm
`
`IcyDsi02
`
`
`
`passivation
`
`
`
`2nd g a l e 3 r d g a l e
`r
`
`Fig. 8. SEM cross-sectional photograph and a schematic drawing of planarized triply
`stacked IC layers fabricated by utilizing etch-back technology and laser recrystallization
`of poly-Si.
`
`Sersor TEG
`Shift Resisters
`
`T r a n s l s t o r s
`Test C i r c u i t s
`
`~
`
`n
`
`Triple Active Layers
`Test Chip
`
`Fig. 9. Photograph of test chip of 3-D IC and the pattern data of TEG in each layer.
`
`corresponds to the function of logic-in-memoryor memory
`and CPU. Both simplified devices have been fabricated in
`a stacked structure with two active layers.
`Fig. 12 shows a block diagram of a 256-bit static RAM with
`double active layers [23]. Memory cells composed of six en-
`hancement-mode (E/E type NMOS! transistors were fabri-
`Chip size
`cated in the first layer (Si substrate), and a peripheral circuit
`50
`
`Cell size
`such as a sense amplifier, an 110 circuit, or a decoder in the
`
`
`Supply voltage
`At supply voltage of 5 V
`second (Sol) layer. The first and second layers were con-
`
`Address access
`time
`nected electrically through 112 via holes of 4pm2 size. De-
`
`
`Active power dissipation
`tailed features of the chip are presented in Table l , and a
`
`Table 1 Features and Performance of 256-bit Static RAM
`Fabricated in Stacked Structure
`Organization
`Technology
`
`static RAM
`
`
`
`256 X 1 bit
`
` full
`3-D structure
`bottom layer NMOS
`top layer
`CMOS
`2.6 x 1.9 mm2
`x 70 pmZ
`4-8 v
`120 ns
`
`100 mW
`
`1708
`
`PROCEEDINGS OF THE IEEE, VOL. 74, NO. 12, DECEMBER 1986
`
`MICRON ET AL. EXHIBIT 1054
`Page 6 of 23
`
`

`
`photograph of the memory chip with double active layers
`is shown in Fig. 13.
`The memory function was observed for supply voltages
`varying from 4 to 8 V. Address access time at 5 V was 120
`
`Fig. 10. Transistor characteristics
`layers.
`
`in three stacked active
`
`\ J/ L i g h t tc
`
`Fig. 13. Chip photograph of 256-bit static RAM fabricated
`in stacked double active layers as a functional model of
`3-D IC. (Configuration of RAM is shown in Fig. 12.)
`
`---1
`r - - - - - -
`
`0-
`
`Slgnal
`Processlng-
`
`Slgnal -
`Processing
`System
`
`U
`output
`
`Synchronous
`Slgnol Generation
`Clrcutt
`Fig. 11. Schematic block diagram ,of an image processor
`system.
`
`ps, and power consumption was 100 mW. This memory in
`the stacked layers verified that it is possible to access the
`memory address from the upper layer and to take out the
`bit signal to the upper layer from the memory cell in the
`bottom layer. The performance of the RAM has confirmed
`its ability to handle the basic functions of a 3-D structural
`IC: inter-layer signal transfer as well as internal signal trans-
`fer in the layers.
`Fig. 14 shows an elemental circuit of a stacked photo-
`sensor fabricated in double active layers [24]. A photodiode
`with a shallow p-n junction is formed in the second SO1
`
`I
`
`'
`
`
`
`CIRCUIT DIAGRAM of 3-D SRAM
`
`/ / A /
`
`A D D R E S S ! 5 - 0 ;
`
`T O P L A Y E R
`
`Fig. 14. Basic elemental configuration of the stacked pho-
`tosensor and detecting circuit.
`
`layer. Junction characteristics are comparable to those
`found in the bulk. The leakage current was less than
`,Wpm2.
`The sensitivity spectrum of the SO1 photosensor is shown
`in Fig. 15. The spectral sensitivity at the human peak-sen-
`sitive wavelength, 550 pm, was comparable to that of the
`bulk, because the thickness of the SO1 layer (0.7 pm) was
`designed to be greater than that of the other active layers
`
`Fig. 12. Block diagram of stacked 256-bit static RAM.
`
`AKASAKA: THREE-DIMENSIONAL
`
`IC
`
`1709
`
`MICRON ET AL. EXHIBIT 1054
`Page 7 of 23
`
`

`
`Si -SUBSTRPTEp
`
`I
`
`layer [21], [25]. This method can realize the three active layer
`structure by recrystallizing only the
`second layer, easily
`yielding a-Si/SOl/bulk structure. Very primitive photosen-
`sors and processors were fabricated in three stacked layers
`as shown in Fig. 18. This test device is composed of an a-Si
`
`700
`"
`
`'
`'
`'
`600
`5bo
`WAVELENGTH (nrn)
`Fig. 15. Sensitivity spectrum of the SO1 photosensor for
`visible light wavelength.
`
`U
`
`o:c€l
`
`'
`
`(0.5 pm) to gain better photosensitivity. Nevertheless, the
`SO1
`photosensitivity in the longer wavelength region of the
`
`photosensor was likely to be inferior to that of the bulk be-
`cause of the limited active-layer thickness.
`A signal-processing circuit was fabricated in the first ac-
`tive layer. The circuit contains a pulse generation circuit,
`shift registers, and a readoutcircuit,which are shown in Fig.
`14. The function of the stacked photosensor i s shown in Fig.
`16, which shows "L" level in the dark area and "H" level
`in the light.
`
`50 p5a
`Fig. 16. Functional performance of the stacked photosen-
`sor and detecting circuit [24].
`
`A 10-bit linear image sensor was composed by serial time
`driving of 10 elemental pairs of photosensors and signal
`processing circuitswith shift registers. Signal output is seen
`in Fig. 17with the corresponding spatially illuminated pho-
`tosignals to the linear sensor.
`Some attempts have been made to use an amorphous Si
`
`photosensor instead of a p-n diode in the recrystallized SO1
`
`Fig. 17. Examples of output signals of stacked 10-bit linear
`image sensor corresponding to thevarious photo input data
`patterns [24].
`
`1710
`
`t B u L K 1
`
`OUT
`-mJ-
`Fig. 18. An a-Si photosensor and primitive processing cir-
`cuits fabricated in three stacked layers [21].
`
`photosensor on the tpp (third layer), a signal conversion
`circuit to digital 2 values "1," "0" (second layer, Sol), and
`the select logic circuit (bulk). The circuit has been shown
`to work as a primitive signal processor. An interesting chal-
`lenge for this kind of device is to save the failure bit or to
`have the circuit test itself, both of which will be major prob-
`lems in future large-scale integrated 3-D devices. The re-
`sults of fabricating primitive test circuits for image pro-
`cessors or gate arrays have also been reported by other
`workers in japan [25], [26].
`
`PROBLEMS OF STACKED STRUCTURES
`Potentially serious problems in future 3-D devices in-
`clude the high total chip power dissipation and crosstalk
`between the circuit layers.
`
`Power Dissipation and Heating of the Chip
`The junction temperature of the 3-D device is principally
`
`determined by the power consumption and the thermal re-
`sistivity of the chip.
`The total amount of heat dissipation allowed for a single
`chip is principallydetermined bythethermal resistivityfrom
`
`the junction to the outside of the case. The concept of ther-
`mal resistivity is schematically shown in Fig. 19. Since the
`thermal resistivity from inside the package to the outside
`is 40-7OoC/W in the case of air cooling, the thermal flow is
`limited by this factor. The heating problem in a 3-D IC is
`essentially the same as in 2-DVLS1, as long as the integration
`level of the devices is the same.
`Thermal resistivity in a 3-D structure has been roughly
`
`estimated as a function of the number of stacked active lay-
`ers (Fig. 20). We assumed for the calculation that the thick-
`nesses of the active layer (Si) and the intermediate insu-
`lating layer (SOz) are 2 and 1 pm, respectively. Only a slight
`increase of thermal resistivity is observed with the increase
`of the active layers.
`The problem in the 3-D case arises from the total power
`
`
`
`
`
`PROCEEDINGS OF THE IEEE,
`
`VOL. 74, NO. 12, DECEMBER 1986
`
`MICRON ET AL. EXHIBIT 1054
`Page 8 of 23
`
`

`
`i\:
`
`JUNCTION
`IN THE CHP
`
`CHIP
`
`CASE
`
`SYSTEM
`
`SYSTEM
`
`BUILDING
`
`ALUMINA
`
`PASSIVATION LAYER LS102)
`ACTIVE LAYER
`
`q
`
`EARTH
`
`(b)
`Fig. 19. Schematic thermal resistivity diagram corresponding to chip
`IC. (b) 2-D IC.
`
`structure. (a) 3-D
`
`.'
`
`I
`
`I
`
`
`
`y 0.1 y 0.1
`
`(3-0 I C )
`
`0.0 I
`
`1 2 3 4 5 6 7 8
`2-'D IC
`NUMBER OF ACTIVE LAYERS
`(STACKED 1
`Fig. 20. Calculation result of the thermal resistivity for 3-D
`I c.
`
`consumption caused bythe huge number of integrated de-
`vice elements in th.e 3-D structure. When one device ele-
`ment dissipates 5 pW, the total power dissipation will be
`25 W if 5 million elements are integrated on a chip. This
`
`requires fan cooling. If the integration level reaches 10 mil-
`lion elements, the 50-W power consumption would require
`liquidcooling.Inanycase,aninnovationinpackagingtech-
`nology will be necessary as 3-D technology evolves.
`
`Crosstalk of the Signal Between the Stacked Active Layers
`As device sizes become smaller, crosstalk (electrical cou-
`pling) between adjacent active elements or interconnec-
`tions becomes a serious problem. In 3-D structures, in ad-
`dition to this phenomenon, crosstalk between
`stacked
`active layers, which can be called vertical crosstalk, is also
`a consideration. This crosstalk in the vertical direction oc-
`curs when the conventional IC
`layers are stacked mono-
`lithically [27. Observed examples of interference between
`the upper and the bottom layers included: 1) dc bias from
`the bottom layer, i.e., the influence of the potential change
`of the bottom layer on the back channel of SOVMOS tran-
`
`sistors, 2) a high-frequency signal provided from the back
`gate to the SO1 transistor.
`I) Effect of DC Back-Gate Bias on the Back Channel of
`the SO/ Transistor: As shown in Fig. 21, the back bias is oc-
`casionally provided either intentionally or unintentionally
`from the bottom layer through a relatively thick insulating
`layer in the 3-D IC. This is not usually seen in conventional
`2-D ICs.' Though the threshold voltage of the back gate de-
`pends on the impurity concentration and the quality of the
`Si-SiO, interface, the influence of the back bias is rather
`small if the transistor and the crystal of the SO1 layer are
`perfectly fabricated, as shown in Fig. 21. But this phenom-
`enon obviously affects the design of t