PATENT
`Serial No. 12/405,240
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`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
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`APPLICANT:
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`Glenn J. Leedy
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`CONFIRMATION NO.:
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`3222
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`SERIAL NO.:
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`FILING DATE:
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`l2/405,240
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`03-17-2009
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`TITLE:
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`Three dimensional structure mcmory
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`EXAMINER:
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`CHIU, TSZ K
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`ART UNIT:
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`2822
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`Mail Stop Appeal Brief - Patents
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`Commissioner for Patents
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`P.O. Box 1450
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`Alexandria, VA 22313-1450
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`APPEAL BRIEF
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`Dear Sir:
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`This paper is in support of a Notice of Appeal filed 04-05-2013, of the Office Action
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`dated December 5, 2012, to the Board of Patent Appeals and Interferences.
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`MICRON ET AL. EXHIBIT 1031
`Page 1 of 22
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`TABLE OF CONTENTS
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`PATENT
`Serial No. 12/405,240
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`Real Party in Interest
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`Related Appeals and Interferences
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`Status of Claims
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`Status of Amendments
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`Summary of Claimed Subject Matter
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`Grounds of Rejection to be Reviewed on Appeal
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`Argument
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`Claims Appendix
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`Evidence Appendix
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`Related Proceedings Appendix
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`MICRON ET AL. EXHIBIT 1031
`Page 2 of 22
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`REAL PARTY IN INTEREST
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`PATENT
`Serial No. 12/405,240
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`Glenn J. Leedy.
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`MICRON ET AL. EXHIBIT 1031
`Page 3 of 22
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`PATENT
`Serial No. 12/405,240
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`RELATED APPEALS AND INTERFERENCES
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`MICRON ET AL. EXHIBIT 1031
`Page 4 of 22
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`STATUS OF CLAIMS
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`Claims 1-21 have been finally rejected and are on appeal.
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`Serial No.
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`MICRON ET AL. EXHIBIT 1031
`Page 5 of 22
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`STATUS OF AMENDMENTS
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`PATENT
`Serial No. 12/405,240
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`A11 amendments have been entered. No Response After Final has been submitted.
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`MICRON ET AL. EXHIBIT 1031
`Page 6 of 22
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`SUMMARY OF CLAIMED SUBJECT MATTER
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`PATENT
`Serial No. 12/405,240
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`The invention relates to stacked integrated circuits. Multiple substantially flcxiblc
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`integrated circuits having topside and bottom—side surfaces are stacked in relation to one another,
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`wherein at least one of the substantially flexible integrated circuits comprises a substantially
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`flexible semiconductor substrate made frorn a semiconductor wafer thinned by at least one Of
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`abrasion, eteliing and parting to expose a surface, and subsequently polislling the exposed
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`surface to forrn a polished surface. Interconnections electrically connect the plurality of
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`substantially flexible integrated circuits, wherein the interconnections are formed only on the topside
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`The following correspondence between the elements of claim 1 and the specification is
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`illustrative and is provided for convenience:
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`ELEMENT
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`1. A stacked integrated circuit
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`comprising:
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`a plurality of substantially
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`flexible integrated circuits
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`having topside and
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`bottom—side surfaces, wherein
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`said integrated circuits are
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`one another,
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`FIGURE(S)
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`103a, FIG. 1b
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`SPECIFICATION
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`Page 6, lines 12-21
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`wherein at least one of the
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`substantially flexible
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`integrated circuits comprises a
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`substantially flexible
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`from a semiconductor‘ wafer
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`thinned by at least one of
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`abrasion, eteliing and parting
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`to expose a surface, and
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`subsequently polishing the
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`exposed surface to form a
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`polished surface; and
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`Page 14, line 26 to page 18,
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`line 14. Note especially page
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`15, lines 4-6.
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`Figs. 2a, 2b, 2c, and 5
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`Page 12, lines 17-28
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`interconnections electrically
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`connecting the plurality of
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`flexible integrated circuits,
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`MICRON ET AL. EXHIBIT 1031
`Page 7 of 22
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`are formed only on said
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`PATENT
`Serial No. 12/405,240
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`MICRON ET AL. EXHIBIT 1031
`Page 8 of 22
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`GROUNDS OF REJECTION TO BE REVIEWED ON APPEAL
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`Whether claims 1-21 are unpatentable over Leedy in View of Lin.
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`PATENT
`Serial No. 12/405,240
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`MICRON ET AL. EXHIBIT 1031
`Page 9 of 22
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`PATENT
`Serial No. 12/405,240
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`ARGUMENT
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`The rejection states in part:
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`[L]eedy did not teaches (sic) wherein at least one of the first layer of material and
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`the second layer of material is substantially flexible.
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`Lin discloses wherein at least one of the first layer of material and the second
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`layer of material is substantially flexible. (column 2, lines 23-26).
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`Therefore, it would have been obvious at the time the invention was made to a
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`person having ordinary skill in the art to include only a flexible circuit since the
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`flexible circuit will be improved in an integrated circuit design that will permit the
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`IC device to have very large pin or connection counts, but remain flexible over its
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`body to withstand lateral mechanical displacement due to thermal or physical
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`Whereas Leedy relates to stacked integrated circuits, Lin relates to flexible printed circuit
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`boards, or “flex circuits.” In the case of stacked integrated circuits, the substrate is a
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`semiconductor substrate. In the case of flex circuits, the substrate is plastic. Semiconductor
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`material can withstand high temperatures used in semiconductor processing, for example
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`temperatures of 1200 degrees C or more. Plastic cannot withstand anything close to such
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`temperatures; plastic can withstand temperatures of at most a few hundred degrees C.
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`As illustrated in FIG. 2 and FIG. 3 of Lin, Lin provides an intermediate structure that
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`allows an integrated circuit to be wire bonded to a flex circuit 20, with the flex circuit 20 in turn
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`being surface mounted to another flex circuit 58 of a larger assembly. Thermal stresses arising
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`during operation of the IC may therefore be absorbed in the intermediate structure without
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`affecting the surface mount bonds.
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`MICRON ET AL. EXHIBIT 1031
`Page 10 of 22
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`Serial No.
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`PATENT
`l2/405,240
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`The Proposed Combination Fails to Arrive at Claimed Features
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`A stacked integrated circuit like that of Leedy could be mounted to a flex circuit using the
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`technique of Lin. However, since Lin fails to teach or suggest a substantially flexible
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`semiconductor substrate made from a semiconductor wafer, the combination would still fail to
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`teach or suggest the features of claimed invention. As noted above, the substantially flexible
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`substrate in Lin is a plastic (i.e., polyimide) substrate, not a semiconductor substrate.
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`It should be noted that Lin teaches nothing about the manufacture of the [C itself; Lin
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`concerns itself solely with IC packaging offinished ICs. Hence, whereas Lin may legitimately be
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`read as teaching how to package a finished IC (whether stacked or not stacked), Lin cannot be
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`read as teaching anything concerning how to make an IC (whether stacked or not stacked).
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`Applicant submits that any attempt to read into Lin any such teaching or suggestion would be the
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`result not of an impartial reading of the references themselves but of impermissible hindsight.
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`Dependent Claims
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`The rejection cites various passages of Leedy as supposedly teaching the features of
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`various ones of the dependent claims. In many instances, reliance on these passages is misplaced.
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`Examples of such misplaced reliance include the following:
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`LEEDY CITE
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`COMMENT
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`Teaches a generic circuit membrane;
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`does not teach microprocessor as
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`crystal semiconductor substrate; does
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`not teach at least one conductive path
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`that passes through a substrate of a
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`substantiall
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`DEPENDENT
`CLAIM
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`Col. 2, lines 56-65
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`MICRON ET AL. EXHIBIT 1031
`Page 11 of 22
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`and is insulated by an insulation
`material from the substrate as claimed.
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`In Leedy, conductive paths pass
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`semiconductor material; they do not
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`Teaches circuit membrane probe card
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`and its probing capabilities; does not
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`one of the plurality of substantially
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`flexible integrated circuits being
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`Other than Fig. 25, which is irrelevant,
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`teaches generic three dimensional
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`circuit membranes; does not teach
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`memory array, circuitry for generating
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`a gate control signal, and controller as
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`Teaches a generic circuit membrane;
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`does not teach a plurality of vertical
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`interconnects, each of the vertical
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`interconnects comprising a conductive
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`center portion and an insulating portion
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`surrounding the conductive center
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`portion as claimed. In Leedy, since
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`vertical interconnects do not pass
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`through substrate, no insulating portion
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`Col. 30, lines 25-48
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`Fig. 8
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`442-1, 442-2, Fig. 25
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`742-1, 742-2, 742-3, Fig. 32a
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`35. Fig. 3b
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`MICRON ET AL. EXHIBIT 1031
`Page 12 of 22
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`For the foregoing reasons, claims 1-63 would not have been obvious from Leedy in View
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`of Lin. Applicant therefore respectfully requests that the rejection be REVERSED.
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`PATENT
`Serial No. 12/405,240
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`Respectfully submitted,
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`/Michael J. Urc/
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`Michael J. Ure
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`Reg. No. 33,089
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`Dated: 6/03/2013
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`19925 Stevens Creek Blvd. #100
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`Cupertino, CA 95014
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`Tel. (408) 674-0271
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`Fax. (408) 446-3927
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`MICRON ET AL. EXHIBIT 1031
`Page 13 of 22
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`PATENT
`Serial No. 12/405,240
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`CLAIMS APPENDIX
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`1. A stacked integrated circuit comprising:
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`a plurality of substantially flexible integrated circuits having topside and
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`bottoin-side surfaces, wherein said integrated circuits are stacked in relation to
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`one another, wherein at least one of the substantially flexible integrated Circuits Comprises a
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`substantially flexible semiconductor substrate made from a semieoiicluctor Wafer thinned by at
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`least one of abrasion, eteliing and parting to expose a. surface, and subsequently polislrlng the
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`exposed surface to forrn a polished surface; and
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`interconnections electrically connecting the plurality of substantially
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`flexible integrated circuits, wherein the interconnections are formed only on said
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`2. The apparatus of claim 1, wherein at least one of the plurality of substantially flexible integrated
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`circuits has a thickness of one of 10 microns or less and 50 microns or less.
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`3. The apparatus of claim 1, wherein at least one of the plurality of substantially flexible integrated
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`circuits comprises one of a single crystal semiconductor material and a polycrystalline semiconductor
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`material.
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`4. The apparatus of claim 1, wherein the plurality of substantially flexible integrated circuits
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`comprise one of a logic integrated circuit and a memory integrated circuit.
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`5. The apparatus of claim 4, wherein the logic integrated circuit is a microprocessor integrated
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`circuit.
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`MICRON ET AL. EXHIBIT 1031
`Page 14 of 22
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`PATENT
`Serial No. 12/405,240
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`6. The apparatus of claim 1, wherein the plurality of substantially flexible integrated circuits
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`comprise logic integrated circuits.
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`7. The apparatus of claim 1, wherein at least two of the interconnections electrically interconnecting
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`the plurality of substantially flcxiblc integrated circuits are Vertical interconnections.
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`8. The apparatus of claim 1, wherein at least one of the plurality of substantially flexible integrated
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`circuits is formed with a low stress dielectric.
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`9. The apparatus of claim 8, wherein the low stress dielectric is at least one of a silicon dioxide
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`dielectric, an oxide of silicon dielectric and caused to have a stress of about 5 x 108 dynes/cmz or
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`less.
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`The apparatus of claim 1, wherein at least two of: at least one of the substantially flexible
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`integrated circuits comprises dielectric having a stress of about 5 x 108 dynes/cmz or less; the
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`dielectric is at least one of silicon dioxide and an oxide of silicon; at least one of the
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`substantially flexible integrated circuits has one of logic circuitry and memory circuitry formed
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`thereon; at least one conductive path passes through a substrate of a substantially flexible
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`integrated circuit and is insulated by an insulation material from said substrate.
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`The apparatus of claim 1, wherein at least three of: at least one of the substantially
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`flexible integrated circuits comprises dielectric having a stress of about 5 x 108 dynes/cm2 or
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`less; the dielectric is at least one of silicon dioxide and an oxide of silicon; at least one of the
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`15
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`MICRON ET AL. EXHIBIT 1031
`Page 15 of 22
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`substantially flexible integrated circuits has one of logic circuitry and memory circuitry formed
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`thereon; at least one conductive path passes through a substrate of a substantially flexible
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`integrated circuit and is insulated by an insulation material from said substrate.
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`Serial No.
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`PATENT
`l2/405,240
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`12.
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`The apparatus of claim 1, wherein at least four of: at least one of the substantially
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`flexible integrated circuits comprises dielectric having a stress of about 5 x 108 dynes/cmz or
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`less; the dielectric is at least one of silicon dioxide and an oxide of silicon; at least one of the
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`substantially flexible integrated circuits has one of logic circuitry and memory circuitry formed
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`thereon; at least one conductive path passes through a substrate of a substantially flexible
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`integrated circuit and is insulated by an insulation material from said substrate.
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`13.
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`The apparatus of claim 1, comprising at least one conductive path that passes through a
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`substrate of a substantially flexible integrated circuit and is insulated by an insulation material
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`from said substrate, wherein said substrate is a monocrystalline semiconductor substrate.
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`l4.
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`The apparatus of claim 1, wherein the bottom—side surface of at least one of the plurality
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`of substantially flexible integrated circuits is polished.
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`15.
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`The apparatus of claim 1, wherein data processing is performed by at least two of the
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`substantially flexible integrated circuits in cooperation with one another.
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`MICRON ET AL. EXHIBIT 1031
`Page 16 of 22
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`PATENT
`Serial No. 12/405,240
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`16.
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`The apparatus of claim 1, further comprising:
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`a memory array having a plurality of memory cells, a plurality of data lines, and a
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`plurality of gate lines, each memory cell storing a data value and comprising circuitry for
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`coupling that data value to one of said data lines in response to a gate control signal on one of
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`said gate lines;
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`circuitry for generating a gate control signal in response to an address, including means
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`for mapping addresses to gate lines; and
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`a controller for determining that one of said memory cells is defective and for altering
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`said mapping to eliminate references to said one of said memory cells.
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`17. The apparatus of claim 1, wherein said interconnects comprise a plurality of vertical
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`interconnects, each of said vertical interconnects comprising a conductive center portion and an
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`insulating portion surrounding the conductive center portion.
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`18. The apparatus of claim 17, wherein the insulating portion surrounding the conductive center
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`portion of said vertical interconnects comprises a dielectric material having a stress of 5 X 108
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`dynes/cmz or less.
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`19. The apparatus of claim 17, wherein at least one of the following: the insulating portion
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`surrounding the conductive center portion of said vertical interconnects comprises a dielectric
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`material having a stress of 5 X 108 dynes/cmz or less; one of the substantially flexible integrated
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`circuits is formed using a different process technology than another of the substantially flexible
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`l7
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`MICRON ET AL. EXHIBIT 1031
`Page 17 of 22
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`Serial No.
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`PATENT
`l2/405,240
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`integrated circuits, the different process technology being selected from a group consisting of
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`DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance; at
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`least one of substantially flexible integrated circuits comprises a microprocessor; the
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`substantially flexible integrated circuits comprise at least one memory integrated circuit and at
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`least one logic integrated circuit, wherein the at least one logic integrated circuit performs testing
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`of the at least one memory integrated circuit; a plurality of interior vertical interconnections
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`traverse at least one of the substantially flexible integrated circuits; continuous vertical
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`interconnections connect circuitry of the substantially flexible integrated circuits; information
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`processing is performed on data routed between circuitry on different ones the substantially
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`flexible integrated circuits; at least one substantially flexible integrated circuit has
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`reconfiguration circuitry; vertical interconnects connect the circuit substrate and circuitry of a
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`first substantially flexible integrated circuit, each vertical interconnect comprising a conductive
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`center portion and a insulating portion surrounding the conductive center portion, the insulating
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`ortion com risin a dielectric havin stress of 5 x 108 d nes/cm2 or less; at least one of the
`P
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`Y
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`substantially flexible integrated circuits comprises a dielectric layer with a stress of about 5 x
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`lO8 dynes/cmz or less.
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`20. The apparatus of claim 17, wherein at least two of the following: the insulating portion
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`surrounding the conductive center portion of said vertical interconnects comprises a dielectric
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`material having a stress of 5 x 108 dynes/cmz or less; one of the substantially flexible integrated
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`circuits is formed using a different process technology than another of the substantially flexible
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`integrated circuits, the different process technology being selected from a group consisting of
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`DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance; at
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`least one of substantially flexible integrated circuits comprises a microprocessor; the
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`18
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`MICRON ET AL. EXHIBIT 1031
`Page 18 of 22
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`

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`PATENT
`Serial No. 12/405,240
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`substantially flexible integrated circuits comprise at least one memory integrated circuit and at
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`least one logic integrated circuit, wherein the at least one logic integrated circuit performs testing
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`of the at least one memory integrated circuit; a plurality of interior vertical interconnections
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`traverse at least one of the substantially flexible integrated circuits; continuous vertical
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`interconnections connect circuitry of the substantially flexible integrated circuits; information
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`processing is performed on data routed between circuitry on different ones the substantially
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`flexible integrated circuits; at least one substantially flexible integrated circuit has
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`reconfiguration circuitry; vertical interconnects connect the circuit substrate and circuitry of a
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`first substantially flexible integrated circuit, each vertical interconnect comprising a conductive
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`center portion and a insulating portion surrounding the conductive center portion, the insulating
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`portion comprising a dielectric having stress of 5 x 108 dynes/cm2 or less; at least one of the
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`substantially flexible integrated circuits comprises a dielectric layer with a stress of about 5 x
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`108 dynes/cmz or less.
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`21. The apparatus of claim 17, wherein at least three of the following: the insulating portion
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`surrounding the conductive center portion of said vertical interconnects comprises a dielectric
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`material having a stress of 5 x 108 dynes/cmz or less; one of the substantially flexible integrated
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`circuits is formed using a different process technology than another of the substantially flexible
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`integrated circuits, the different process technology being selected from a group consisting of
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`DRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance; at
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`least one of substantially flexible integrated circuits comprises a microprocessor; the
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`substantially flexible integrated circuits comprise at least one memory integrated circuit and at
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`least one logic integrated circuit, wherein the at least one logic integrated circuit performs testing
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`of the at least one memory integrated circuit; a plurality of interior vertical interconnections
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`19
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`MICRON ET AL. EXHIBIT 1031
`Page 19 of 22
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`

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`PATENT
`Serial No. 12/405,240
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`traverse at least one of the substantially flexible integrated circuits; continuous Vertical
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`interconnections connect circuitry of the substantially flexible integrated circuits; information
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`processing is performed on data routed between circuitry on different ones the substantially
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`flcxiblc integrated circuits; at least one substantially flcxiblc integrated circuit has
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`reconfiguration circuitry; Vertical interconnects connect the circuit substrate and circuitry of a
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`first substantially flexible integrated circuit, each Vertical interconnect comprising a conductive
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`center portion and a insulating portion surrounding the conductive center portion, the insulating
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`portion comprising a dielectric having stress of 5 x 108 dynes/cmz or less; at least one of the
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`substantially flexible integrated circuits comprises a dielectric layer with a stress of about 5 x
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`108 dynes/cmz or less.
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`MICRON ET AL. EXHIBIT 1031
`Page 20 of 22
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`

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`PATENT
`Serial No. 12/405,240
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`EVIDENCE APPENDIX
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`MICRON ET AL. EXHIBIT 1031
`Page 21 of 22
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`

`
`PATENT
`Serial No. 12/405,240
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`RELATED PROCEEDINGS APPENDIX
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`MICRON ET AL. EXHIBIT 1031
`Page 22 of 22