IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
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`Title of Invention:
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`Three dimensional structure memory
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`Commissioner for Patents
`P.O. Box 1450
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`Alexandria, VA 22313-1450
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`Sir:
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`RESPONSE
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`Responsive to the prior Office Action, please amend this application as follows.
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`MICRON ET AL. EX'H]BIT 1030
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`Page 1 of 12
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`IN THE CLAIMS:
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`l. (Currently amended) A stacked integrated circuit comprising:
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`a plurality of substantially flexible integrated circuits having topside and
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`bottom-side surfaces, wherein said integrated circuits are stacked in relation to
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`one another, wherein at least one of the substantially flexible integrated circuits comprises
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`a substantially flexible semiconductor substrate made from a semiconductor wafer
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`thinned by at least one of abrasion, etching and parting to expose a surface, and
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`subscgucntly polishing the exposed surface to form a polished surface
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`; and
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`interconnections electrically connecting the plurality of substantially
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`flexible integrated circuits, wherein the interconnections are formed only on said
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`surfaces.
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`2. (Previously presented) The apparatus of claim l, wherein at least one of the plurality of
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`substantially flexible integrated circuits has a thickness of one of 10 microns or less and 50
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`microns or less.
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`3. (Previously presented) The apparatus of claim l, wherein at least one of the plurality of
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`substantially flexible integrated circuits comprises one of a single crystal semiconductor
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`material and a polycrystalline semiconductor material.
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`4. (Previously presented) The apparatus of claim l, wherein the plurality of substantially
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`flexible integrated circuits comprise one of a logic integrated circuit and a memory integrated
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`circuit.
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`MICRON ET AL. EXHIBIT 1030
`Page 2 of 12
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`5. (Original) The apparatus of claim 4, wherein the logic integrated circuit is a
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`microprocessor integrated circuit.
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`6. (Previously presented) The apparatus of claim l, wherein the plurality of substantially
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`flexible integrated circuits comprise logic integrated circuits.
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`7. (Previously presented) The apparatus of claim l, wherein at least two of the
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`interconnections electrically interconnecting the plurality of substantially flexible integrated
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`circuits are vertical interconnections.
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`8. (Previously presented) The apparatus of claim l, wherein at least one of the plurality of
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`substantially flexible integrated circuits is formed with a low stress dielectric.
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`9. (Previously presented) The apparatus of claim 8, wherein the low stress dielectric is at
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`least one of a silicon dioxide dielectric, an oxide of silicon dielectric and caused to have a
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`stress of about 5 x 108 dynes/cmz or less.
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`10. (Previously presented)
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`The apparatus of claim 1, wherein at least two of: at least
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`one of the substantially flexible integrated circuits comprises dielectric having a stress of
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`about 5 x 108 dynes/cmz or less; the dielectric is at least one of silicon dioxide and an
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`oxide of silicon; at least one of the substantially flexible integrated circuits has one of
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`logic circuitry and memory circuitry formed thereon; at least one conductive path passes
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`MICRON ET AL. EXHIBIT 1030
`Page 3 of 12
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`through a substrate of a substantially flexible integrated circuit and is insulated by an
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`insulation material from said substrate.
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`11. (Previously presented)
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`The apparatus of claim 1, wherein at least three of: at least
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`one of the substantially flexible integrated circuits comprises dielectric having a stress of
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`about 5 x 108 dynes/cmz or less; the dielectric is at least one of silicon dioxide and an
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`oxide of silicon; at least one of the substantially flexible integrated circuits has one of
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`logic circuitry and memory circuitry formed thereon; at least one conductive path passes
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`through a substrate of a substantially flexible integrated circuit and is insulated by an
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`insulation material from said substrate.
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`12. (Previously presented)
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`The apparatus of claim 1, wherein at least four of: at least
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`one of the substantially flexible integrated circuits comprises dielectric having a stress of
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`about 5 x 108 dynes/cmz or less; the dielectric is at least one of silicon dioxide and an
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`oxide of silicon; at least one of the substantially flexible integrated circuits has one of
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`logic circuitry and memory circuitry formed thereon; at least one conductive path passes
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`through a substrate of a substantially flexible integrated circuit and is insulated by an
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`insulation material from said substrate.
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`l3. (Previously presented)
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`The apparatus of claim 1. comprising at least one
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`conductive path that passes through a substrate of a substantially flexible integrated
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`MICRON ET AL. EXHIBIT 1030
`Page 4 of 12
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`circuit and is insulated by an insulation material from said substrate, wherein said
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`substrate is a monocrystalline semiconductor substrate.
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`14. (Previously presented)
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`The apparatus of claim 1, wherein the bottom-side surface
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`of at least one of the plurality of substantially flexible integrated circuits is polished.
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`15. (Previously presented)
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`The apparatus of claim 1, wherein data processing is
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`performed by at least two of the substantially flexible integrated circuits in cooperation
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`with one another.
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`l6. (Previously presented)
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`The apparatus of claim 1, further comprising:
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`a memory array having a plurality of memory cells, a plurality of data lines, and a
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`plurality of gate lines, each memory cell storing a data value and comprising circuitry for
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`coupling that data value to one of said data lines in response to a gate control signal on
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`one of said gate lines;
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`circuitry for generating a gate control signal in response to an address, including
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`means for mapping addresses to gate lines; and
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`a controller for determining that one of said memory cells is defective and for
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`altering said mapping to eliminate references to said one of said memory cells.
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`MICRON ET AL. EXHIBIT 1030
`Page 5 of 12
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`17. (Previously presented) The apparatus of claim 1, wherein said interconnects comprise
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`a plurality of vertical interconnects, each of said vertical interconnects comprising a
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`conductive center portion and an insulating portion surrounding the conductive center
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`portion.
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`18. (Previously presented) The apparatus of claim 17, wherein the insulating portion
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`surrounding the conductive center portion of said vertical interconnects comprises a
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`dielectric material having a stress of 5 x 108 dynes/cmz or less.
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`19. (Previously presented) The apparatus of claim 17, wherein at least one of the
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`following: the insulating portion surrounding the conductive center portion of said
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`vertical interconnects comprises a dielectric material having a stress of 5 x 108 dynes/cmz
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`or less; one of the substantially flexible integrated circuits is formed using a different
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`process technology than another of the substantially flexible integrated circuits, the
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`different process technology being selected from a group consisting of DRAM, SRAM,
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`FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance; at least one of
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`substantially flexible integrated circuits comprises a microprocessor; the substantially
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`flexible integrated circuits comprise at least one memory integrated circuit and at least
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`one logic integrated circuit, wherein the at least one logic integrated circuit performs
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`testing of the at least one memory integrated circuit; a plurality of interior vertical
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`interconnections traverse at least one of the substantially flexible integrated circuits;
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`continuous vertical interconnections connect circuitry of the substantially flexible
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`integrated circuits; information processing is performed on data routed between circuitry
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`MICRON ET AL. EXHIBIT 1030
`Page 6 of 12
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`on different ones the substantially flexible integrated circuits; at least one substantially
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`flexible integrated circuit has reconfiguration circuitry; vertical interconnects connect the
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`circuit substrate and circuitry of a first substantially flexible integrated circuit, each
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`vertical interconnect comprising a conductive center portion and a insulating portion
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`surrounding the conductive center portion, the insulating portion comprising a dielectric
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`having stress of 5 x 108 dyncs/cmz or less; at least one of the substantially flexible
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`integrated circuits comprises a dielectric layer with a stress of about 5 x l08 dynes/cmz or
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`less.
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`20. (Previously presented) The apparatus of claim 17, wherein at least two of the
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`following: the insulating portion surrounding the conductive center portion of said
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`vertical interconnects comprises a dielectric material having a stress of 5 x 108 dynes/cmz
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`or less; one of the substantially flexible integrated circuits is formed using a different
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`process technology than another of the substantially flexible integrated circuits, the
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`different process technology being selected from a group consisting of DRAM, SRAM,
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`FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance; at least one of
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`substantially flexible integrated circuits comprises a microprocessor; the substantially
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`flexible integrated circuits comprise at least one memory integrated circuit and at least
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`one logic integrated circuit, wherein the at least one logic integrated circuit performs
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`testing of the at least one memory integrated circuit; a plurality of interior vertical
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`interconnections traverse at least one of the substantially flexible integrated circuits;
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`continuous vertical interconnections connect circuitry of the substantially flexible
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`integrated circuits; information processing is performed on data routed between circuitry
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`MICRON ET AL. EXHIBIT 1030
`Page 7 of 12
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`on different ones the substantially flexible integrated circuits; at least one substantially
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`flexible integrated circuit has reconfiguration circuitry; vertical interconnects connect the
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`circuit substrate and circuitry of a first substantially flexible integrated circuit, each
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`vertical interconnect comprising a conductive center portion and a insulating portion
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`surrounding the conductive center portion, the insulating portion comprising a dielectric
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`having stress of 5 x 108 dyncs/cmz or less; at least one of the substantially flexible
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`integrated circuits comprises a dielectric layer with a stress of about 5 x l08 dynes/cmz or
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`less.
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`21. (Previously presented) The apparatus of claim 17, wherein at least three of the
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`following: the insulating portion surrounding the conductive center portion of said
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`vertical interconnects comprises a dielectric material having a stress of 5 x 108 dynes/cmz
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`or less; one of the substantially flexible integrated circuits is formed using a different
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`process technology than another of the substantially flexible integrated circuits, the
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`different process technology being selected from a group consisting of DRAM, SRAM,
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`FLASH, EPROM, EEPROM, Ferroelectric and Giant Magneto Resistance; at least one of
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`substantially flexible integrated circuits comprises a microprocessor; the substantially
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`flexible integrated circuits comprise at least one memory integrated circuit and at least
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`one logic integrated circuit, wherein the at least one logic integrated circuit performs
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`testing of the at least one memory integrated circuit; a plurality of interior vertical
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`interconnections traverse at least one of the substantially flexible integrated circuits;
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`continuous vertical interconnections connect circuitry of the substantially flexible
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`integrated circuits; information processing is performed on data routed between circuitry
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`MICRON ET AL. EXHIBIT 1030
`Page 8 of 12
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`on different ones the substantially flexible integrated circuits; at least one substantially
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`flexible integrated circuit has reconfiguration circuitry; Vertical interconnects connect the
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`circuit substrate and circuitry of a first substantially flexible integrated circuit, each
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`Vertical interconnect comprising a conductive center portion and a insulating portion
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`surrounding the conductive center portion, the insulating portion comprising a dielectric
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`having stress of 5 x 108 dyncs/crnz or less; at least one of the substantially flexible
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`integrated circuits comprises a dielectric layer with a stress of about 5 x l08 dynes/cmz or
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`less.
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`MICRON ET AL. EXHIBIT 1030
`Page 9 of 12
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`REMARKS
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`The prior Office Action has been carefully considered. Reconsideration and
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`allowance in View of the present remarks is respectfully requested.
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`Claims 1-21 were rejected as being anticipated by or unpatcntablc ovcr Lccdy.
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`The claims have been amended to more clearly distinguish over the cited reference.
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`Reconsideration is respectfully requested.
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`In particular, the claims have been amended to recite in part a substantially
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`flexible semiconductor substrate. No such feature is taught or suggested by Leedy.
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`Leedy (FIG. 8) discloses a flexible layer made up of a huge number of tiny
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`semiconductor islands embedded within dielectric. Each semiconductor island
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`corresponds to a device such as a transistor. That flexible layer is not believed to be a
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`“substrate” within the reasonable commonly-accepted meaning of that term. Certainly
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`that flexible layer cannot be considered to be a “semiconductor substrate,” since
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`structural integrity of the flexible layer, which is the function of a substrate to provide,
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`derives not from semiconductor material but rather from dielectric material.
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`Considering a single one of the tiny islands of semiconductor material, nor is such
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`an island believed to be a “substrate” within the reasonable commonly-accepted meaning
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`MICRON ET AL. EXHIBIT 1030
`Page 10 of 12
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`of that ter1n. Moreover, given the minute dimensions of such an island, the island of
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`semiconductor itself is not flexible as claimed; rather, it is rigid.
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`Accordingly, the claims as amended are believed to patentably define over the
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`cited references.
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`Moreover, numerous features of the claims alleged to be shown by Leedy are not
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`in fact shown by Leedy. None of the features relating to memory integrated circuits are
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`believed to be taught or suggested by Leedy. That is, while Leedy may teach one
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`particular embodiment of a stacked integrated circuit (FIG. 8), it does not teach or
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`suggest numerous features of the claims as they relate to memory.
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`Leedy (FIG. 31b) does teach “control and/or memory logic 712, 713
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`fabricated
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`as part of [an] MDI circuit membrane display 700.” This embodiment of Leedy is
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`unrelated to the stacked integrated circuit embodiment of FIG. 8 of Leedy. Beyond this
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`bare mention of memory fabricated as part of a planar display, Leedy does not contain
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`any teachings relevant to the memory features of the present claims.
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`MICRON ET AL. EXHIBIT 1030
`Page 11 of 12
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`Withdrawal of the rejections and allowance of claims 1-21 is respectfillly
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`requested.
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`Respectfully submitted,
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`/Michael J. Ure/
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`Michael J. Ure, Reg. 33,089
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`Dated: 9/4/2012
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`MICRON ET AL. EXHIBIT 1030
`Page 12 of 12