Filing or 371 (C) Date:
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`Application Typc:
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`Examiner Name:
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`Group Art Unit:
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`Attorney Docket Number:
`Class / Subclass:
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`First Named Inventor:
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`\\ \\ .2 .
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`09-26-2003
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`Utility
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`LEWIS, MONICA
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`2822
`9439
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`ELM-2 CONT. 4
`43 8/238
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`Glenn Leedyw, Saline, MI
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`Three dimensional multi layer memory and control logic
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`integrated circuit structure
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`Commissioner for Patents
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`P.O. Box 1450
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`Alexandria, VA 223l3—l450
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`Sir:
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`RESPONSE
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`Rcsponsivc to the Office Action of 04/24/2009, plcasc amend this application as
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`follows.
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`MICRON ET AL. EXHIBIT 1029
`Page 1 of 15
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`IN THE CLAIMS
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`l-87. (Canceled)
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`88.
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`(Currently Amended) An integrated circuit structure comprising:
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`a first substrate comprising a first surface having interconnect contacts
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`and
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`a thinned second substrate comprising a first surface and a second sttrtace
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`each having interconnect contacts ’ ‘ *‘
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`. wherein the second surlace is U 3 Josile
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`the iirst Stll‘iilCC Zil1CiM\\.‘i‘tCl'Cil} the SeCong_§“t:Lij}1ce oiithe second substrate is polished; and
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`onductive paths between the
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`interconnect contacts of the first surfaces of the first substrate and said one (‘>i'I‘i1t’.‘ first
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`SllI‘i’1lCC otthc second substrate and the second stii'i2»tc<: ol’t’ltc sccontl substrate.~.~«\-¢li<=+ei+s
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`wherein the iirst surlace olthe first substrate and one ol"thc iirstfi sttt'lacq__Q_l_'
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`the second substrate and the second surfitcc of the second substrate are bonded, the first
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` substrate overlapping at leasta majority of the fia=st-sur~t”~aee—ef3—t~he
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`A
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`89.
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`(Withdrawn) The apparatus ofclaim 88, wherein the second
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`substrate is one ofa thinned monocrystalline semiconductor substrate and a thinned
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`polycrystalline semiconductor substrate.
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`90.
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`(Withdrawn) The apparatus of claim 88, wherein the circuitry
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`formed on the second substrate is one of active circuitry and passive circuitry.
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`91.
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`(Withdrawn) The apparatus ofclaim 88, wherein the circuitry
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`formed on the second substrate consists of both active circuitry and passive circuitry.
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`92.
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`(Withdrawn) The apparatus ofclaim 88, wherein the first substrate
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`is a substrate having circuitry formed thereon.
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`MICRON ET AL. EXHIBIT 1029
`Page 2 of 15
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`93.
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`(Withdrawn) The apparatus of claim 92, wherein the circuitry of
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`the first substrate is one of active circuitry and passive circuitry.
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`(Withdrawn) The apparatus of claim 92, wherein the circuitry of
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`the first substrate comprises both active circuitry and passive circuitry.
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`95.
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`(Previously Presented) The structure of claim 88, further
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`at least one additional thinned substrate having circuitry formed thereon;
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`a first of said at least one additional thinned substrate being bonded to the
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`second substrate and any additional thinned substrates being bonded to the directly
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`adjacent additional thinned substrate; and
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`conductive paths formed between said first of said at least one additional '
`thinned substrate and at least one of said first and second substrates and also between
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`each additional thinned substrate and at least one of said substrates of the integrated
`circuit structure.
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`96.
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`(Withdrawn) The apparatus ofclaim 95, wherein at least two of the
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`first, the second and the at least one additional thinned substrates are formed using a
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`different process technology, wherein the different process technology is selected from
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`the group consisting ofDRAM, SRAM, FLASH, EPROM, EEPROM, Ferroelectric and
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`Giant Magneto Resistance.
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`97.
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`(Withdrawn) The apparatus ofclaim 95, wherein at least one ofthe
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`first, the second and the at least one additional thinned substrates comprises a
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`microprocessor.
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`98.
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`(Withdrawn) The apparatus ofclaim 95, wherein:
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`at least one substrate of the first, the second and the at least one additional
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`thinned substrates has memory circuitry formed thereon; and
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`at least one substrate of the first, the second and the at least one additional
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`thinned substrates has logic circuitry formed thereon that performs tests on the at least
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`one substrate that has memory circuitry formed thereon.
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`MICRON ET AL. EXHIBIT 1029
`Page 3 of 15
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`99.
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`(Withdrawn) The apparatus of claim 95, wherein at least one
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`substrate of the first, the second and the at least one additional thinned substrates has
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`memory circuitry formed thereon, the memory circuitry having a plurality ofmemory
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`locations, wherein at least one memory location ofthe plurality of memory locations is
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`used for sparing and wherein data from the at least one memory location on the at least
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`one substrate having memory circuitry formed thereon is used instead of data from a
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`defective memory location on the at least one substrate that has memory circuitry formed
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`thereon.
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`I00.
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`(Withdrawn) The apparatus ofclaim 95, wherein:
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`at least one substrate of the first, the second and the at least one additional
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`thinned substrates has memory circuitry formed thereon; and
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`at least one substrate of the first, the second and the at least one additional
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`thinned substrates has logic circuitry formed thereon that performs programmable gate
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`line address assignment with respect to the at least one substrate having memory circuitry
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`101.
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`(Withdrawn) The apparatus ofclaim 95, further comprising a
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`plurality of interior vertical interconnections that traverse at least one of the first, the
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`I02.
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`(Withdrawn) The apparatus of claim 95, wherein infonnation
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`processing is performed on data routed between the circuitry of at least two of the first,
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`103.
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`(Withdrawn) The apparatus ofclaim 95, wherein at least one ofthe
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`first, the second and the at least one additional thinned substrates has reconfiguration
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`circuitry.
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`104.
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`(Withdrawn) The apparatus ofclaim 95, wherein at least one ofthe
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`first, the second, and the at least one additional thinned substrates has logic circuitry
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`formed thereon for performing at least one function from the group consisting of: virtual
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`memory management, ECC, indirect addressing, content addressing, data compression,
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`MICRON ET AL. EXHIBIT 1029
`Page 4 of 15
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`data decompression, graphics acceleration, audio encoding, audio decoding, video
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`encoding, video decoding, voice recognition, handwriting recognition, power
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`management and database processing.
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`105.
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`(Withdrawn) The apparatus ofclaim 95, further comprising:
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`a memory array having a plurality ofmemory storage cells, a plurality of
`data lines, and a plurality ofgate lines, each memory storage cell stores a data value and
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`has circuitry for coupling the data value to one ofthe plurality of data lines in response to
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`receiving a gate control signal from one ofthe plurality ofgate lines;
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`circuitry that generates the gate control signal in response to receiving an
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`address, including means for mapping addresses to gate lines; and
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`a controller that determines if one of the plurality of memory cells is
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`defective and alters said mapping to remove references to the one of the plurality of
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`memory cells that is defective.
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`106.
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`(Previously Presented) The structure of claim 95, further
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`substrate;
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`at least one controller substrate having logic circuitry formed thereon;
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`at least one memory substrate having memory circuitry formed thereon;
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`a plurality ofdata lines and a plurality ofgate lines on each memory
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`an array of memory cells on each memory substrate, each memory cell
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`stores a data value and has circuitry that couples the data value to one of the plurality of
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`data lines in response to selecting one ofthe plurality ofgate lines;
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`a gate line selection circuit that enables a gate line for a memory
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`operation, wherein the gate line selection circuit has programmable gates to receive
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`address assignments for at least one gate line ofthe plurality ofgate lines and wherein the
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`address assignments for determining which ofthe plurality ofgate lines is selected for
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`each programmed address assignment; and
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`controller substrate logic that determines if one memory cell of the array
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`of memory cells is defective and alters the address assignments of the plurality of gate
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`MICRON ET AL. EXHIBIT 1029
`Page 5 of 15
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`lines to remove references to the gate line that causes the defective memory cell to Couple
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`a data value to one ofthe plurality ofdata lines.
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`controller substrate logic:
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`107.
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`(Previously Presented) The structure of claim 106, wherein the
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`tests the array of memory cells periodically to determine if one of the
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`array ofmemory cells is defective; and
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`removes references in the address assignments to gate lines that cause
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`detected defective memory cells to couple data values to the plurality of data lines.
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`108.
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`(Previously Presented) The structure of claim 106, further
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`programmable logic to prevent the use of data values from the plurality of
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`data lines when gate lines cause detected defective memory cells to couple data values to
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`the plurality ofdata lines.
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`109.
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`(Previously Presented) The structure ofclaim 106, wherein the
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`array of memory cells are arranged within physical space in a physical order and are
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`arranged within an address space in a logical order and wherein the physical order of at
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`least one memory cell is different than the logical order ofthe at least one memory cell.
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`1 10.
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`(Previously Presented) The structure of claim 106, wherein:
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`the logic circuitry of the at least one controller substrate is tested by an
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`external means; and
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`the array of memory cells of the at least one memory substrate are tested
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`by the logic circuitry of the at least one controller substrate, wherein the testing achieves ’
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`a functional testing ofa substantial portion ofthe array of memory cells.
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`(Previously Presented) The structure ofclaim lO6, wherein the
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`logic circuitry ofthe at least one controller substrate performs functional testing ofa
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`substantial portion ofthe array ofmemory cells.
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`(Previously Presented) The structure ofclaim 106, wherein the
`I I2.
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`controller substrate logic is further configured to:
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`MICRON ET AL. EXHIBIT 1029
`Page 6 of 15
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`replace references to memory cells addressed using the defective gate line
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`with references to spare memory cells addressed using a spare gate line.
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`I 13.
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`circuitry of the at least one controller substrate [:)1‘:‘~i‘~li1~)l~‘l‘HSC‘c\l) perform all functional testing
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`I 14.
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`of the array of memory cells of the at least one memory substrate.
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`115.
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`(Withdrawn) The apparatus of claim 88, wherein the first substrate
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`I 16.
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`(Currently Amended) An integrated circuit structure comprising:
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`a first substrate having topside and bottomside surfaces, wherein the
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`topside surface of the first substrate has interconnect contacts ;
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`a thinned second substrate having topside and bottomside surfaces,
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`wherein the to aside surface and the bottomside surface of thesecond substrate
`interconnect contacts . and wherein the bottomside sixrface ofthe second
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`.substrate is mlishccl;
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`wherein at mafor onion old‘
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`‘ the topside surface of the first substrate
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`and one ofthc Io .')Sltlt3 siirl}-iicc ofihc second siihslmtc and the botmmsitlc surliicc ol‘t|*n:
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`second substrate are honclccl tog_cll1ci'; and
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`conductive paths l%>r—meel~between the interconnect contacts on the topside
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`ofthe first substrate and ;2_z_1_i_c_l__onc oI’i,hc imsicle si,ii-lace ol'ihc sccoiicl substrate 4
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`and the bottomside surface of the second substrate, the conductive paths providing
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`electrical connections between the first substrate and the second substrate;«~whei=ein—+he
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`lii'st~sabst~.Hi«1e-»is rat~leasH~»4ee—as4~hic~l+a+Hl1e~seeonei~sHlastratea;_
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`wherein the
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`substrate overlapping
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`0\’€l‘l€lpS
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`at least a majority ofthe 1
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`MICRON ET AL. EXHIBIT 1029
`Page 7 of 15
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`1 l7.
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`(Currently Amended) The integrated circuit structure ofclaim l 16,
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`wherein selected ones of said interconnect contacts said topside surface of said first
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`substrate are in electrical contact with selected ones of the interconnect contacts F.-)l}»-tfli
`said bottomside surface of said second substrate so as to form said electrical connections.
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`I l8.
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`(Currently Amended) An integrated circuit structure comprising:
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`a first substrate having a first and second surface;
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`a second substrate having a first and second surface, wherein said second
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`surfaces of the first and second substrates are opposite to said first surfaces;
`\\«'hcrcin at least one of the first substrate and the SCC()l1d substrate is
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`1.lti..nn..c_c_l__t_«;~. Wm 211. least 9.00 IhiI_m_s:d strlvstttiattst, '~‘1!1£l.‘_El_l€Ft2,l_t1-ll3.s:_$§9$n1§l..fiflllffiflflifi
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`least one thinned stibstrate
`nolishedz
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`9-wherein the first surface ofthe first
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`substrate and a maior portion ofonc oi” the first surface of the second substrate and the
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`second surl'2icc oflhe second substrate are bonded lw at least one bond.‘ wherein the at
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`least one bond secures a ma’or aortion of the second substrate to the first substrate; and
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`conductive paths ¥em+ed~enl)etween at least two of‘ the first surfaces of the
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`first substrate and the first and second sttrfag_e_g_9t“ the second substrates,
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`, wliercin the first
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`seeandsubstrate ovei‘|ap. 5 at least a majority ofthe
`second substrate.
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`119.
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`(Previously Presented) The structure of claim 116, further
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`at least one additional thinned substrate having circuitry formed thereon;
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`a first of said at least one additional thinned substrate being bonded to the
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`second substrate and any additional thinned substrates being bonded to the directly
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`adjacent additional thinned substrate; and
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`conductive paths formed between said first of said at least one additional
`thinned substrate and at least one of said first and second substrates and also between
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`MICRON ET AL. EXHIBIT 1029
`Page 8 of 15
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`each additional thinned substrate and at least one of said substrates of the integrated
`circuit structure.
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`I20.
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`(Previously Presented) The structure ofclaim I 19, further
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`comprising:
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`substrate;
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`at least one controller substrate having logic circuitry formed thereon;
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`at least one memory substrate having memory circuitry formed thereon;
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`a plurality ofdata lines and a plurality ofgate lines on each memory
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`an array of memory cells on each memory substrate, each memory cell
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`stores a data value and has circuitry that couples the data value to one of the plurality of
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`data lines in response to selecting one of the plurality of gate lines;
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`a gate line selection circuit that enables a gate line for a memory
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`operation, wherein the gate line selection circuit has programmable gates to receive
`address assignments for at least one gate line of the plurality of gate lines and wherein the.
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`address assignments for determining which ofthe plurality of gate lines is Selected for
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`each programmed address assignment; and
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`controller substrate logic that determines ifone memory cell ofthe array
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`of memory cells is defective and alters the address assignments of the plurality of gate
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`lines to remove references to the gate line that causes the defective memory cell to couple
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`a data value to one ofthe plurality of data lines.
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`121.
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`(Previously Presented) The structure ofclaim 120, wherein the
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`controller substrate logic:
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`tests the array ofmemory cells periodically to determine ifone of the
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`array of memory cells is defective; and
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`removes references in the address assignments to gate lines that cause
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`detected defective memory cells to couple data values to the plurality ofdata lines.
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`I22.
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`(Previously Presented) The structure ofclaim 120, further
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`comprising:
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`programmable logic to prevent the use of data values from the plurality of
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`MICRON ET AL. EXHIBIT 1029
`Page 9 of 15
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`data lines when gate lines cause detected defective memory cells to couple data values to
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`the plurality ofdata lines.
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`(Previously Presented) The structure of claim 120, wherein the
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`array of memory cells are arranged within physical space in a physical order and are
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`l23.
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`arranged within an address space in a logical order and wherein the physical order of at
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`least one memory cell is different than the logical order ofthe at least one memory cell.
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`124.
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`(Previously Presented) The structure ofclaim I20, wherein:
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`the logic circuitry of the at least one controller substrate is tested by an
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`external means; and
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`the array of memory cells of the at least one memory substrate are tested
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`by the logic circuitry of the at least one controller substrate, wherein the testing achieves
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`a functional testing of a substantial portion of the array of memory cells.
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`125.
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`(Previously Presented) The structure ofclaim 120, wherein the
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`logic circuitry of the at least one controller substrate performs functional testing of a
`substantial portion of the array of memory cells.
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`(Previously Presented) The structure ofclaim 120, wherein the
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`controller substrate logic is further configured to:
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`126.
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`prevent the use of at least one defective gate line; and
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`replace references to memory cells addressed using the defective gate line
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`with references to spare memory cells addressed using a spare gate line.
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`127.
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`(Previously Presented) The structure ofclaim 120, wherein the
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`controller substrate logic is further configured to prevent the use of at least one defective
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`gate line.
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`128.
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`(Currently amended) The structure ofclaim 120, wherein the logic
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`circuitry of the at least one controller substrate peniartmscan perlorm all functional testing
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`ofthe array of memory cells ofthe at least one memory substrate.
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`MICRON ET AL. EXHIBIT 1029
`Page 10 of 15
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`(New) The structure of claim 88, wherein the second substrate is
`thinned to about 50 microns or less.
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`129.
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`(New) The structure of claim 116, wherein the second substrate is
`thinned to about 50 microns or less.
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`130.
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`(New) The structure of claim 118, wherein the second substrate is
`thinned to about 50 microns or less.
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`131.
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`l32.
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`(New) The structure of claim 88, wherein the first substrate and the
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`second substrate are the same size or overlap each other completely.
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`(New) The structure of claim l 16, wherein the first substrate and
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`the second substrate are the same size or overlap each other completely.
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`I33.
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`l34.
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`(New) The structure of claim 1 18, wherein the first substrate and
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`the second substrate are the same size or overlap each other completely.
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`MICRON ET AL. EXHIBIT 1029
`Page 11 of 15
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`REMARKS
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`The Office Action of 04/24/2009 has been carefully considered.
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`Claims 110 and 124 were indicated as containing allowable subject matter, which
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`indication is apprcciatively acknowledged.
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`Claims 88, 95 and 116-119 were rej ected as being unpatentable over Sugiyama in
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`View of Watanabe (newly cited) and filI'1lhCI' in View of Leedy. (Although page 3 of the
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`rejection refers only to Sugiyama and Watanabe, page 4 of the rejection refers also to
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`Leedy. The omission from Leedy in the initial statement of the rejection is therefore
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`believed to be in error.) Claims 106-108, 111-114, 120-122 and 125-128 were rejected as
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`being unpatentable over the same base combination further in View of Faris and Sakui.
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`Claims 109 and 123 were rejected as being unpatentable over the prior combination
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`further in View of Daberko. The claims have been amended to more clearly distinguish
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`over the cited references. Dependent claims 129-134 have been newly added.
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`Reconsideration is respectfully requested.
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`More particularly, independent claims 88, 116, and 118 have been amended to
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`recite in part a thinned substrate having a polished surface. Surface polishing achieves
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`stress relief and provides a smooth surface for the formation of interconnect
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`metallization. None of the cited references is believed to teach or suggest such surface
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`polishing with respect to a thinned substrate. All of the claims are therefore believed to be
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`allowable over the prior art for at least this reason.
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`With respect to the prior obviousness rejection, although this rejection is believed
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`to be no longer applicable, it is also believed to be significantly flawed, as set forth
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`MICRON ET AL. EXHIBIT 1029
`Page 12 of 15
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`Rejection 0[ Claims 88, 95 and 116-119 as Ungatentable Over Sugiyama in View of
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`Watanabe Further in View of Leedy
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`In the prior Office Action, the claims were rejected as being unpatentable over
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`Sugiyama in view of Leedy. The purported motivation for combining the teachings of
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`Sugiyama and Leedy was “to provide structural integrity.” In the prior Response,
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`Applicant disputed this motivation as lacking technical merit. This argument was
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`apparently found to be persuasive, resulting in the present Office Action in which the
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`claims are rejected as being unpatentable over Sugiyama in View of Watanabe further in
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`view of Leedy.
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`However, the same supposed motivation for combining the teachings of Leedy
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`with those of Sugiyama and Watanabe is cited—“to provide structural integrity.” This
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`motivation is believed to be technically unsound for the reasons set forth in the prior
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`reply. That is, the substrates of Sugiyama are, to all indications, of ordinary thickness
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`(e.g., 300-500 microns).Thc structural integrity of substrates of such ordinary thickness
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`without the need of any further measures is well-established and demonstrated. Hence,
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`contrary to the rejection, Sugiyama has no need of the techniques of Leedy for ensuring
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`structural integrity of a thinned substrate or IC membrane.
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`Furthermore, the problem of proper motivation to combine has only been
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`compounded with the proposed additional combination of Watanabe. Watanabe teaches a
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`technique for making an IC assembly having two ICs made of dissimilar semiconductor
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`materials, namely silicon and gallium arsenide. The silicon wafer is thinned and adhered
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`to a sapphire wafer. Following dicing, a relatively small gallium arsenide IC is bonded to
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`the silicon IC. The sapphire substrate provides thermal matching.
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`The Watanabe technique is wholly inapplicable to Sugiyama. Sugiyama teaches
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`the face—to—face bonding of two IC wafers. There is no opportunity for the bonding of a
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`further IC subsequent to dicing—the surfaces that might otherwise be bonded to are
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`internal to the Sugiyama structure. Without such subsequent bonding, there would be no
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`need for the thermal matching substrate, i.e., the sapphire substrate.
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`MICRON ET AL. EXHIBIT 1029
`Page 13 of 15
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`As no reasonable motivation has been identified for combining the teachings of
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`the references in the manner indicated, the cited references are not believed to teach or
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`suggest the invention of claim 88, particularly as it has now been amended to recite in
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`part a thinned substrate having a polished surface.
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`The same argument applies equally to claims 1 l6 and H9. Hence, it may be seen
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`that the cited references do not teach or suggest the invention of claims 88, 1 l6 or l 19.
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`Withdrawal of the rejection is respectfully requested.
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`The various combinations of references used to reject the dependent claims do
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`nothing to address the teachings absent from the base combination as noted above.
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`Therefore, the dependent claims are believed to be allowable as depending on an
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`allowable base claim.
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`Applicant further rcitcratcs that motivation to combine is not supplied merely by
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`two references being from the same field of endeavor (e.g., two integrated circuits). Ifa
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`proposed combination would make no reasonable sense to a person of ordinary skill in
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`the art, motivation to combine is necessarily lacking.
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`As there has been ample opportunity during prosecution of the present application
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`for a case of obviousness to be established (if the prior art will indeed support such a
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`finding), and since no primafacie case of obviousness is believed to have been
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`established, allowance of the present application is believed to be in order and is
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`respectfully requested.
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`MICRON ET AL. EXHIBIT 1029
`Page 14 of 15
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`Withdrawal of the rejections and allowance of claims 88, 95, 106-109, 111-114,
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`116-123 and 125-134 is respectfidlly requested.
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`Respectfully submitted,
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`/Michael J. Ure/
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`Michael J. Ure, Reg. 33,089
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`Dated: 6."25."2009
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`MICRON ET AL. EXHIBIT 1029
`Page 15 of 15